KR20100014675A - Non-volatile memory and method for compensation for voltage drops along a word line - Google Patents

Abstract

Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.

Description

NON-VOLATILE MEMORY AND METHOD FOR COMPENSATION FOR VOLTAGE DROPS ALONG A WORD LINE}

FIELD OF THE INVENTION The present invention generally relates to nonvolatile semiconductor memories such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM, and more particularly to memory in which variations along word lines are compensated for by an appropriate bit line voltage. It is about operation.

Solid state memory is capable of nonvolatile storage of charge, particularly in the form of EEPROMs and flash EEPROMs packaged as small form factor cards (SFFCs). Selected as a storage device in the field. Also, unlike RAM (random access memory), which is a solid state memory, flash memory is nonvolatile and data is stored even after the power is turned off. Despite the higher price, flash memory is increasingly being used in mass storage applications. Conventional mass storage based on rotating magnetic media such as hard drives and floppy disks is inadequate in mobile and handheld environments. This is because disk drives tend to be huge and are prone to mechanical failure and require high delay and high power. These undesirable attributes make disk based storage impractical in most mobile and portable applications. On the other hand, flash memory, in the form of an embedded and removable card, is ideally suited for mobile and handheld environments due to its small size, low power consumption, high speed and high reliability features.

EEPROMs and electrically programmable read-only memories (EPROMs) are nonvolatile memories that can be erased and " programmed " in their memory cells or to write new data. Both utilize a floating (not connected) conductive gate located over the channel region of the semiconductor substrate between the source and drain regions in the field effect transistor structure. The control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to allow for conduction between the source and drain regions.

The floating gate can hold a range of charges and can therefore be programmed to any threshold voltage level within the threshold voltage window. The magnitude of the threshold voltage window is defined by the minimum and maximum threshold levels of the device, which in turn correspond to the range of charges that can be programmed to the floating gate. The threshold window generally depends on the characteristics, operating conditions and history of the memory device. Each individual and resolvable threshold voltage level range within the window can generally be used to indicate the limited memory state of the cell. If the threshold voltage is divided into two separate regions, each memory cell may store one bit of data. Similarly, if the threshold voltage window is divided into more than two separate regions, each memory cell may store more than one bit of data.

In a typical two-state EEPROM cell, at least one current breakpoint level is identified to divide the connection window into two regions. When a cell is read by applying predetermined fixed voltages, its source / drain current is broken down into a memory state by comparing with the breakpoint level (or reference current I _REF ). If the current read is higher than the breakpoint level read, then the cell is determined to be in one logic state (eg, a "0" state). On the other hand, if the current is less than the breakpoint level current, it is determined that the cell is in a different logic state (eg, a "1" state). Thus, these two-state cells store one bit of digital information. An externally programmable reference current source is often provided as part of the memory system to generate breakpoint level currents.

In order to increase memory capacity, flash EEPROM devices are being manufactured at higher densities as the stage of semiconductor technology advances. Another way to increase storage capacity is to have each memory cell store more than two states.

For multi-state or multi-level EEPROM memory cells, the challenge window is divided into more than two regions by more than one breakpoint, so that each cell can store more than one bit of data. Thus, the information that a given EEPROM array can store increases with the number of states each cell can store. EEPROM or flash EEPROMs with multi-state or multi-level memory cells are described in US Pat. No. 5,172,338.

The transistor serving as the memory cell is typically programmed to a "programmed" state by one of two mechanisms. In "hot electron injection", the high voltage applied to the drain accelerates the electrons across the substrate channel region. At the same time, the high voltage applied to the control gate attracts hot electrons through the thin gate dielectric to the floating gate. In "tunneling injection", a high voltage is applied to the control gate for the substrate. In this way, electrons are drawn from the substrate to the intervening floating gate.

The memory device may be erased by a number of mechanisms. For EPROM, the memory can be bulk erased by removing the charge from the floating gate by ultraviolet light. For EEPROM, the memory cell applies a high voltage to the substrate with respect to the control gate to induce electrons in the floating gate to tunnel through the thin oxide (ie, Fowler-Nordheim tunneling). It is electrically erasable by applying. Typically, the EEPROM is erasable by one byte. For a flash EEPROM, the memory can electrically erase one or more blocks all at once or at one time, and one block may consist of more than 512 bytes of memory.

The memory device typically can include one or more memory chips that can be mounted on a card. Each memory chip includes an array of memory cells supported by peripheral circuits such as decoders, erase, write and read circuits. More sophisticated memory devices work with external memory controllers that perform intelligent and higher levels of memory operation and interfacing.

There are many commercially available nonvolatile solid state memory devices currently in use. These memory devices may be flash EEPROM or may use other forms of nonvolatile memory cells. Examples of flash memories and systems and their fabrication methods are described in US Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063 and 5,661,053, 5,313,421 and 6,222,762. In particular, flash memory devices having NAND string structures are described in US Pat. Nos. 5,570,315, 5,903,495, 6,046,935. In addition, nonvolatile memory devices are also fabricated from memory cells having a dielectric layer for storing charge. Instead of the conductive floating gate elements described previously, a dielectric layer is used. Such a memory device using a dielectric storage element is described in "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" by Eitan et al., November 2000, IEEE Electronic Device Letters 21, pp. 543-545. . The ONO dielectric layer extends across the channel between the source and drain diffusions. Charges for one data bit are disposed in the dielectric layer adjacent to the drain and charges for the other data bits are disposed in the dielectric layer adjacent to the source. For example, US Pat. Nos. 5,768,192 and 6,011,725 disclose nonvolatile memory cells having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by individually reading the binary states of spatially separated charge storage regions within the dielectric.

In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, one "page" of memory elements are read or programmed together. In existing memory architectures, a row typically includes several interleaved pages or may constitute one page. All memory elements on a page will be read or programmed together.

In a typical memory architecture, rows of memory elements share a common word line. However, due to the more shrinkage of the memory elements and the higher integration of the memory chips, the wires are thinner and more resistant. This causes a significant increase in wire RC delay, such as that found on word lines. For example, this is known to cause a 0.4V difference in programmed threshold (VT) values between memory elements close to the row decoder and memory elements away from the row decoder. During the programming of the page, additional programming pulses may be required to handle the differences, thus degrading performance.

Thus, there is a general need for high capacity and high efficiency nonvolatile memory. In particular, there is a need to have a high capacity non-volatile memory that can perform memory operations at high performance in large blocks.

According to a general aspect of the present invention, variations in programming effectiveness due to variations in time constants along word lines across the memory plane are compensated by adjusting the bit line voltages across the plane to modify the programming speeds. In this way, variations in programming effectiveness are substantially reduced during programming of a group of memory cells coupled to a word line.

This will reduce the number of programming pulses required to program a group of memory cells, thereby improving performance.

In one embodiment, during programming, the bit lines in the first half of the memory plane closer to the word line voltage source are set to the first voltage and the bit lines in the second half of the memory plane farther from the word line voltage source. It is set to the second voltage. In particular, the first voltage is greater than the second voltage such that variations in programming effectiveness between the two halves are substantially minimized.

According to another embodiment of the present invention, different bit line voltages are driven by respective bit line voltage shifters. For example, bit lines in the first half of the memory plane are coupled to be driven to the first voltage by a first voltage shifter, and bit lines in the second half of the memory plane are coupled to the second voltage by the second voltage shifter. Coupled to drive.

In general, more than two bit line voltages may be implemented based on distance from a word line voltage source, such as a row decoder.

Additional features and advantages of the invention will be understood from the preferred embodiments described in conjunction with the accompanying drawings.

1 schematically illustrates the functional blocks of a nonvolatile memory chip in which the present invention may be implemented.

2 schematically illustrates a nonvolatile memory cell.

FIG. 3 shows the relationship between the control gate voltage V _CG and the source-drain current I _D for the four different charges Q1 to Q4, in which the floating gate may be selectively stored at any one time.

4 shows an example of an NOR array of memory cells.

5A schematically illustrates a string of memory cells consisting of a NAND string.

FIG. 5B shows an example of a NAND array 200 of memory cells constructed from NAND strings 50 as shown in FIG. 5A.

6 illustrates a series of programming voltage pulses in the form of a stepped waveform applied to a selected word line.

7A illustrates a word line coupled to a plurality of memory cells.

7B shows the product of the resistance and capacitance of a given segment of a word line for an access node.

7C shows the response of a programming pulse at various locations from an access node.

FIG. 7D illustrates a general scheme of the present invention for compensating for RC variations along a word line during programming. FIG.

8A shows a word line coupled to a plurality of memory cells.

FIG. 8B illustrates a general scheme of the present invention for compensating for RC variations along a word line during programming. FIG.

8C shows the bit line voltage coming from the row decoder as a function of the distance of each memory cell in accordance with a preferred embodiment.

8D illustrates bit line voltage coming from the row decoder as a function of the distance of each memory cell in accordance with another preferred embodiment.

9 illustrates one embodiment of applying bit line voltages in a memory plane according to the bit line voltage profile of FIG. 8C.

10 shows a preferred sense module for setting the bit line voltage in more detail.

FIG. 11 shows an embodiment of the VBL shifter shown in FIGS. 9 and 10.

12 is a flow diagram illustrating programming to compensate for a bit line according to a word line, in accordance with the general technique of the present invention.

Memory system

1-5 illustrate example memory systems in which various aspects of the present invention may be implemented.

6-12 show embodiments of the word line compensation techniques and device of the present invention.

1 schematically shows the functional blocks of a nonvolatile memory chip in which the present invention may be implemented. Memory chip 100 includes a two-dimensional array of memory cells 200, control circuit 210, and peripheral circuits such as decoders, read / write circuits, and multiplexers.

Memory array 200 is provided by word lines through row decoders 230 (divided by 230A and 230B) and by bit lines through column decoders 260 (divided by 260A and 260B). Addressable (see also FIGS. 4 and 5). Read / write circuits 270 (divided into 270A and 270B) allow one page of memory cells to be read or programmed in parallel. Data I / O bus 231 is coupled to read / write circuits 270.

In a preferred embodiment, one page consists of successive rows of memory cells sharing the same word line. In another embodiment where a row of memory cells is divided into multiple pages, block multiplexers 250 (divided into 250A and 250B) are provided to multiplex read / write circuits 270 into individual pages. For example, two pages, each formed by odd and even columns of a memory cell, are multiplexed into read / write circuits.

1 illustrates a preferred embodiment in which access to the memory array 200 by various peripheral circuits is implemented in a symmetrical manner on opposite sides of the array such that the densities of access lines and circuits on each face are reduced by half. Shows. Thus, the row decoder is divided into row decoders 230A and 230B, and the column decoder is divided into column decoders 260A and 260B. In an embodiment in which a row of memory cells is divided into multiple pages, page multiplexer 250 is divided into page multiplexers 250A and 250B. Similarly, read / write circuits 270 may include read / write circuits 270A for connecting bit lines from the bottom and read / write circuits for connecting bit lines from the top of array 200. Divided by (270B). In this way, the density of the read / write modules and thus the density of the sense modules 380 is reduced by essentially one half.

Control circuit 110 is an on-chip controller that cooperates with read / write circuits 270 to perform memory operations on memory array 200. Control circuit 110 typically includes a state machine 112 and other circuits such as an on-chip address decoder and a power control module (not explicitly shown). State machine 112 provides chip level control of memory operations. The control circuit communicates with the host via an external memory controller.

Memory array 200 is typically configured as a two dimensional array of memory cells arranged in rows and columns and addressable by word lines and bit lines. Arrays can be formed according to NOR-type or NAND-type architectures.

2 schematically illustrates a nonvolatile memory cell. The memory cell 10 may be implemented by a field effect transistor having a charge storage unit 20, such as a floating gate or dielectric layer. Memory cell 10 also includes a source 14, a drain 16, and a control gate 30.

There are many commercially available nonvolatile solid state memory devices in use today. These memory devices may use different types of memory cells, each type having one or more charge storage elements.

Typical nonvolatile memory cells include EEPROM and flash EEPROM. Examples of EEPROM cells and methods of making them are described in US Pat. No. 5,595,924. Examples of flash EEPROM cells, their uses in memory systems and methods of manufacturing them are described in US Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421 and 6,222,762. In particular, examples of memory devices having NAND cell structures are described in US Pat. Nos. 5,570,315, 5,903,495, 6,046,935. Also, examples of memory devices using dielectric storage devices are described by Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," in the November 2000 IEEE Electronic Device Letters 21, pages 543 to 545. Patent Nos. 5,768,192 and 6,011,725.

In practice, the memory state of a cell is generally read by sensing the conduction current across the cell's source and drain electrodes when a reference voltage is applied to the control gate. Thus, for each predetermined charge on the floating gate of the cell, the corresponding conduction current for a fixed reference control gate voltage can be detected. Similarly, the range of charges programmable onto the floating gate defines a corresponding threshold voltage window or corresponding conductive current window.

Alternatively, instead of detecting the conduction current among the divided current windows, it is possible to set a threshold voltage for a given memory state under test at the control gate and to detect when the conduction current is lower or higher than the threshold current. In one embodiment, detection of the conduction current with respect to the threshold current is achieved by examining the rate at which the conduction current is discharging through the capacity of the bit line.

3 shows the relationship between the control gate voltage V _CG and the source-drain current I _D for the four different charges Q1 to Q4 in which the floating gate can be selectively stored at any time. Four solid I _D versus V _CG curves, represent four possible charge levels that can be programmed on a floating gate of the memory cell, respectively corresponding to four possible memory states. For example, the threshold voltage window of a population of cells can range from 0.5V to 3.5V. Seven possible memory states, "Gr", "A", "B", "C", "D", "E", and "F", representing the erased one and six programmed states respectively Can be separated by dividing into 5 regions at intervals of 0.5V each. For example, when using as a reference current, I _REF of 2㎂ shown, the cell programmed with Q1 is in the region of the window system being that the curve is separated by V _CG = 0.5 V and 1.0V, and I _REF It can be considered to be in memory state "A" because it intersects. Similarly, Q4 is in memory state "E".

As can be seen from the above description, the more states the memory cell is to store, the finer the threshold window is divided. This will require higher precision in programming and read operations in order to be able to achieve the required resolution.

4 shows an example of an NOR array of memory cells. In the memory array 200, each row of memory cells is daisy chained by sources 14 and drains 16. This design is sometimes referred to as a virtual ground design. The cells 10 in the row have control gates 30 connected to the same word line as the word line 42. The cells in the column have sources and drains connected to selected bit lines, such as bit lines 34 and 36, respectively.

Figure 5a schematically illustrates a string of memory cells consisting of a NAND string. NAND string 50 is a series of memory transistors Ml, M2, ... Mn (e.g., daisy chained by sources and drains). N = 4, 8, 16 or more). The pairs of select transistors S1 and S2 control the chain connection of the memory transistors to the outside via the source terminal 54 and the drain terminal 56 of the NAND strings, respectively. In the memory array, when the source select transistor S1 is turned on, the source terminal is coupled to the source line (see Fig. 5B). Similarly, when drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to the bit line of the memory array. Each memory transistor 10 in the chain acts as a memory cell. It has an electronic storage element 20 for storing a predetermined amount of charge to represent the intended memory state. The control gate 30 of each memory transistor controls the read and write operations. As seen in FIG. 5B, the control gates 30 of the corresponding memory transistors of the row of the NAND string are all connected to the same word line. Similarly, each control gate 32 of select transistors S1, S2 provides control access to the NAND string through source terminal 54 and drain terminal 56, respectively. Similarly, the control gates 32 of the corresponding select transistors of the row of the NAND string are all connected to the same select line.

When the addressed memory transistor 10 in the NAND string is read or verified during programming, the control gate 30 is supplied with the appropriate voltage. At the same time, the rest of the unaddressed memory transistors in the NAND string 50 are fully turned on by the application of sufficient voltage on the control gates. In this manner, the conductive path is effectively generated from the source of the individual memory transistors to the source terminal 54 of the NAND string, as well as the drain of the individual memory transistors to the drain terminal 56 of the cell. Memory devices having such NAND string structures are described in US Pat. Nos. 5,570,315, 5,903,495, 6,046,935.

FIG. 5B shows an example of a NAND array 200 of memory cells constructed from NAND strings 50 as shown in FIG. 5A. Along each column of NAND strings, a bit line such as bit line 36 is coupled to the drain terminal 56 of each NAND string. Along each bank of NAND strings, a source line such as source line 34 is coupled to the source terminals 54 of each NAND string. In addition, the control gates along the row of the memory cell in the bank of NAND strings are connected to a word line, such as word line 42. Control gates along the rows of select transistors in the bank of NAND strings are connected to a select line, such as select line 44. The entire row of memory cells in the bank of NAND strings may be addressed by appropriate voltages on the word lines and select lines of the bank of NAND strings. When a memory transistor in a NAND string is being read, the remaining memory transistors of the string are hardly turned on through the associated word lines, so that the current flowing through the string is essentially dependent on the level of charge stored in the cell being read.

Compensation for variations due to word lines during memory operation

In a typical memory architecture, one row of memory elements share a common word line. For example, each row of memory cells has a control gate connected to a word line. However, due to the more shrinkage of memory elements and the higher integration of memory chips, the wires become thinner and more resistant. This causes the wire RC delay such as found on the word line to be significantly increased. For example, it has been found that this causes a 0.4V difference in programmed threshold (VT) values between memory elements close to the row decoder and memory elements far from the row decoder. During programming of the page, additional programming pulses may be required to address the differences, thereby degrading performance.

One possible solution is to improve the process of manufacturing a memory chip by using materials that are less resistant to word lines. However, process changes are difficult to implement and, if practicable, will eventually reach their limits.

According to one aspect of the present invention, variations in programming effectiveness due to variations in time constants along word lines across the memory plane are compensated by adjusting the bit line voltages across the plane to modify the programming speeds. In this way, variations in programming effectiveness are substantially reduced during programming of a group of memory cells coupled to a word line.

6 shows a series of programming voltage pulses in the form of a stepped waveform applied to a selected word line. When the cell is programmed to a predetermined state, successive programming voltage pulses are required and attempt to add increasing charges to the floating gate every hour. Between programming pulses, the cell is read back or verified to determine the source-drain current for the breakpoint level. Programming for the cell stops when it is verified to reach the desired state. The programming pulse train used may have an increasing period or amplitude to eliminate accumulated electrons programmed into the charge storage unit of the memory cell. Programming circuits generally apply a series of programming pulses to a selected word line. In this way, a page of memory cells whose control gates are connected to a word line can be programmed together. Each time one memory cell of the page is programmed to the target state, the program is inhibited, but the other cells continue to be programmed until all the cells of the page are program verified.

7A-7D schematically illustrate variations in various operating voltages along a word line, in accordance with a general embodiment of the present invention.

7A illustrates a memory line coupled to a plurality of memory cells. Depending on the type of memory architecture, each memory cell 10 may come from a NOR cell as shown in FIG. 4 or from a NAND string 50 as shown in FIG. 5A. In one embodiment, word line WL 42 is accessible from access node 46 at the end coupled to word line decoder 230. During a memory operation, an operational word line voltage is supplied from the word line decoder to the access node 46. Thus, access node 46 may be considered a word line voltage source. One row of memory cells in the memory array share word line WL 42. Each memory cell 10 has a control gate 30 coupled to the WL 42 at various locations from the access node 46.

7B shows the product of the resistance and capacitance of a given segment of a word line for an access node. The word line WL 42 is formed from a conductor having a limited resistance. The resistance of the segment of the word line is proportional to the length of the segment. On the other hand, the capacity of the segment is substantially independent of the length. Thus, the product of RC over the segment of the word line increases linearly as a function of the length for the access node.

7C shows the response of a programming pulse at various locations from an access node. When a separate programming pulse (see Figure 6) is fed to the access node for the word line, it essentially encounters the RC circuit. In general, at position r from an access node, the value of RC is given by RC (r). At that location, the voltage V _WL (r) is in response to an input programming pulse for a segment of the word line up to r. The response is the charging of a portion of the word line and the time constant is given by RC (r). The charging voltage at position r and time t is V _WL (r, t) = V _WL (r = 0) [1-EXP (-t / RC (r))]. The discharge voltage at position r and time t is V _WL (r, t) = V _WL (r = 0) EXP (-t / RC (r)). In other words, the product RC (r) is a time constant that determines the rate of charge or discharge of the word lie at position r. After one unit of time constant, the word line will be charged to 63.2%. After two units of time constant, the word line will be charged to 86.5% and so on. Therefore, the larger the RC, the slower the charge and discharge will be. For a rectangular programming pulse, the word line will charge with the rising edge of the pulse and discharge with the falling edge of the pulse.

The effect of RC variation along the word line is for cells farther away from the row decoder, and the RC delay is greater, thus reducing the effectiveness of the programming purse. This effect has been observed to be sufficient in integrated circuit chips using 56nm technology. For example, it has been known to cause a difference of 0.4V in the programmed VT values between cells close to the row decoder and cells away from the row decoder (for the same number of program pulses). This difference in the programmed VT values may require additional programming pulses to reach the same VT for the cell furthest from the row decoder.

7d illustrates the general scheme of the present invention for compensating for RC variations along a word line during programming. In essence, the bit line voltage during programming is adjusted according to the distance of each cell from access node 46 or row decoder 230. In general, during programming, the programming effectiveness depends on the electric field between the control gate and the substrate or the potential difference between the control gate and the bit line. The bit line voltage during conventional programming is generally kept to a minimum at V _BL = 0. If the bit line voltage is higher, the programming effectiveness will be reduced since the electric field for electron tunneling from the substrate to the floating gate will be reduced. Because cells closer to the row decoder program faster, higher bit line voltages are applied during programming to slow down compared to cells farther away from the row decoder. This will allow the same number of programming pulses to program all cells along the word line with nearly the same VT.

8A-8D schematically illustrate variations of various operating voltages along a word line, in accordance with preferred embodiments of the present invention. The word line WL is divided into four parts, part 1 is the closest to the access node 46 of the row decoder 230 and part 4 is the furthest. For convenience of comparison, FIG. 8A is identical to FIG. 7A and FIG. 8B is identical to FIG. 7D.

8C shows the bit line voltage as a function of the distance of each memory cell coming from the row decoder according to the preferred embodiment. In essence, to simplify wiring and circuitry, the bit line voltage across the word line is quantized to a limited number of values. 8C shows a plane traversed by a word line divided into two halves. The left half of the plane closest to the row decoder includes portions 1 and 2 of the word line, and the right half of the plane away from the row decoder includes portions 3 and 4 of the word line. The bit line voltage V _BL (r) is V ₁ for the left half of the plane and V _BL (r) is V ₀ for the right half of the plane. The optimal values of V ₁ and V ₀ will depend on the particular memory device and can be determined by a test. In most cases V ₀ = 0.

8D shows the bit line voltage as a function of the distance of each memory cell coming out of the row decoder according to another preferred embodiment. In this embodiment, the plane traversed by the word line is divided into four parts corresponding to parts 1 to 4. Bit line voltages V _BL (r) are V ₁₁ , V ₁₀ , V ₀₁ and V ₀₀ for portions 1, 2, 3 and 4, respectively.

FIG. 9 illustrates one embodiment of applying bit line voltages in a memory plane according to the bit line voltage profile of FIG. 8C. For example, the memory plane forms the entire memory array 200 spanned by word lines in the row direction and bit lines 32 in the column direction. The word line voltage is supplied to a selected word line, such as WL 42, through an access node 46 of row decoder 230. The bit lines are individually coupled to the sense modules of read / write circuit 270 (distributed between read / write circuits 270A and 270B in FIG. 1). Each sense module has a node A that can set the coupled bit line to ground potential or a predetermined bit line voltage. For the binary embodiment shown in FIG. 8C, the bit lines in the left half of the plane shown in FIG. 9 are all coupled to node A-1 701-1, and predetermined voltage V using VBL shifter 710. _Is set to ₁ On the other hand, the bit lines of the right half of the plane are all coupled to node A-0 701-0 and set to a predetermined voltage V ₀ (eg ground potential).

10 shows a preferred sense module for setting the bit line voltage in more detail. Sensor module 480 includes a sense amplifier 600 for sensing current at node SEN2 481. Sense node SEN2 may be selectively coupled to read bus 499 or bit line 36 and memory cell 10 via voltage clamp 610 and isolation transistor 482. However, the sense amplifier 600 and the voltage clamp 610 are disabled during programming. In essence, the bit line voltage is set at the node, node A 701. When the isolation transistor is turned on with signal BLS, the bit line is coupled to node 613 to enable pulldown circuit 486 (enabled by signal INV) and pulldown isolation transistor 550 (enabled by signal GRS). Is coupled to node A 701 through a number of circuit steps. During programming, if the bit line voltage is set via node A 701, transistors 482 and 550 and pulldown circuit 486 are both turned on, so that bit line 36 is coupled to node A 701. .

As described in relation to FIG. 9, node A 701 of the individual sense modules on the left half of the memory plane is coupled to a node, node A-1 701-1, and is powered by a VBL shifter 700. It is driven by V ₁ . Similarly, node A 701 of the individual sense modules on the right half of the memory plane is coupled to a node, node A-0 701-0, and set to ground potential.

Although the technique for the binary embodiment of FIG. 8C has been provided, it is clear that for a case where the plane is divided into multiple parts, each bit line of each of the parts will have Node As coupled to a predetermined voltage. The predetermined voltage is set to the ground potential for the part furthest from the row decoder. For other parts, the predetermined voltage is set by each VBL shifter.

FIG. 11 illustrates one embodiment of the VBL shifter shown in FIGS. 9 and 10. The VBL shifter 700 is inserted between node A and ground of the individual sense modules. In particular, a potential divider formed by two resistors R1 and R2 in series is inserted between node A and ground. In one embodiment, resistor R2 is digitally adjustable by the DAC control circuit. The differential amplifier 720 is used to drive node A. Differential amplifier 720 has two differential inputs 722 and 724. Reference voltage VREF is connected to input 722 and the voltage tapped from between R1 and R2 is connected to input 724. In this way, the voltage at node A can be set to the desired value by adjusting the value of R2.

12 is a flow diagram illustrating programming to compensate for a bit line along a word line, in accordance with the general technique of the present invention.

Step 800: Provide a nonvolatile memory comprising a group of memory cells coupled to a word line and each memory cell of the group accessible by a bit line.

Step 810: Provide an access node for a word line to apply a programming voltage, wherein each memory cell of the group is at a corresponding distance of the word line to the access node. For example, the access node comes from the row decoder 230.

Step 820: Set the bit line voltage of each cell of the group as a function of its corresponding distance. For example, the bit line voltage profiles of FIG. 8C or 8D may be applied.

Step 830: Program a group of memory cells in parallel by applying a programming voltage to the access node.

Fast pass record implementation

In another preferred embodiment, a "fast pass write" ("QPW") programming technique is also implemented. Whenever the cell's programming approaches are close to the verify limit point, programming will switch to a slower (ie, finer) mode by proper biasing of the bit line voltage or by modifying the programming pulses. In this way, larger programming steps can be used initially for rapid convergence without risking overshooting the target state. The "QPW" programming algorithm is disclosed in US patent application Ser. No. 11 / 323,596, filed Dec. 29, 2005 and entitled "Methods for Improved Program-Verify Operations in Non-Volatile Memories." The entire disclosure is incorporated herein by reference.

QPW programming techniques can be combined with the present compensation techniques. Both techniques adjust the bit line voltage to achieve their goals. QPW technology adjusts the bit line voltage at a specific time, but compensation for word line variations adjusts the bit line voltage as a function of cell displacement from the row decoder. Thus, the two adjustments can be applied linearly without damage to each other. For the bit line voltages with the binary profile shown in FIG. 8C, for example, the left half of the plane can set the bit lines to 0.35V, while the right half remains at 0V. If QPW is implemented, the initial bit line voltages are the same as in FIG. 8C. If a given cell is programmed close to the threshold, the bit line of the cell will have an increase of, for example, 0.7V to slow down programming near the threshold. Thus, if the cell is in the left half of the plane, the bit line voltage will be 1.05V and if the cell is in the right half of the plane, the bit line voltage will be 0.7V.

Another implementation of the invention also implements QPW on the left half of the plane, but does not use QPW on the right half of the plane.

Examples have been provided for bit line voltages having a binary (FIG. 8C) or quaternary profile (FIG. 8D) across a word line during programming, although other profiles are possible. Ideally, it reduces the bit line voltages in an analog manner (Fig. 8B) as it moves away from the access point or row decoder to compensate for the reduction in programming effectiveness.

All patents, patent applications, articles, books, specifications, other publications, documents, and tools referenced herein are fully incorporated herein by reference for all purposes. For the purposes of any inconsistency or conflict between regulations or terminology between the integrated publications, documents, or text and tools herein, the use of the terminology or terminology herein will be predominant.

While various aspects of the invention have been described with respect to specific embodiments, it is understood that the invention is entitled to protection within the full scope of the appended claims.

As noted above, the present invention is used to provide electrically erasable programmable read only memory (EEPROM) and nonvolatile semiconductor memory such as flash EEPROM.

Claims (33)

A method of programming a group of memory cells in parallel in a non-volatile memory comprising a group of memory cells coupled to a word line, each memory cell of the group being accessible by a bit line. Providing an access node for the word line to apply a programming voltage, wherein each memory cell of the group is at a corresponding distance of the word line with respect to the access node; Setting the bit line voltage of each memory cell of the group as a function of the corresponding distance; Programming the group of memory cells in parallel by applying the programming voltage to the access node. Including, programming method. 2. The method of claim 1, wherein the bit line voltage of each memory cell of the group is reduced as a monotonic function of the corresponding distance of each memory cell. The method of claim 1, wherein the programming voltage comprises a series of voltage pulses. 4. The method of claim 3, wherein the voltage pulses increase in amplitude with every pulse. 4. The method of claim 3, wherein each memory cell of the group receives the programming voltage from the access node via a corresponding RC network defined by the corresponding distance of the word line to the access node. 6. The method of claim 5, wherein the programming voltage received by each memory cell has programming efficacy modified by finite charge and discharge times due to the corresponding RC network, Setting the bit line voltage for each memory cell of the group as a function of corresponding distance compensates for the modified programming efficacy. 2. The apparatus of claim 1, wherein the word line is divided into two halves, the first half closer to the access node, the second half further away from the access node, Wherein the function generates a first bit line voltage for a memory cell coupled to the first half and a second bit line voltage for a memory cell coupled to the second half of the word line. 8. The method of claim 7, wherein the second bit line voltage is at ground potential. The method of claim 1, wherein the word line is divided into a plurality of parts, Wherein the function generates a separate bit line voltage for a memory cell coupled to each portion of the word line. The method of claim 1, wherein the nonvolatile memory is a flash EEPROM. The method of claim 1, wherein the nonvolatile memory has a NAND structure. The method of claim 1, wherein the nonvolatile memory is on a removable memory card. 2. The method of claim 1, wherein the nonvolatile memory has a memory cell having a floating gate structure. 2. The method of claim 1, wherein the nonvolatile memory comprises a memory cell having a dielectric layer structure. The programming method according to any one of claims 1 to 14, wherein the nonvolatile memory has memory cells that individually store one bit of data. 15. The method of any one of the preceding claims, wherein the nonvolatile memory has memory cells that individually store more than one bit of data. Non-volatile memory, An array of memory cells in a memory plane, A group of memory cells coupled to word lines across the memory plane, each memory cell of the group being accessible by a bit line to a column of the memory plane; An access node for the word line for applying a programming voltage, each memory cell of the group being at a corresponding distance of the word line with respect to the access node; The memory plane divided into a plurality of circumferential portions, each portion comprising a set of bit lines; An independent voltage source for each set of bit lines to supply a bit line voltage as a function of said corresponding distance from said access node. Including, non-volatile memory. 18. The nonvolatile memory as in claim 17, wherein the bit line voltage of each memory cell of the group is reduced as a monotonic function of the corresponding distance of each memory cell. 18. The nonvolatile memory as in claim 17, wherein the programming voltage comprises a series of voltage pulses. 20. The nonvolatile memory as in claim 19, wherein the voltage pulses increase in amplitude with every pulse. 20. The non- volatile memory as in claim 19, wherein each memory cell of the group receives the programming voltage from the access node via a corresponding RC network defined by the corresponding distance of the word line to the access node. 22. The method of claim 21 wherein the programming voltage received by each memory cell has programming efficacy modified by finite charge and discharge times due to the corresponding RC network, And the independent voltage source for each set of bit lines supplying a bit line voltage as a function of the corresponding distance from the access node compensates for the modified programming efficacy. 18. The apparatus of claim 17, wherein the word line is divided into two halves, the first half closer to the access node, the second half further away from the access node, The function generates a first bit line voltage for a memory cell coupled to the first half and a second bit line voltage for a memory cell coupled to the second half of the word line. 24. The nonvolatile memory as in claim 23, wherein the second bit line voltage is at ground potential. 18. The apparatus of claim 17, wherein the word line is divided into a plurality of portions, Wherein the function generates a separate bit line voltage for a memory cell coupled to each portion of the word line. 18. The nonvolatile memory as in claim 17, wherein the nonvolatile memory is a flash EEPROM. 18. The nonvolatile memory as in claim 17, wherein the nonvolatile memory has a NAND structure. 18. The nonvolatile memory as in claim 17, wherein the nonvolatile memory is on a removable memory card. 18. The nonvolatile memory as in claim 17, wherein the nonvolatile memory has a memory cell having a floating gate structure. 18. The nonvolatile memory as in claim 17, wherein the nonvolatile memory comprises a memory cell having a dielectric layer structure. Non-volatile memory, An array of memory cells in a memory plane, A group of memory cells coupled to word lines across the memory plane, each memory cell of the group being accessible by a bit line to a column of the memory plane; An access node for the word line for applying a programming voltage, each memory cell of the group being at a corresponding distance of the word line with respect to the access node; The memory plane divided into a plurality of circumferential portions, each portion comprising a set of bit lines; An independent voltage source for each set of bit lines to supply a bit line voltage as a function of the corresponding distance from the access node; Means for programming the group of memory cells in parallel by applying the programming voltage to the access node. Including, non-volatile memory. 32. The nonvolatile memory according to any one of claims 17 to 31, wherein the nonvolatile memory has memory cells that individually store one bit of data. 32. The nonvolatile memory as in any one of claims 17-31, wherein the nonvolatile memory has memory cells that individually store more than one bit of data.

Images