KR20100014547A - Memory cell comprising a carbon nanotube fabric element and a steering element and methods of forming the same - Google Patents

Abstract

A rewriteable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. A method to form a rewriteable nonvolatile memory cell and numerous other aspects are also disclosed.

Description

MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT AND METHODS OF FORMING THE SAME}

The present application, in March 2007, entitled "Method to Form a Memory Cell Comprsing a Carbon Nanotube Fabric Element and a Steering Element" US Patent Application No. 11 / 692,144 (Representative Document No. SAND-01193US0) to Herner et al., Filed date 27, and entitled "Carbon Cells with Carbon Nanotube Fabric Elements and Steering Elements." Priority to US Patent Application No. 11 / 692,148 (Representative Document No. SAND-01193US1) to Herner et al., Filed March 27, 2007, entitled "Memory Cell Comprsing a Carbon Nanotube Fabric Element and a Steering Element." Both of which are hereby incorporated by reference in their entirety.

Related Applications

The present application is filed on March 27, 2007, entitled "Method to Form Upward-pointing PIN Diodes Having Large and Uniform Current," entitled "Method to Form Upward-pointing PIN Diodes Having Large and Uniform Current." US patent application Ser. No. 11 / 692,151 (Attorney Docket No. SAND-01179US0), entitled "Large Array of Upward-Operating PIN Diodes with Large and Uniform Current" Pointing PIN Diodes Having Large and Uniform Current, "US Pat. Appl. No. 11 / 692,153 filed on March 27, 2007, Representative Document No. SAND-01179US1, both of which are herein incorporated by reference. The full text is incorporated by reference.

Carbon nanotube materials are believed to operate by bending individual carbon nanotubes or carbon nanotube ribbons in an electric field. This bending mechanism requires space for the carbon nanotubes to bend. In nanotechnology, the formation and manufacture of such spaces is extremely difficult.

It is desirable to form memory cells using easily fabricated carbon nanotubes. It is more desirable to form such memory cells in a high density, very large cross-point array.

The invention is defined by the following claims, and nothing in this description is regarded as a limitation on these claims. In general, the present invention relates to a memory array and a method of forming a memory array, wherein the memory cells comprise a carbon nanotube fabric and a control element, such as a diode or a transistor, that are electrically arranged in series.

A first aspect of the invention provides a memory cell, the memory cell comprising a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric comprise a first conductor. And are electrically arranged in series between the second conductor and the entire memory cell is formed over the substrate.

A second aspect of the invention provides a method of programming a carbon nanotube memory cell, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric and a second conductor, the steering element and the carbon nanotubes. The fabric is electrically arranged in series between the first conductor and the second conductor, the entire carbon nanotube memory cell is formed over the substrate, the carbon nanotube fabric has a first resistance, and the method comprises a first conductor and a second conductor. Applying a first electrical set pulse between conductors, and after application of the first electrical set pulse, the carbon nanotube fabric has a second resistance, and the second resistance is lower than the first resistance.

A preferred embodiment of the present invention forms a monolithic three dimensional memory array, which includes a first memory level monolithically formed over a substrate and (b) a second memory level monolithically formed over the first memory level; I) a plurality of substantially parallel, substantially coplanar first bottom conductors, ii) a plurality of steering elements, iii) a plurality of first level carbon nanotube fabric elements, iv) a plurality of substantially Parallel to and substantially coplanar, and v) a plurality of first level memory cells, each first level memory cell being disposed between one of the first bottom conductors and one of the first top conductors. One control element and one first level carbon nanotube fabric element arranged in electrical series.

Each aspect and embodiment of the invention described herein may be used alone or in combination with one another.

DESCRIPTION OF THE EMBODIMENTS Preferred aspects and embodiments will now be described with reference to the accompanying drawings.

1 is a perspective view of a memory cell formed in accordance with a preferred embodiment of the present invention.

2 is a partial perspective view of a first memory level including memory cells such as those shown in FIG.

3A and 3C are cross-sectional views illustrating memory arrays formed in accordance with embodiments of the present invention. 3A and 3C show the same structure at observation points perpendicular to each other, and FIG. 3B is a plan view of the structure.

4 is a cross-sectional view of another embodiment of the present invention.

5A-5D are cross-sectional views illustrating steps of forming two monolithic memory levels of a monolithic three dimensional memory array formed in accordance with a preferred embodiment of the present invention.

Carbon nanotubes are rolls of hollow cylinders of carbon, typically sheets of single carbon atom thickness. Carbon nanotubes typically have a diameter of about 1 to 2 nm and a length of hundreds or thousands of times larger than the diameter.

Nonvolatile memory retains information even when the device is powered off. Non-volatile memory cells using carbon nanotubes are described, for example, in Segal, which is entitled "Electromechanical memory having cell selection circuitry constructed with nanotube technology." Jaiprakash, US Pat. No. 6,643,165 to Segal et al. And entitled "Devices having vertically-disposed nanofabric articles and method of making the same." US Pat. No. 7,112,464, et al.

In both Segall et al. And Jaiprakash et al., The carbon nanotube elements (carbon nanotube ribbons consisting of single carbon nanotubes or multiple tubes) are spatially separated from the electrodes, and the carbon nanotube elements are oriented horizontally. It is suspended above the electrode or is vertically oriented and adjacent to the vertically oriented electrode. Memory cells operate by exposing the carbon nanotube elements to electrical charges such that the carbon nanotube elements are mechanically bent to make electrical contact with the electrodes. These two electrical states of the memory cell with or without the carbon nanotube element in contact with adjacent electrodes can be detected and remain when power is removed from the device and correspond to the two distinguishable data states of the memory cell.

Since the mechanism depends on the movement of the carbon nanotube element, the structure must be made to allow this movement by having a gap between the carbon nanotube element and the adjacent electrode. The production of such gaps in very small dimensions will be difficult and will become increasingly difficult because the dimensions are constantly smaller.

In the present invention, nonvolatile memory cells are formed using carbon nanotube fabrics. The term carbon nanotube fabric is used herein to describe a plurality of consecutive carbon nanotubes in which there is no desired orientation of the individual tubes as opposed to the carbon nanotube ribbons where the nanotubes must be substantially parallel. In a preferred embodiment, such carbon nanotube fabrics comprise several or multiple layers of carbon nanotubes in an arbitrary orientation. Operation of the cell does not require the formation of open spaces in which individual nanotubes can be bent, and therefore, is more robust and simpler to manufacture.

Carbon nanotube fabrics are expected to exhibit resistive switching behavior. That is, the fabric changes its resistance upon receiving sufficient voltage or current. The switch from the higher resistance to the lower resistance is referred to as a set transition and is achieved by an electrical set pulse, and the reset transition from the lower resistance to a higher resistance is achieved by an electrical reset pulse. The terms set voltage, set current, reset voltage and reset current are also used.

Thus, in summary, in one embodiment, the cell includes a carbon nanotube fabric and steering element electrically arranged in series between the first conductor and the second conductor. The carbon nanotube fabric may be in a first state with a first resistance. After application of the first electrical set pulse between the first conductor and the second conductor, the carbon nanotube fabric has a second resistance, which is less than the first resistance. Next, after application of the first electrical reset pulse across the steering element and the carbon nanotube fabric, the carbon nanotube fabric has a third resistance, the third resistance being greater than the second resistance. The data state of the memory cell is stored in any of these resistive states. A read voltage is applied to sense the data state after the application of the first set pulse or the application of the first reset pulse.

1 illustrates an embodiment of the invention. The carbon nanotube fabric 118 and the diode 302 are disposed in series between the bottom conductor 200 and the top conductor 400. Selective conductive barrier layers 110 and 111 intervene the carbon nanotube fabric 118. In one embodiment, when this memory cell is formed, the carbon nanotube fabric 118 is in a first resistance state, such as a high resistance or reset state. In this reset state, when a read voltage is applied between the top conductor 400 and the bottom conductor 200, a fine current or no current flows between the conductors. After application of the set pulses, the resistance of the carbon nanotube fabric 118 is subjected to a set transition to the set state in a low resistance state. In this set of carbon nanotube fabrics 118, when the same read voltage is applied between the top conductor 400 and the bottom conductor 200, significantly more current flows between them. After application of the reset pulse, the resistance of the carbon nanotube fabric 118 receives a reset transition and returns to a high resistance reset state. When a read voltage is applied between the top conductor 400 and the bottom conductor 200, a significantly smaller current flows between them. Different currents under the applied read voltage between the set state and the reset state can be reliably sensed. These different states correspond to separate data states of the memory cell. For example, one resistance state may correspond to data "0" and the other corresponds to data "1". In alternative embodiments, the initial state of the carbon nanotube fabric 118 may be a low resistance state. For brevity, two data states will be described. However, those skilled in the art will understand that in some embodiments, three, four or more reliably distinguishable resistance states can be achieved.

2 shows a plurality of bottom conductors 200 and top conductors 400 having intervening pillars 300, the pillars 300 comprising diodes and carbon nanotube fabric elements. In alternative embodiments, the diode may be replaced with any other non-omic device. In this way a first level of memory cell can be formed, and only a small portion of this memory level is shown here. In a preferred embodiment, additional memory levels can be stacked over this first memory level to form a high density monolithic three dimensional memory array. The memory array is formed of layers deposited or grown over a substrate, such as a single crystal silicon substrate. The support circuit is preferably formed on a substrate below the memory array.

An alternative embodiment of the present invention is a rewritable memory cell comprising a series of transistors and resistance-switching materials, incorporated herein by reference, assigned to the assignee of the present invention. Transetti and Resistance-Switching Material in Serise, "US Pat. Appl. No. 11 / 143,269, issued June 2, 2005 to Petti et al. Petty et al. Disclose a memory cell having a layer of resistance-switching binary metal oxide or nitride formed in series with a MOS transistor. In an embodiment such as Patty, the MOS transistor is a thin film transistor, and its channel layer is formed in the deposited polycrystalline semiconductor material rather than inside the single crystal wafer substrate.

Turning to FIG. 3A, in a preferred embodiment, such as Petty, a plurality of substantially parallel data lines 10 are formed. A semiconductor pillar 12 is formed over one of each data line 10. Each pillar 12 includes high doped regions 14 and 18 that serve as drain and source regions, and light doped regions 16 that serve as channel regions. The gate electrode 20 surrounds each filler 12.

3B shows the cell of FIG. 3A seen from above. In a repeating pattern, the pitch is the distance between one feature and the next occurrence of the same feature. For example, the pitch of the pillars 12 is the distance between the center of one pillar and the center of the adjacent pillar. In one direction, the pillar 12 has a first pitch P ₁ , and in the other direction, the pillar 12 has a larger pitch P ₂ , for example P ₂ is 1.5 times greater than P _1. Can be large. (The feature size is the width of the gap or minimum feature formed by photolithography in the device. In other words, the pitch P ₁ can be twice the size of the feature and the pitch P ₂ can be three times the feature size.) In the direction with the smaller pitch P ₁ shown in FIG. 3A, the gate electrodes 20 of adjacent memory cells join to form a single select line 22. In the direction with the larger pitch P ₂ , the gate electrodes 20 of adjacent cells do not merge, and adjacent select lines 22 are isolated. FIG. 3A shows the structure in cross section along line X-X 'in FIG. 3B, and FIG. 3C shows the structure in cross section along line Y-Y' in FIG. 3B.

3A and 3C, a reference line 24, preferably perpendicular to the data line 10, has a vertical direction between each column 12 between one of the data lines 10 and one of the reference lines 24. It is formed on the pillar 12 to be arranged. The resistive-switching memory element 26 is formed in each memory cell, for example, between the source region 18 and the baseline 24. Alternatively, resistance-switching memory element 26 may be formed between drain region 14 and data line 10. In a preferred embodiment of the present invention, resistance-switching element 26 comprises a layer of carbon nanotube fabric. In the embodiment of Figures 3A-3C, it should be noted that the carbon nanotube fabric is present on top of the column, not below the column.

4 illustrates another embodiment of Petty et al. This embodiment similarly includes a memory cell in a TFT array having each transistor and a reversible resistance-switching memory element in series but having a different structure. Substantially parallel rail 30 (shown in cross section, extending out of the ground) comprises a plurality of line sets 31, each line set 31 having two data lines 32 and one reference line 34. ), And the reference line 34 is immediately adjacent between the two data lines 32. The substantially parallel select line 36 extends above the rail 30 and preferably perpendicular to the rail. The select line 36 extends over the same space as the gate dielectric layer 38 and the channel layer 40. The memory level includes pillars 42, each pillar 42 being disposed vertically between one of the channel layers 40 and one of the data lines 32 or one of the reference lines 34. Transistors are formed including adjacent columns along the same select line. Transistor 44 includes channel region 51 between source region 50 and drain region 52. One pillar 42a includes a resistance-switching element 46 and the other pillar 42b does not. In this embodiment, adjacent transistors share a baseline. For example, transistor 48 shares baseline 34 with transistor 44. There is no transistor between adjacent data lines 32. In a preferred embodiment of the invention, resistance-switching element 46 comprises a carbon nanotube fabric layer.

1, 3A-3C and 4, the carbon nanotube fabric is paired with a diode or transistor. Diodes and transistors share non-omic conduction characteristics. Ohmic conductors such as wires conduct current symmetrically, and the current increases linearly with the voltage according to Ohm's law. Devices that do not follow this law exhibit non-ohm conduction and will be described as steering elements. By pairing the steering element with the carbon nanotube fabric, the memory cells can be formed in a large crossover array. The steering element provides electrical isolation between adjacent cells so that the selected cell can be set, reset or sensed without unintentionally setting or resetting the cell sharing the word line or bit line with the selected cell.

Each of these embodiments includes a first conductor, a steering element, a carbon nanotube fabric and a second conductor, wherein the steering element and the carbon nanotube fabric are electrically arranged in series between the first conductor and the second conductor, and the entire memory. The cell is formed over the substrate.

These embodiments are provided by way of example, and other embodiments may be devised that fall within the scope of the invention.

Dated June 8, 2005, entitled "Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material", incorporated herein by reference. As described in US patent application Ser. No. 11 / 148,530 to Herner et al., When polycrystalline silicon or polysilicon is deposited when it is crystallized in contact with only materials with high lattice mismatch such as silicon dioxide and titanium nitride Is formed with a high number of crystal defects, resulting in high high resistance. The application of programming pulses through these high-defect polysilicons obviously changes the polysilicon to become low resistive.

Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low, entitled "Invention", both of which are hereby incorporated by reference. -Impedance States, "US Patent Application No. 10 / 955,549 to Herner et al., Filed Sep. 29, 2004, and a memory cell comprising a semiconductor junction diode crystallized adjacent to silicide. As further described in Herner, US Pat. No. 7,176,064, entitled "Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide", the deposited amorphous silicon is a suitable When crystallized in contact with, the resulting crystallized silicon has a much higher quality with fewer defects It said, has a much lower resistance. The lattice spacing of titanium silicide or cobalt silicide is very close to the lattice spacing of silicon, and when the amorphous silicon is crystallized in contact with the appropriate silicide layer in the desired orientation, the silicide provides a template for the crystal formation of silicon. It is believed to minimize defect formation. Unlike high-defect silicon, crystallized only adjacent to materials with high lattice mismatch, the application of large electrical pulses does not adequately change the resistance of this low-defect, low-resistance silicon crystallized in contact with the silicon layer.

Referring to FIG. 1, in a preferred embodiment, diode 302 is preferably a junction diode. The term junction diode is used herein to refer to a semiconductor device having two terminal electrodes, consisting of a semiconductor material that is p-type at one electrode and n-type at the other, having the property of conducting current more easily in one direction than the other. Used to refer. Examples include a p-n diode having a p-type semiconductor material in contact with an n-type semiconductor material and a p-i-n diode in which an intrinsic (undoped) semiconductor material is interposed between the p-type semiconductor material and the n-type semiconductor material. In the embodiment of FIG. 1, the diode 302 is preferably formed of silicon, and the bottom layer of the top conductor 400 is a silicide-forming metal such as titanium or cobalt. Annealing causes the silicon of diode 302 to react with the silicide-forming metal to form a layer of silicide, such as titanium silicide or cobalt silicide, which provides a crystallization template for the silicon of diode 302 It can be formed of high-quality, low-resistance silicon. Thus, the set or reset pulse applied between conductors 400 and 200 functions only to switch the resistance state of carbon nanotube fiber 118 and does not change the resistance of silicon in diode 302. This makes the set or reset transition more controllable and predictable, and can function to reduce the amount of pulse needed. In another embodiment, the silicon of diode 302 is deposited in an amorphous state, and can be crystallized adjacent only to materials with high lattice mismatches, and thus made of high-defect, high-resistance polysilicon.

The present description describes a diode formed of crystallized silicon in contact with a suitable silicide. Silicon and germanium can be mixed completely, and the lattice spacing of germanium is very close to the lattice spacing of silicon. Alloys of amorphous silicon-germanium crystallized in contact with a suitable silicide-germanide (such as titanium silicide-germanide or cobalt silicide-germanide) are similar to form low-defect, low-resistance polysilicon-polygernium. It is expected to crystallize.

Preferred diodes of the present invention are vertically oriented p-i-n diodes having a bottom high doping region, a medium intrinsic or light doping region of a first conductivity type, and a top high doping silicon of a second conductivity type opposite to the first conductivity type.

A detailed description is provided describing the fabrication of two memory levels formed over a substrate, wherein the memory levels include memory cells having diodes and carbon nanotube fabric elements arranged in series between the bottom and top conductors. Nov. 15, 2006, entitled "PIN Diode Crystallized Adjacent to a Silicide in Series with a Dielectric Antifuse," which is incorporated herein by reference. The detailed description of Herner, US patent application Ser. No. 11 / 560,283, filed with is useful for the fabrication of this memory level. In order not to obscure the present invention, it will be understood that not all details from this and other integrated documents are included, but no teachings of these applications and patents are excluded. For the sake of completeness, numerous details will be provided, including materials, steps, and conditions, but those skilled in the art will appreciate that many of these details will be altered, extended or omitted to the extent that the results are within the scope of the invention. I can understand that you can.

Yes

Turning to FIG. 5A, fabrication of the memory begins with the substrate 100. The substrate 100 may comprise monocrystalline silicon, monocrystalline silicon, IV-IV compounds such as silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VII compounds, epitaxial layers on such substrates or any other semiconductor material. And may be any semiconductor substrate known in the art. The substrate may include an integrated circuit fabricated therein.

The insulating layer 102 is formed on the substrate 100. Insulating layer 102 may be silicon oxide, silicon nitride, Si—C—O—H film, or other suitable insulating material.

The first conductor 200 is formed over the substrate 100 and the insulator 102. An adhesive layer 104 is included between the insulating layer 102 and the conductive layer 106 to help adhere the conductive layer 106 to the insulating layer 102. If the conductive layer 106 disposed above is tungsten, titanium nitride is suitable as the adhesive layer 104. Conductive layer 106 may comprise any conductive material known in the art, such as tungsten, tantalum, titanium, or other materials including alloys thereof.

Once all of the layers forming the conductor rails have been deposited, the layers can be formed using any suitable masking and etching process to form a substantially parallel, substantially coplanar conductor 200 having a cross section shown in FIG. 5A. Patterned and etched. Conductor 200 extends out of the ground. In one embodiment, the photoresist is deposited, patterned by photolithography, the layers are etched, and then the photoresist is removed using standard processing techniques.

Next, a dielectric material 108 is deposited between and over the conductor rails 200. Dielectric material 108 may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide deposited by the high density plasma method is used as the dielectric material 108.

Finally, excess dielectric material 108 on top of conductor rail 200 is removed to expose the top of conductor rail 200 separated by dielectric material 108, leaving a substantially planar surface. The resulting structure is shown in FIG. 5A. Removal of this dielectric overfill to form a planar surface can be performed by any process known in the art, such as chemical mechanical planarization (CMP) or etchback. In an alternative embodiment, the conductor 200 may instead be formed in the damascene method.

Turning to FIG. 5B, an optional conductive layer 110 is then deposited. Layer 110 is a conductive material, for example titanium nitride, tantalum nitride or tungsten. This layer may be any suitable thickness, for example about 50 to about 200 angstroms, preferably about 100 angstroms. In some embodiments, the barrier layer 110 may be omitted.

Next, a thin layer 118 of carbon nanotube fabric is formed using any conventional method. [For brevity, substrate 100 is omitted from FIG. 5B and subsequent figures, the presence of which may be inferred] In some embodiments, this layer is formed by spin casting or spraying a solution comprising carbon nanotubes. And such solutions are commercially available. Carbon nanotube fabric layer 118 is preferably about 2 nm to about 500 nm thick, most preferably about 4 to about 40 nm thick.

Conductive layer 111 is deposited on layer 118. It may be any suitable conductive material, for example titanium nitride, having any suitable thickness, for example about 50 to about 200 angstroms, preferably about 100 angstroms. In some embodiments, conductive layer 111 may be omitted.

Conductive layers 110 and 111, which are present directly above and just below carbon nanotube fabric 118, respectively, and which are in permanent contact with the carbon nanotube fabric, serve as electrodes and assist in resistive switching of carbon nanotube fabric 118. Can be. The next layer to be deposited is a semiconductor material, such as silicon, and is typically deposited by a low pressure chemical vapor deposition (LPCVD) process. Silicon deposited by LPCVD has good step coverage and tends to penetrate between individual carbon nanotubes and change the fabric's composition and behavior when deposited directly on carbon nanotube fabric 118. . The conductive layer 111 formed of a material having poor step coverage helps to prevent such penetration.

Next, a semiconductor material to be patterned into pillars is deposited. The semiconductor material may be silicon, germanium, silicon-germanium alloy or other suitable semiconductor or semiconductor alloy. For brevity, the present description refers to a semiconductor material as silicon, but a skilled practitioner will understand that any of these other suitable materials may be selected instead.

Bottom high doped region 112 may be formed by any deposition and doping method known in the art. Although silicon may be deposited and then doped, it is preferred to be doped in situ by flowing a donor gas that provides p-type dopant atoms, such as boron, during deposition of silicon. In a preferred embodiment, the donor gas is BCl ₃ and the p-type region 112 is preferably doped to a concentration of about 1 × 10 ²¹ atoms / cm ³ . The high doped region 112 is preferably about 100 to about 800 angstroms thick, most preferably about 200 angstroms thick.

Intrinsic or lightly doped region 114 may then be formed by any method known in the art. Region 114 is preferably silicon and has a thickness of about 1200 to about 4000 angstroms, preferably about 3000 angstroms. Silicon in high doped region 112 and intrinsic region 114 is preferably amorphous when deposited.

Along with the conductive layer 111, carbon nanotube fabric 118 and conductive layer 110 disposed below, immediately deposited semiconductor regions 114, 112 are patterned and etched to form pillars 300. The pillars 300 should have approximately the same pitch and approximately the same width as the conductor 200 below so that each pillar 300 should be formed on top of the conductor 200. Some misalignment can be tolerated.

Pillar 300 may be formed using any suitable masking and etching process. For example, the photoresist may be deposited, patterned using standard photolithography techniques, etched, and then the photoresist removed. Alternatively, a hard mask of some other material, such as, for example, silicon dioxide, may be formed on top of the stack of semiconductor layers along with a bottom antireflective coating (BARC) on the top, and then patterned and etched. .

Similarly, dielectric antireflective coating (DARC) can be used as the hard mask.

Both are owned by the assignee of the present invention and are incorporated herein by reference, entitled " Photomask Features with Interior Nonprinting Window Using Alternating Phase Shifting. &Quot; Chen, US Application No. 10 / 728,436, filed Dec. 5, 2003, entitled "Photomask Features with Chromeless Nonprinting Phase Shifting." The photolithography technique described in US application Ser. No. 10 / 815,312, filed April 1, 2004, is preferred to perform any photolithography step used to form a memory array according to the present invention. Can be used.

The diameter of the pillar 300 may be, for example, about 22 nm to about 130 nm, preferably about 32 nm to about 80 nm, for example about 45 nm, as needed. The gap between the pillars 300 is preferably approximately equal to the diameter of the pillars. It should be noted that when very small features are patterned as columns, the photolithography process tends to round corners, so that the cross section of the columns tends to be circular regardless of the actual shape of the corresponding features in the photomask. .

Dielectric material 108 is deposited between and over semiconductor pillars 300 to fill the gaps between the pillars. Dielectric material 108 may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the insulating material.

Next, the dielectric material on top of pillar 300 is removed to expose the top of pillar 300 separated by dielectric material 108 and leave a substantially flat surface. Removal of this dielectric overcharge may be performed by any process known in the art, such as CMP or etch back. After CMP or etch back, ion implantation is performed to form the highly doped n-type top region 116. The n-type dopant is preferably a shallow implant of arsenic having, for example, an injection energy of 10 keV and a dose of about 3 × 10 ¹⁵ / cm ² . This implantation step completes the formation of the diode 302. The resulting structure is shown in FIG. 5B. Fabrication of the pin diode 302 is a method of the invention filed on the same date as the present application "Method to Form Upward-Pointing PIN Diodes Having Large and Uniform Current" In Herner US Patent No. It is described in more detail in the issue (agent document number SAND-01179US0). For example, some thickness of silicon of about 300 to about 800 angstroms is lost during CMP, thus the final height of diode 302 has a feature size of about 800 to about 4000 angstroms, for example, about 45 nm. Note that it can be about 2500 angstroms for the diode.

Turning to FIG. 5C, a layer 120 of silicide forming metal, such as, for example, titanium, cobalt, chromium, tantalum, platinum, niobium or palladium, is then deposited. Preferably, layer 120 is titanium or cobalt, and if layer 120 is titanium, its thickness is preferably about 10 to about 100 angstroms, most preferably about 20 angstroms. Layer 120 is followed by a titanium nitride layer 404. Layer 404 is preferably about 20 to about 100 angstroms, most preferably about 80 angstroms. Next, a layer 406 of conductive material such as, for example, tungsten is deposited. For example, this layer can be about 1500 angstroms of tungsten formed by CVD. Layers 406, 404, 120 are patterned and etched with rail-shaped top conductor 400, which preferably extends in a direction perpendicular to bottom conductor 200. The pitch and orientation of the top conductor 400 is such that each conductor 400 is formed on and in contact with the column of the column 300, and the conductor 400 has a width approximately equal to that of the column 300. desirable. Some misalignment can be tolerated.

Next, a dielectric material (not shown) is deposited between and over the conductor 400. The dielectric material may be any known electrically insulating material such as silicon oxide, silicon nitride or silicon oxynitride. In a preferred embodiment, silicon oxide is used as the dielectric material.

5C, it should be noted that the layer of silicide forming metal 120 is in contact with the silicon of the upper high doped region 116. During the subsequent high temperature step, the metal of layer 120 reacts with some of the silicon in the highly doped p-type region 116 to form a silicide layer (not shown), which is formed between the diode and the upper conductor 400. And, alternatively, this silicide layer may be considered to be part of the upper conductor 400. This silicide layer is formed at a temperature lower than the temperature required to crystallize the silicon, thus forming while the regions 112, 114, 116 are still mostly amorphous. When a silicon-germanium alloy is used in the upper high doping region 116, the silicide-germanide layer may be formed of cobalt silicide-germanide or titanium silicide-germanide, for example.

In the embodiment just described, the diode 302 of FIG. 5C includes a bottom high doped p-type region, a middle intrinsic region, and a top high doped n-type region. In a preferred embodiment, the next memory level to be monolithically formed above it shares conductor 400 with the first memory level just formed. That is, the upper conductor 400 of the first memory level functions as the lower conductor of the second memory level. If the conductors are shared in this manner, then the diode in the second memory level is preferably directed in the opposite direction, including the bottom high doped n-type region, the middle intrinsic region, and the top high doped p-type region. .

Turning to FIG. 5D, an optional conductive layer 210, a carbon nanotube fabric layer 218, and an optional conductive layer 211 are formed next, which are layers 110 of the pillar 300 of the first memory level. 118, 111, and the same material and the same thickness, it is preferable to use the same method.

Next, a diode is formed. Bottom high doped region 212 is formed by any deposition and doping method known in the art. Silicon is deposited and then doped, but is preferably doped in situ by flowing a donor gas that provides an n-type dopant atom, such as phosphorus, during deposition of silicon. The high doped region 212 is preferably about 100 to about 800 angstroms, most preferably about 100 to about 200 angstroms.

Next, the next semiconductor region to be deposited is preferably undoped. However, in deposited silicon, n-type dopants, such as phosphorus, exhibit strong interfacial behavior and tend to migrate towards the surface when silicon is deposited. Deposition of silicon continues without any dopant gas provided, but phosphorus atoms that move upward and seek to the surface unintentionally dope this region. The invention, which is incorporated herein by reference, is entitled “Deposited Semiconductor Structure to Minimize N-Type Dopant Diffusion and Method of Making” to minimize N-type dopant diffusion. As described in Herner's US patent application Ser. No. 11 / 298,331, filed May 9, the interfacial behavior of phosphorus in the deposited silicon is suppressed by the addition of germanium. It is preferred that a layer of silicon-germanium alloy comprising at least 10 at% germanium be deposited at this point. For example, it is desirable to deposit about 200 angstroms of Si _0.8 Ge _{0.2 which} is deposited undoped without using any dopant gas that provides phosphorus. This thin layer is not shown in FIG. 5D.

The use of this thin silicon-germanium layer maximizes its thickness by minimizing unintentional diffusion of the n-type dopant into the intrinsic region to be formed. The thicker intrinsic region minimizes leakage current across the diode when the diode is under reverse bias, reducing power loss. This method allows the thickness of the intrinsic region to be increased without increasing the overall height of the diode. As can be seen, the diodes are patterned into pillars, and increasing the height of the diodes increases the aspect ratio of the etching step to form these pillars and the step to fill the gap therebetween. As the aspect ratio increases, both etching and filling become more difficult.

Intrinsic region 214 may then be formed by any method known in the art. Region 214 is preferably silicon and preferably has a thickness of about 1100 to about 3300 angstroms, preferably about 1700 angstroms. Silicon in high doped region 212 and intrinsic region 214 is preferably amorphous upon deposition.

The semiconductor regions 214 and 212 immediately deposited along with the conductive layer 211, carbon nanotube fabric 218, and conductive layer 210 disposed below are patterned and etched to form pillars 500. The pillars 500 should have approximately the same pitch and approximately the same width as the conductors 400 below so that each pillar 500 is formed on top of the conductors 400. Some misalignment can be tolerated. Pillar 500 may be patterned and etched using the same techniques used to form pillar 300 of the first memory level.

Dielectric material 108 is deposited between and over semiconductor pillars 500 to fill gaps therebetween. As in the first memory level, the dielectric material 108 over the pillars 500 is removed to expose the top of the pillars 500 separated by the dielectric material 108, leaving a substantially flat surface. After this planarization step, ion implantation is performed to form the highly doped p-type top region 116. Preferably, the p-type dopant is a shallow implantation of boron having an implantation energy of 2 keV and a dosage of about 3 × 10 ¹⁵ / cm ² . This implantation step completes the formation of the diode 502. Some thickness of silicon is lost during the CMP step, so the finished diode 502 has a height similar to that of the diode 302.

The upper conductor 600 is formed of the same manner and the same material as the conductor 400 shared between the first and second memory levels. A layer 220 of silicide-forming metal is deposited, followed by a titanium nitride layer 604 and a layer 606 of conductive material, for example tungsten. The layers 606, 604, 220 are patterned and etched into the rail-shaped upper conductor 600, which preferably extends in a direction substantially perpendicular to the conductor 400 and substantially parallel to the conductor 200.

Each memory level may be annealed upon formation, but preferably, after all of the memory levels have been formed, a single crystallization anneal is performed, for example, at about 750 ° C. for about 60 seconds to remove the semiconductor material of diodes 302 and 502. Crystallize. The resulting diode is generally polycrystalline. Since the semiconductor material of these diodes is crystallized in contact with a silicide or silicide-germanide layer having good lattice match, the semiconductor material of diodes 302, 502, etc. is low-defect and low-resistance.

In the embodiment just described, the conductors are shared between memory levels. That is, the top conductor 400 of the first memory level functions as the bottom conductor of the second memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level of FIG. 5C, the surface of which is planarized, and the configuration of the second memory level on this planar interlevel dielectric without any shared conductors. Begins. In a given embodiment, the diode of the first memory level is downward oriented with p-type silicon on the bottom and n-type on the top, and the diode of the second memory level is n-type silicon on the bottom. Upward with a p-type on the top. In embodiments where the conductors are shared, the diode types are preferably alternately up on one level and down on the next level. In embodiments in which the conductors are not shared, the diodes may be of one type, either all downward or upward. The term upward or downward refers to the direction of current flow when the diode is under forward bias.

In the embodiment just described, referring to FIG. 5D, at the first memory level, the carbon nanotube fabric 118 is disposed between the diode 302 and the bottom conductor 200, and at the second memory level the diode 502. ) And the bottom conductor 400. In other embodiments, the carbon nanotube fabric element may be disposed between the vertically oriented diode and the top conductor.

In some embodiments, it may be desirable to apply a programming pulse to the diode with reverse bias. This is a method of using a memory cell comprising a switchable semiconductor memory element having a tunable resistance, which is owned by the assignee of the present invention and incorporated herein by reference. Semiconductor Memory Element With Trimmable Resistance, "as described in US Patent Application No. 11 / 496,986 to Kumar et al., Filed Jul. 28, 2006 to reduce leakage across unselected cells in the array. Or it may have the advantage of removing.

In summary, a first memory level formed monolithically over a substrate has been described, which comprises: i) a plurality of substantially parallel, substantially coplanar first bottom conductors, ii) a plurality of steering elements, iii. A) a plurality of first level carbon nanotube fabric elements, iv) a plurality of substantially parallel, substantially coplanar first top conductors and v) a plurality of first level memory cells, each first level memory The cell includes one steering element electrically arranged in series between one of the first bottom conductors and one of the first top conductors, and one first level carbon nanotube fabric element, (b) a first memory level The second memory level is formed in a monolith above.

A monolithic three dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate, such as a wafer, having no intervening substrate. Layers forming one memory level are grown or deposited directly on top of an existing level or layers of levels. In contrast, stacked memories form memory levels on separate substrates and store memory on top of each other, such as in Leedy's US Pat. No. 5,915,167, entitled "Three dimensional structure memory." It has been constructed by adhering levels. The substrate may be removed from thinning or memory levels prior to bonding, but since the memory levels are initially formed on a separate substrate, these memories are not truly monolithic three dimensional memory arrays.

A monolithic three dimensional memory array formed over a substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight or virtually any number of memory levels can be formed over the substrate in such a multilevel array.

An alternative method for forming a stacked memory array in which a conductor is formed using a damascene structure instead of using a substractive technique as in the provided embodiment is assigned to the assignee of the present invention. Radius, filed May 31, 2006, entitled "Conductive Hard Mask to Protect Patterned Features During Trench Etch," entitled "Conductive Hard Mask to Protect Patterned Features During Trench Etching," incorporated herein by reference. Described in US Patent Application No. 11 / 444,936 to Radigan et al. Radigan et al. May be used instead to form the array according to the invention. In the method of Radigan et al., Conductive hard masks are used to etch the diode under them. When applying this hard mask to the present invention, in a preferred embodiment, the bottom layer of the hard mask in contact with the silicon of the diode is preferably one of titanium, cobalt or other silicide-forming metals described above. Then, during annealing, silicide is formed to provide the silicide crystallization template described above.

Although a detailed manufacturing method has been described herein, any other method of forming the same structure may be used if the result is within the scope of the present invention.

The foregoing detailed description has described only a few of the many forms that the invention can take. For this reason, this detailed description is an illustration rather than a limitation. It is only the following claims, including all equivalents, that define the scope of the invention.

As mentioned above, the present invention is used to provide a memory array and a method of forming a memory array.

Claims (48)

In a memory cell, The first conductor, Steering element, Carbon nanotube fabric, The second conductor Including, The steering element and the carbon nanotube fabric are electrically arranged in series between the first conductor and the second conductor, And the entire memory cell is formed over a substrate. The memory cell of claim 1, wherein the substrate comprises single crystal silicon. The memory cell of claim 1 wherein the steering element is a junction diode. 4. The memory cell of claim 3 wherein the diode is a p-i-n diode. The memory cell of claim 4 wherein the diode is vertically oriented. 6. The memory cell of claim 5 wherein the second conductor is over the first conductor and the diode and the carbon nanotube fabric are disposed between the first conductor and the second conductor. The memory cell of claim 6, wherein the carbon nanotube fabric is disposed in permanent contact with the first and second metal or metallic elements between the first and second metal or metallic elements. 8. The memory cell of claim 7, wherein the first or second metal or metallic element comprises titanium nitride, tantalum nitride or tungsten. 8. The method of claim 7, wherein the first metal or metallic element is in permanent contact with the carbon nanotube fabric under the carbon nanotube fabric and the second metal or metallic element is on the carbon nanotube fabric. A memory cell in permanent contact with the tube fabric. 7. The memory cell of claim 6, further comprising a silicide layer disposed between the second conductor and the diode. The memory cell of claim 10, wherein the silicide layer is titanium silicide or cobalt silicide. 12. The memory cell of claim 11, wherein the second conductor comprises a bottom layer, wherein the bottom layer is titanium or cobalt. The memory cell of claim 6, wherein the carbon nanotube fabric is disposed between the first conductor and the diode. 5. The memory cell of claim 4 wherein the diode comprises a bottom high doping n-type region, a middle intrinsic or light doping region, and a top high doping p-type region. 15. The memory cell of claim 14 wherein the intermediate intrinsic or light doped region comprises a silicon-germanium layer. The memory cell of claim 15, wherein the silicon-germanium layer is at least 10 at% germanium. 2. The memory cell of claim 1 wherein the steering element is a thin film transistor having a channel region formed in a polycrystalline semiconductor material. The memory cell of claim 1, wherein the data state of the memory cell is stored in the resistive state of the carbon nanotube fabric. In a monolithic three dimensional memory array, (a) a first memory level formed monolithically on a substrate, (b) a second memory level formed monolithically over said first memory level; Including, The first memory level is, i) a plurality of substantially parallel, substantially coplanar first bottom conductors, ii) a plurality of control elements, iii) a plurality of first level carbon nanotube fabric elements, iv) a plurality of substantially parallel, substantially coplanar first upper conductors, v) a plurality of first level memory cells, wherein each first level memory cell is electrically arranged in series between one of the first bottom conductors and one of the first top conductors; A plurality of first level memory cells comprising one of the tube fabric elements and one of the steering elements; A monolithic three dimensional memory array comprising. 20. The monolithic three dimensional memory array of claim 19 wherein the substrate comprises single crystal silicon. 22. The monolithic three dimensional memory array of claim 21 wherein each steering element is a first level junction diode. 22. The monolithic three dimensional memory array of claim 21 wherein each steering element is a first level p-i-n diode. 23. The unitary three-dimensional memory array of claim 22 wherein each first level p-i-n diode is vertically oriented. 24. The monolithic three dimensional memory array of claim 23 wherein in each first level memory cell, the first top conductor is over the first bottom conductor. 25. The monolithic three dimensional memory array of claim 24 wherein each first level memory cell further comprises a silicide layer disposed between one of the first level p-i-n diodes and one of the first upper conductors. 26. The monolithic three dimensional memory array of claim 25 wherein the silicide layer is titanium silicide or cobalt silicide. 27. The monolithic three dimensional memory array of claim 26 wherein each of the first top conductors comprises a bottom layer, wherein the bottom layer is titanium or cobalt. 25. The unitary three-dimensional memory array of claim 24 wherein each carbon nanotube fabric element is disposed between one of the first level p-i-n diodes and one of the first bottom conductors. 23. The monolithic three dimensional memory array of claim 22 wherein each first level p-i-n diode comprises a bottom high doped n-type region, an intermediate intrinsic or light doped region, and an upper high doped p-type region. 20. The device of claim 19, wherein the second memory level comprises a plurality of second level memory cells, each second level memory cell comprising a second level pin diode, and each second level pin diode being a bottom high. A monolithic three dimensional memory array comprising a doped p-type region and an intermediate intrinsic or light doped region and an upper highly doped n-type region. 31. The device of claim 30, wherein the second memory level comprises a second plurality of bottom conductors and a second plurality of top conductors, wherein each second level pin diode is one of the second bottom conductors and the second top conductor. And a bottom conductor of the second memory level and a top conductor of the first memory level are shared between one of the conductors. 23. The unitary three-dimensional memory array of claim 22 wherein each first level p-i-n diode comprises a bottom high doped p-type region, an intermediate intrinsic or light doped region, and an upper high doped n-type region. 33. The device of claim 32, wherein the second memory level comprises a plurality of second level memory cells, each second level memory cell comprising a second level pin diode, and each second level pin diode being a bottom high. A monolithic three dimensional memory array comprising doped n-type regions, intermediate intrinsic or light doped regions, and upper high doped p-type regions. 20. The monolithic three dimensional memory array of claim 19 wherein each steering element is a thin film transistor. In a method of programming carbon nanotube memory cells, The memory cell comprises a first conductor, a steering element, a carbon nanotube fabric and a second conductor, wherein the steering element and the carbon nanotube fabric are electrically arranged in series between the first conductor and the second conductor. Wherein the entire carbon nanotube memory cell is formed over a substrate, the carbon nanotube fabric has a first resistance, The method, Applying a first electrical set pulse between the first conductor and the second conductor Including, After application of the first electrical set pulse, the carbon nanotube fabric has a second resistance, the second resistance being lower than the first resistance. 36. The method of claim 35, further comprising after applying the first electrical set pulse, applying a first electrical reset pulse across the steering element and the carbon nanotube fabric, After applying the first electrical reset pulse, the carbon nanotube fabric has a third resistance, wherein the third resistance is higher than the second resistance. 37. The method of claim 36, wherein the data state of the carbon nanotube memory cell is stored in a first, second, or third resistive state of the carbon nanotube fabric. 36. The method of claim 35, wherein the steering element is a diode. 39. The method of claim 38, wherein the diode is a junction diode. 40. The method of claim 39, wherein the diode is a vertically oriented p-i-n diode. 41. The method of claim 40, wherein the first conductor is over the substrate, the second conductor is over the first conductor, and the diode and the carbon nanotube fabric are perpendicular to the first conductor and the second conductor. To program a carbon nanotube memory cell. 42. The method of claim 41 wherein the memory cell further comprises a silicide layer in contact with the diode. 43. The method of claim 42, wherein the silicide layer is titanium silicide or cobalt silicide. 42. The carbon nanotube fabric of claim 41, wherein the carbon nanotube fabric is disposed between the top electrode and the bottom electrode and in contact with the top electrode and the bottom electrode, wherein the top electrode is directly over the carbon nanotube fabric and the bottom electrode is the carbon A method of programming carbon nanotube memory cells, directly under the nanotube fabric. 37. The memory cell of claim 36, wherein a read voltage is applied between the first conductor and the second conductor after applying the first electrical set pulse and before applying the first electrical reset pulse. Sensing the first data state of the carbon nanotube memory cell. 46. The method of claim 45, further comprising applying a read voltage between the first conductor and the second conductor after applying the first electrical reset pulse to sense a second data state of the memory cell; Wherein the first data state and the second data state are different. 37. The method of claim 36, wherein the steering element is a thin film transistor, the thin film transistor having a channel layer formed in a polycrystalline semiconductor material. 36. The method of claim 35, wherein the substrate comprises single crystal silicon.

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