KR20100011478A - Conductive pattern in semiconductor device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A conductive pattern in a semiconductor device and a method for stably forming the pattern are provided to improve the resistance of a conductive pattern by forming the conductive pattern into the laminated structure of the metal layer and a metal silicide layer. CONSTITUTION: A first insulating layer(103) is formed in the junction area(101a) of the semiconductor substrate(101). A damascene pattern(105) is formed in order to expose the junction area. A metal silicide layer is formed in the bottom surface of a damascene pattern. The metal silicide layer is changed to a more stable metal silicide layer(115). A barrier layer(117) is formed in the surface of a first insulating layer including the upper side of the metal silicide layer and the surface of the damascene pattern. A second metal layer(119) is formed on the barrier layer. The upper side of the first insulating layer is exposed by eliminating the second metal layer and the barrier layer.

Description

Conductive pattern in semiconductor device and manufacturing method thereof

The present invention relates to a conductive pattern of a semiconductor device and a method of forming the same. In particular, even when a metal is introduced into the conductive pattern formed inside the damascene pattern, the conductive pattern is stably prevented from occurring in the conductive pattern. The present invention relates to a conductive pattern of a semiconductor device and a method of forming the same.

The semiconductor device includes a plurality of conductive patterns, and each conductive pattern is filled with a conductive material in a damascene pattern such as a contact hole and a trench formed by etching an insulating film, and then chemical mechanical polishing (hereinafter, “. CMP ") through a series of processes that leave the conductive material only inside the contact holes. As such, the size of the damascene pattern defining the region in which the conductive pattern is to be formed is decreasing as the semiconductor device is highly integrated, and the gap between the damascene patterns is getting closer. Accordingly, there is a difficulty in performing an etching process for forming a damascene pattern.

It is difficult to proceed with the process for forming a contact hole exposing the junction region of the flash memory device among the damascene patterns. This is because the contact hole exposing the junction region of the flash memory device must expose the junction region formed on the semiconductor substrate on both sides of the gate pattern by etching the insulating film covering the gate pattern formed by stacking a plurality of thin films. In more detail, the gate pattern of the flash device is formed by stacking a floating gate film, a dielectric film, and a control gate film. Impurity ions are implanted into the semiconductor substrate using the gate pattern as a mask to form a junction region. As semiconductor devices become more integrated, the narrower the gap between gate patterns, the smaller the width of the junction region, the smaller the size of the contact hole exposing the junction region, and the shorter the distance between the contact holes. Accordingly, the aspect ratio of the contact hole increases, so it is difficult to simultaneously secure the critical line widths of the upper surface of the contact hole and the lower portion of the contact hole. In other words, when the semiconductor device is highly integrated, securing the line width of the upper surface of the contact hole may cause a problem in that it is impossible to secure the critical line width under the contact hole. In order to solve this problem, when the contact hole is formed by adjusting the etching degree, a bowing phenomenon occurs in which sidewalls of an intermediate depth of the insulating layer are excessively etched. Due to the bowing phenomenon, the upper portion of the contact hole is formed in an overhang structure. Thereafter, a contact plug having a conductive pattern is formed in the contact hole of the overhang structure. The contact plug is formed through a series of processes in which the inside of the contact hole of the overhang structure is filled with a conductive material and then the conductive material is left only in the contact hole by the CMP method. Recently, metals have been introduced as conductive materials to improve the resistance of contact plugs. However, due to the overhang structure, seams are generated in the process of filling the inside of the contact hole with a conductive material. When the conductive material is a metal, H ₂ O _{2 is} included in the slurry used in the CMP process to remove the metal formed on the insulating film. However, the shim described above provides a path of penetration of H ₂ O ₂ , causing the problem of removing some or all of the conductive material formed inside the contact hole. As such, when some or all of the conductive material formed in the contact hole is removed, the contact plug is abnormally formed or the contact plug is not formed.

The contact plug must electrically connect the junction region and the metal wiring formed on the contact plug so that a voltage can be applied to the transistor of the semiconductor device. However, as described above, when a metal is introduced to lower the resistance, H ₂ O ₂ penetrates into a core generated as the aspect ratio increases, causing loss of a contact plug, thereby causing a problem in that the semiconductor device does not operate.

The present invention provides a conductive pattern of a semiconductor device and a method of forming the conductive pattern so that the conductive pattern can be stably formed inside the damascene pattern by preventing metal from being generated in the conductive pattern even when a metal is introduced into the conductive pattern formed inside the damascene pattern. To provide.

The conductive pattern of the semiconductor device according to the present invention includes an insulating film formed on a semiconductor substrate including a damascene pattern, a metal silicide film formed inside the damascene pattern at a lower height than the damascene pattern, and a damascene opening on the upper surface of the metal silicide film. And a metal film filling the inside of the pattern.

A method of forming a conductive pattern according to the present invention includes the steps of forming an insulating film including a damascene pattern on a semiconductor substrate, forming a metal silicide film inside the damascene pattern to a lower height than the damascene pattern, and the upper portion of the metal silicide film Forming a first metal layer in the damascene pattern opened in

The forming of the metal silicide film inside the damascene pattern may include forming a polysilicon film inside the damascene pattern to a height lower than that of the damascene pattern, and forming a second silicon on the surface of the insulating film including an upper surface of the polysilicon film and a surface of the damascene pattern. Forming a film, reacting the second metal film and the polysilicon film to form a metal silicide film of an initial phase inside the damascene pattern, and converting the metal silicide film of the initial phase into a metal silicide film that is more stable than the metal silicide film of the initial phase. It includes.

In the step of forming the polysilicon film inside the damascene pattern at a height lower than that of the damascene pattern, the height of the damascene pattern opened at the top of the polysilicon layer is preferably 30% to 40% of the total height of the damascene pattern.

The second metal film contains Ni.

The metal silicide film contains NiSi ₂ , and the initial phase metal silicide film contains NiSi.

Forming the metal silicide film of the initial phase is carried out using an annealing process at a temperature of 450 ℃ to 600 ℃.

The phase change of the metal silicide film of the initial phase into the metal silicide film is carried out using an annealing process at a temperature of 800 ° C to 950 ° C.

After forming the second metal film on the top surface of the polysilicon film and the surface of the insulating film including the surface of the damascene pattern, the method further includes forming a TiN film on the second metal film.

After the forming of the metal silicide film on the initial phase, the TiN film and the second metal film remaining without reacting are further included.

It is preferable that the thickness of a 2nd metal film is 200 kPa-300 kPa.

The thickness of the TiN film is preferably 100 kPa to 150 kPa.

After forming the metal silicide film, the method further includes forming a barrier film on the surface of the insulating film including the top surface of the metal silicide film and the surface of the opened damascene pattern.

The forming of the first metal film in the damascene pattern opened on the upper portion of the metal silicide film includes forming a first metal film on the barrier film, and removing the barrier film and the first metal film formed on the insulating film.

The metal film contains tungsten.

The present invention forms a metal silicide on the lower portion of the damascene pattern to lower the aspect ratio of the damascene pattern and then embeds the damascene pattern with the metal material, thereby preventing the generation of seams in the metal material, thereby removing the metal material inside the damascene pattern. Can be prevented. As a result, the present invention can stably form the conductive pattern inside the damascene pattern, thereby preventing the defect of the semiconductor device.

In addition, the present invention can improve the resistance of the conductive pattern because the conductive pattern formed inside the damascene pattern is formed in a laminated structure of the metal silicide film and the metal film.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided to inform you completely.

1A to 1K are cross-sectional views illustrating a conductive pattern of a semiconductor device and a method of forming the same according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a first insulating layer 103 including a plurality of damascene patterns 105 is formed on a semiconductor substrate 101.

Wells and threshold voltage ions are implanted into the semiconductor substrate 101, and gate patterns (not shown) are formed on the semiconductor substrate 101 with a gate insulating film (not shown) interposed therebetween, and semiconductors on both sides of the gate pattern are formed. The substrate 101 may be in a state where the junction region 101a is formed.

The first insulating layer 103 is formed on the semiconductor substrate 101 on which the gate pattern is formed so as to electrically isolate the gate pattern. In the case of a flash device, the gate pattern may have a structure in which a floating gate, a dielectric film, and a control gate are stacked.

The damascene pattern 105 may be a contact hole formed to expose a junction region previously formed in the semiconductor substrate 101 at both sides of the gate pattern. The damascene pattern 105 may be formed on the junction region 101a by using a hard mask pattern (not shown) formed on the first insulating layer 103 as an etching mask after the first insulating layer 103 is formed. It is formed by etching the insulating film 103. The hard mask pattern may be formed by stacking SiON / amorphous carbon / SiON. In addition, the first insulating layer 103 may be formed using an oxide layer. The hard mask pattern may be removed in the process of etching the first insulating layer 103 or may be removed through a separate etching process. The damascene pattern 105 formed in the first insulating layer 103 through the above-described process defines an area in which the conductive pattern is to be formed by opening to the first height h1. The conductive pattern may be for electrically connecting the bit line formed on the first insulating layer 103 to the junction region 101a in a subsequent process.

Referring to FIG. 1B, a cleaning process is performed to remove residues generated after the damascene pattern 105 is formed, and the polysilicon 107 is formed on the first insulating layer 103 to fill the interior of the damascene pattern 105. ). Since the polysilicon 107 has better embedding characteristics than the metal material, it is possible to improve seam generation.

Referring to FIG. 1C, a portion of the polysilicon 107 formed on the upper portion of the first insulating layer 103 and the damascene pattern 105 is removed. As a result, the polysilicon 107 remains inside the damascene pattern 105 at a height lower than the height of the damascene pattern 105, and the second height h2 opened in the damascene pattern 105 is shown in FIG. 1A. It becomes lower than the first height h1 described above. In other words, the aspect ratio of the opened portion of the damascene pattern 105 is lowered by the polysilicon 107 filling the bottom surface of the damascene pattern 105. The second height h2 is preferably 30% to 40% of the first height h1 in order to prevent the seam from being generated in the metal material filling the inside of the damascene pattern 105 in a subsequent process.

The process of removing a portion of the polysilicon 107 formed on the upper portion of the first insulating layer 103 and the damascene pattern 105 may be performed through an etching process such as an etch back.

Referring to FIG. 1D, the first metal layer 109 and the capping layer may be formed on the surface of the insulating layer 103 including the upper surface of the polysilicon 107 remaining inside the damascene pattern 105 and the surface of the damascene pattern 105. 111).

The first metal film 109 is formed to react with the polysilicon 107 in a subsequent process to form a metal silicide film on the bottom of the damascene pattern 105, and preferably includes Ni. It is preferable that the thickness of such a 1st metal film 109 is 200 kPa-300 kPa. In addition, the first metal layer 109 may be formed by a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) method.

The capping film 111 is a film formed to prevent the first metal film 109 from being oxidized while the metal silicide film of the initial phase is formed in a subsequent process, and preferably includes TiN. The thickness of the capping film 111 is preferably 100 kPa to 150 kPa.

The first metal layer 109 and the capping layer 111 described above may be deposited by an in-situ method.

Referring to FIG. 1E, the first metal layer 109 and the polysilicon 107 described above in FIG. 1D may be reacted to form an initial metal silicide layer 113 on the bottom surface of the damascene pattern 105.

In order to form the initial metal silicide film 113 by reacting the first metal film (109 in FIG. 1D) and polysilicon (107 in FIG. 1D), an annealing process is performed at a temperature of 450 ° C to 600 ° C. do. At this time, when the first metal film (109 in Fig. 1D) is formed of Ni, the metal silicide film 113 of the initial phase is formed of NiSi.

Referring to FIG. 1F, the first metal film (109 of FIG. 1E) and the capping film (111 of FIG. 1E) that remain unreacted are removed to leave only the initial metal silicide film 113 inside the damascene pattern 105. . The first metal layer 109 of FIG. 1E and the capping layer 111 of FIG. 1E may be removed through an etching process, and the metal silicide layer 113 of the initial phase may be removed from the first metal layer (see FIG. 1E). 109) and the etching selectivity difference between the capping layer (111 in FIG. 1E) is large and is not removed.

Referring to FIG. 1G, the metal silicide film (113 in FIG. 1F) of the initial phase is changed into a metal silicide film 115 which is a more stable phase. The phase change of the metal silicide film (113 in FIG. 1F) of the initial phase may be made by performing an annealing process at a temperature of 800 ° C to 950 ° C. When the first metal film (109 in FIG. 1D) is formed of Ni, the metal silicide film 115 is formed of NiSi ₂ .

Since the metal silicide layer 115 is formed on the bottom surface of the damascene pattern 105, the aspect ratio of the damascene pattern 105 is lower than that in FIG. 1A and the specific resistance is lower than that of the polysilicon. The resistance of the conductive pattern formed therein can be improved.

1H and 1I, after the barrier film 117 is formed on the surface of the first insulating film 117 including the upper surface of the metal silicide film 115 and the surface of the damascene pattern 105, the barrier film 117 is formed. ) A second metal film 119 is formed.

The barrier film 117 is formed to improve the adhesion of the second metal film 119 formed in a subsequent process and to prevent the diffusion of metal ions into the lower film. The barrier film 117 includes TiN. desirable.

The second metal film 119 is formed to have a sufficient thickness so as to fill all the upper portions of the opened damascene pattern 105. The second metal layer 119 is formed to further improve the resistance of the conductive pattern formed in the damascene pattern 105, and may be formed by depositing tungsten (W) by CVD. In the second metal layer 119 having a poor embedding property as compared to polysilicon, the lower portion of the damascene pattern 105 is buried by the metal silicide layer 115 so that the aspect ratio of the opened portion of the damascene pattern 105 is lowered. Is formed in the state. Accordingly, the phenomenon in which seams are generated in the second metal film 119 is improved.

Referring to FIG. 1J, the upper surface of the first insulating layer 103 is exposed by removing the second metal layer 119 and the barrier layer 117 formed on the first insulating layer 103. Accordingly, the barrier film 117 and the second metal film 119 are formed only in the damascene pattern 105. As a result, a conductive pattern 121 including the metal silicide layer 115, the barrier layer 117, and the second metal layer 119 is formed in the damascene pattern 105, and the conductive patterns 121 adjacent to each other are formed. Is insulated with the first insulating film 103 therebetween. In more detail, the conductive pattern 121 has a “U” shape along the metal silicide layer 115 formed on the bottom surface of the damascene pattern 105, the top surface of the metal silicide layer 115, and sidewalls of the damascene pattern 105. The barrier layer 117 and the second metal layer 119 formed inside the damascene pattern 105 on the barrier layer 117 are included.

The process of removing the second metal film 119 and the barrier film 117 formed on the first insulating film 103 may be performed by using chemical mechanical polishing (hereinafter, referred to as "CMP") method. Can be. In the present invention, since the second metal film 119 is formed in the state in which the aspect ratio of the opening of the damascene pattern 105 is reduced, it is possible to prevent the seam from being generated in the second metal film 119. It is possible to prevent the included H ₂ O ₂ from penetrating into the second metal film 119. Accordingly, since the second metal film 119 formed inside the damascene pattern 105 may be improved, the conductive pattern 121 may be stably formed, thereby improving defects in the semiconductor device. have.

Referring to FIG. 1K, the second insulating layer 123 is formed on the surface of the first insulating layer 103 including the conductive pattern 121 to insulate the upper wiring formed in the subsequent process and the conductive pattern 121. An oxide film may be used as the second insulating film 123.

Thereafter, a subsequent step of forming an upper wiring is performed.

As described above, in the present invention, the bottom surface of the damascene pattern is first filled with polysilicon having better embedding characteristics than the metal layer, and then the seam is prevented from occurring in the metal layer by filling the opening of the remaining damascene pattern with the metal layer. can do. Since the seam can be prevented from occurring in the metal film, the present invention can improve a phenomenon in which the metal film is lost during the CMP process, thereby stably forming a conductive pattern including the metal film. In addition, it is possible to improve the resistance of the conductive pattern formed inside the damascene pattern by changing the polysilicon film formed on the bottom surface of the damascene pattern to a metal silicide by reacting with the metal film.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1K are cross-sectional views showing a conductive pattern of a semiconductor device and a method of forming the same according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: semiconductor substrate 103, 123: insulating film

105: damascene pattern 107: polysilicon film

109, 119: metal film 111: capping film

113: initial metal silicide film 115: metal silicide film

117: barrier film 121: conductive pattern

Claims (18)

An insulating film formed on the semiconductor substrate including the damascene pattern; A metal silicide layer formed inside the damascene pattern at a height lower than that of the damascene pattern; And A conductive pattern of a semiconductor device comprising a metal film to fill the inside of the damascene pattern opened on the metal silicide film. The method of claim 1, And a barrier film is further formed between the metal silicide film and the metal film and between the insulating film and the metal film. The method of claim 1, The metal silicide layer includes NiSi ₂ . The method of claim 1, The metal layer is a conductive pattern of a semiconductor device containing tungsten. Forming an insulating film including a damascene pattern on the semiconductor substrate; Forming a metal silicide layer in the damascene pattern at a height lower than that of the damascene pattern; And And forming a first metal film inside the damascene pattern opened on the metal silicide layer. The method of claim 5, wherein Forming a metal silicide layer in the damascene pattern Forming a polysilicon film inside the damascene pattern at a height lower than that of the damascene pattern; Forming a second metal film on a surface of the insulating film including an upper surface of the polysilicon film and a surface of the damascene pattern; Reacting the second metal film and the polysilicon film to form an initial phase metal silicide film in the damascene pattern; And And converting the metal silicide film of the initial phase into the metal silicide film which is more stable than the metal silicide film of the initial phase. The method of claim 6, In the step of forming a polysilicon film inside the damascene pattern to a lower height than the damascene pattern, the height of the damascene pattern opening in the upper portion of the polysilicon layer is 30% to 40% of the total height of the damascene pattern Method for forming a conductive pattern of the device. The method of claim 6, The second metal film is a conductive pattern forming method of a semiconductor device containing Ni. The method of claim 6, The metal silicide film comprises NiSi ₂ , and the metal silicide film in the initial phase comprises NiSi. The method of claim 6, Forming the metal silicide film of the initial phase is a conductive pattern forming method of a semiconductor device is carried out using an annealing process at a temperature of 450 ℃ to 600 ℃. The method of claim 6, Phase shifting the metal silicide film of the initial phase to the metal silicide film is carried out using an annealing process at a temperature of 800 ℃ to 950 ℃. The method of claim 6, After the step of forming a second metal film on the surface of the insulating film including the upper surface of the polysilicon film and the surface of the damascene pattern, And forming a TiN film on the second metal film. The method of claim 12, And forming a metal silicide film on the initial phase, and then removing the TiN film and the second metal film remaining unreacted. The method of claim 12, The thickness of the second metal film is a method of forming a conductive pattern of a semiconductor device 200 ~ 300Å. The method of claim 6, The TiN film has a thickness of 100 kPa to 150 kPa, the conductive pattern forming method of a semiconductor device. The method of claim 5, wherein After the metal silicide film is formed, And forming a barrier film on a surface of the insulating film including an upper surface of the metal silicide layer and a surface of the opened damascene pattern. The method of claim 16, Forming a first metal film in the damascene pattern opened on the upper surface of the metal silicide film Forming the first metal film on the barrier film; And removing the barrier layer and the first metal layer formed on the insulating layer. The method of claim 5, wherein The metal film is a conductive pattern forming method of a semiconductor device containing tungsten.

Images