KR20100010673A - Nonvolatile memory device, reading and driving method thereof - Google Patents

Abstract

The present invention provides a method, a driving method, and a device for implementing the same, which can stably read a memory cell state even after repeated E / W cycling. To this end, the present invention provides a plurality of strings including a plurality of memory cells connected in series between first and second select transistors, a plurality of word lines for selecting the memory cells, and a plurality of bit lines for selecting the strings. A read method of a nonvolatile memory device, comprising: reading a non-volatile memory device by boosting and supplying a read voltage supplied to a selected bit line among the bit lines according to the number of cycles of erase and write operations during a read operation. Provide a method.

Description

NONVOLATILE MEMORY DEVICE, READING AND DRIVING METHOD THEREOF

The present invention relates to a method of driving a semiconductor device, and more particularly, to a method of driving a semiconductor memory device, and more particularly, to a method of reading a nonvolatile memory device.

NAND type flash memory devices, which are nonvolatile memory devices, form a unit string by connecting a plurality of cells in series for high integration, and are mainly a memory stick and a USB driver (Universal Serial Bus). As a device that can replace a driver and a hard disk, the application field is expanding.

1 is an equivalent circuit diagram illustrating a memory cell array of a general NAND flash memory device. Here, as an example, a string structure consisting of 32 memory cells is illustrated.

As shown in FIG. 1, a general NAND flash memory device is composed of a plurality of memory blocks. The memory block includes a plurality of strings ST. The string ST may include a drain select transistor DST (hereinafter referred to as a first select transistor) and a source select transistor SST (hereinafter referred to as a second select transistor), and a first and second select transistors DST, It consists of a plurality of memory cells MC0 to MC31 connected in series between the SSTs. In addition, the source of the second selection transistor SST is commonly connected to the common source line CSL. The gate of the first select transistor DST is connected to the drain select line DSL, and the gate of the second select transistor SST is connected to the source select line SSL. In addition, the control gates of the memory cells MC0 to MC31 are connected to the word lines WL0 to WL31, respectively.

A reading method of a NAND flash memory device having such a configuration will be described below. As an example, the read operation of the 'MC29' memory cell in FIG. 1 will be described.

Line / bias BL0 DSL SSL CSL W29 (selection cell) WL0 to WL28, WL30, WL31 (non-selected cells) Voltage Vread Vpass Vpass VSS Vgate Vpass

In Table 1, 'Vpass' is a pass voltage capable of turning on a memory cell regardless of the state (write or erase state) of the memory cell. 'Vread' is a read voltage applied to the selected bit line and is about a power supply voltage. 'VSS' means a ground voltage of 0V. In addition, 'Vgate' is a gate voltage applied to the selected word line and is approximately '0V'.

First, the case where 'MC29' is an erase cell will be described.

Referring to FIGS. 1 and 1, in the read operation performed after the write verify operation or the write operation, a gate voltage Vgate of '0 V' is applied to the selection word line W29 connected to the selection cell MC29. The pass voltage Vpass is applied to the unselected word lines WL0 to WL28, WL30 and WL31 connected to the unselected cells MC0 to MC28, MC30 and MC31. In addition, a read voltage Vread is applied to the select bit line BL0. In addition, a pass voltage Vpass is applied to the drain select line DSL and the source select line SSL connected to the first and second select transistors DST and SST, respectively.

Under such a bias condition, the first and second selection transistors DST and SST and the unselected cells MC0 to MC28, MC30 and MC31 are turned on. The erase select cell MC29 is also turned on. Accordingly, a current path is formed between the selection bit line BL0 and the common source line CSL, and the read voltage Vread precharged to the selection bit line BL0 is converted to the common source line CSL. Discharged. Therefore, since the select bit line BL0 drops to '0 V', the select cell MC29 is read into the erase cell through the page buffer (not shown).

On the other hand, the case where 'MC29' is a write cell will be described.

When the selection cell MC29 is a write cell, the threshold voltage is higher than the gate voltage Vgate so that it is not turned on and remains in a turn-off state. Accordingly, the current path between the selection bit line BL0 and the common source line CSL is blocked by the selection cell MC29. Therefore, since the read voltage Vread precharged to the select bit line BL0 cannot be discharged to the common source line CSL, the select cell MC29 is read into the write cell through the page buffer.

However, in the case of applying the conventional NAND flash memory device reading method, no problem occurs in the read operation during the initial operation, but repeated E / W cycling (repetitive erase and write operations). After that, a problem occurred.

2 is a diagram illustrating a threshold voltage distribution after a write operation of a memory cell with respect to the number of E / W cyclings. The X axis represents the number of memory cells, and the Y axis represents the threshold voltage after a write operation. In FIG. 2, in the portion representing the number of E / W cycling, 'Initial' represents an initial state representing a number of times less than or equal to '1K', and '1K' represents 1000 times.

As shown in FIG. 2, it can be seen that as the number of E / W cycling increases, the threshold voltage (see A) of the memory cell increases after the write operation. This is because electrons and the like are trapped in the tunnel insulation film after repeated E / W cycling, thereby deteriorating the tunnel insulation film.

In a normal read operation, when a pass voltage is applied to an unselected memory cell gate, the cell should be turned on regardless of the state of the memory cell. However, when the tunnel insulation layer is deteriorated, since the threshold voltage of the write cell is already higher than the pass voltage, the memory cell is not turned on even when the pass voltage is applied. As a result, no current flows in the string, which results in a failure to read the state of the memory cell, resulting in poor processing.

Accordingly, the present invention has been proposed to solve the problems according to the prior art, and a nonvolatile memory device capable of stably reading a state of a memory cell even after a large number of repeated E / W cycling, and a method of reading and driving the same. The purpose is to provide.

According to an aspect of the present invention, a plurality of strings including a plurality of memory cells connected in series between first and second selection transistors, a plurality of word lines for selecting the memory cells, A read method of a nonvolatile memory device having a plurality of bit lines connected to each of the strings, the method comprising: during a read operation, a number of cycles of erase and write operations of a read voltage supplied to a selected bit line among the bit lines; The present invention provides a method of reading a nonvolatile memory device by boosting and supplying the same.

According to another aspect of the present invention, there is provided a plurality of strings including a plurality of memory cells connected in series between first and second selection transistors, and a plurality of words for selecting the memory cells. A method of driving a nonvolatile memory device having a line and a plurality of bit lines connected to the string, the method comprising: performing a read operation by applying a first read voltage to a selected bit line among the bit lines; Performing an erase and write operation on a selected memory cell among the memory cells, detecting the number of cyclings of the erase and write operations, and if the number of cyclings of the erase and write operations is equal to or greater than a set first reference number; And performing a read operation by supplying a second read voltage higher than the first read voltage to the select bit line. It provides a driving method of a volatile memory device.

According to still another aspect of the present invention, there is provided a plurality of strings including a plurality of memory cells connected in series between first and second selection transistors, and a plurality of strings for selecting the memory cells. A word line, a plurality of bit lines respectively connected to the string, and a read voltage generator configured to supply a read voltage to a selected bit line among the bit lines, wherein the read voltage generator is configured to read the read voltage during a read operation. The present invention provides a nonvolatile memory device in which a voltage of the selected memory cells is boosted and supplied according to the number of cycles of erase and write operations of the selected memory cells.

According to the present invention having the above-described configuration, the number of cyclings of the erase and write operations is performed by supplying the read voltage by increasing the read voltage according to the number of times of E / W cycling, that is, the repeated cycling of the erase and write operations, during the read operation. As the value increases, the current flowing through the selection bit line which decreases in response to the deterioration of the tunnel insulation layer may be increased to compensate for the decrease in the selection bit line current reduced by the degradation of the tunnel insulation layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals (or reference numerals) throughout the specification represent the same components.

Example

3 is a flowchart illustrating a method of driving a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, a reading method in a method of driving a nonvolatile memory device according to an embodiment of the present invention will be described. In the read method according to the exemplary embodiment of the present invention, since the bias condition other than the read voltage supplied to the selected bit line is the same as the general bias condition, a detailed description of other bias conditions except for the read voltage will be omitted. In addition, the read operation includes both a write verification operation and a normal read operation performed for each loop in the incremental step pulse programming scheme (ISPP).

The read method of the nonvolatile memory device according to the embodiment of the present invention boosts and supplies the read voltage to the selection bit line according to the number of times of E / W cycling, that is, repeated cycling of the erase and write operations. That is, as in the prior art, the read voltage is boosted and supplied according to the number of cycles rather than the read voltages having the same voltage magnitude collectively regardless of the number of repeated cycles of erase and write operations.

On the other hand, in the present invention, the number of cycles of the erase and write operations may be counted one time after each operation is completed independently of the erase operation and the write operation, or may be counted once after both operations are completed by including the erase operation and the write operation. have. In addition, in the case of the write operation, the write operation may be counted once after the write operation is completed for all blocks constituting the memory cell array, or may be counted once after the write operation for one block is completed.

As described in the prior art, the tunnel insulating film of the memory cell is trapped by electrons and degraded by cycling of repeated erase and write operations. Deterioration of the tunnel insulating film is increased in correspondence to the number of cycling of the erase and write operations. The degradation of the tunnel insulation layer reduces the current flowing through the selection bit line during the read operation, and uses the sensing current (a current value as a reference for determining whether it is '1' or '0' when sensing data in the page buffer). The select bit line makes it impossible to reliably detect the memory cell state.

Therefore, in the present invention, the erase and write operations are performed in order to increase the current flowing through the selection bit line (hereinafter, the selection bit line current) which decreases in response to the deterioration of the tunnel insulating layer as the number of cycling of the erase and write operations increases. The reading voltage is boosted and supplied according to the number of cycling. That is, the reduction voltage is compensated by boosting the read voltage to correspond to the decrease value of the selected bit line current reduced by the deterioration of the tunnel insulation layer.

Hereinafter, a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIG. 4.

4 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention. For convenience of description, only one page buffer PB connected to two bit lines BLe and BLo is shown. For example, a read operation of the memory cell of the string ST connected to the even-numbered bit line BLe among the two bit lines BLe and BLo will be performed.

Referring to FIG. 4, a nonvolatile memory device according to an embodiment of the present invention includes a memory cell array MCA. The memory cell array MCA includes one or a plurality of blocks, and each block is a plurality of memory cells MC0 to MC31 connected in series between the first and second selection transistors DST and SST. A plurality of strings (ST) made up.

In addition, the nonvolatile memory device according to an exemplary embodiment of the present invention may include a plurality of word lines WL0 to WL31 and strings connected to gates of the memory cells MC0 to MC31 to select memory cells MC0 to MC31. In order to select ST, a plurality of bit lines BLe and BLo connected to the drain of the first selection transistor DST are provided. Here, the number of memory cells MC0 to MC31, word lines WL0 to WL31, and bit lines BLe and BLO is not limited.

In addition, the nonvolatile memory device according to the embodiment of the present invention further includes a page buffer PB for detecting memory cell data from a pair of bit lines BLe and BLo. The page buffer PB is divided into a single latch structure or a dual latch structure according to the number of latches. Here, a single latch structure will be described as an example. This page buffer PB is not limited to the configuration shown in the figure.

As shown in FIG. 4, the page buffer PB temporarily stores a bit line selection unit 100 for selecting any one of a pair of bit lines BLe and BLo, and memory cell data detected from the selected bit lines. The latch part LT is provided. In addition, a plurality of transistors P and N5 to N9 are further provided for data transmission when the device is driven (having write, erase and read operations).

In addition, the nonvolatile memory device according to the embodiment of the present invention includes a read voltage generator 110. The read voltage generator 110 may receive a high voltage VPP of about 5V to 10V higher than the power supply voltage VDD, and drop the high voltage VPP to a predetermined voltage in response to the number of cycles of erase and write operations. To be supplied to the drain of the precharge transistor (P).

5 is a configuration diagram illustrating the read voltage generator 110.

Referring to FIG. 5, the read voltage generator 110 divides the high voltage VPP and outputs a plurality of read voltages Vread1 to Vread3 having different voltage magnitudes, and erases and writes them. Selecting one of the read voltages Vread1 to Vread3 in response to the read control signals Cread1 to Cread3 that are enabled (logic high) according to the number of cycles of operation to output to the drain of the precharge transistor P. The unit 112 is provided. In addition, a fuse block 113 connected between the voltage divider 111 and the selector 112 is further provided.

The voltage divider 111 includes a plurality of resistors R1 to R4 connected in series between the high voltage terminal and the ground voltage terminal. At this time, the size of the resistor (R1 ~ R4) may be appropriately selected according to the size of the read voltage to be distributed. In addition, the sizes of the resistors R1 to R4 may be the same or different from each other. The selector 112 includes a plurality of switching elements SW1 to SW3 controlled by the read control signals Cread1 to Cread3. In this case, the switching elements SW1 to SW3 may be formed of a plurality of transistors. The fuse block 113 includes a plurality of fuses F1 to F3.

6 is a diagram illustrating another read voltage generator 110.

Referring to FIG. 6, the read voltage generator 110 voltage drops the high voltage VPP to output a plurality of read voltages Vread1 to Vread3 having different voltage levels, and erases them. And one of the read voltages Vread1 to Vread3 in response to the read control signals Cread1 to Cread3 that are enabled (logically high) according to the number of cycles of the write operation, and outputs to the drain of the precharge transistor P. It has a selector 122 to. In addition, a fuse block 123 connected between the voltage drop unit 121 and the selection unit 122 is further provided.

The voltage drop unit 121 includes a plurality of VDC (Voltage Down Converters, VDC1 to VDC3) for receiving a high voltage VPP and dropping the voltage to a predetermined magnitude. The selector 122 may include a plurality of switching elements SW1 to SW3, that is, transistors, controlled by the read control signals Cread1 to Cread3. The fuse block 123 includes a plurality of fuses F1 to F3.

5 and 6, each of the fuse blocks 113 and 123 is for setting a voltage to be used during an actual read operation among a plurality of read voltages generated from the voltage divider 111 or the voltage drop 121. In other words, the size and number of read voltages to be used in the read operation for each selected bit line are not uniformly the same, but different. For example, when the read voltage generating unit 110 generates a read voltage of 3 V, 3.5 V, 4 V, 4.5 V, and 5 V, the read voltage of the fuse configured in the fuse blocks 113 and 123 during the read operation on the 10th bit line. This is to use read voltages of 3V, 4V, and 5V through cutting operation, and use read voltages of 3V, 3.5V, and 4.5V during read operation on the 20th bit line.

Hereinafter, a method of driving a nonvolatile memory device according to an embodiment of the present invention will be described. The read method included in the driving method will be described based on a string connected to the even-numbered bit line BLe among the bit lines BLe and BLo for convenience of description.

Referring to FIGS. 3 and 4, after an erase operation or a write operation, a read is performed on a memory cell of an even-numbered bit line BLe, that is, a string ST connected to a selection bit line, by using the first read voltage Vread1. Carry out the operation (S10). At this time, the erase operation and the write operation correspond to the number of cycling less than the first reference frequency. Here, the first reference number may be set differently according to SLC (Single Level Cell) and MLC (Multi Level Cell). This is because the tunnel insulating film is more deteriorated in MLC than in SLC. For example, less than 100K (where K is 1000 times) for SLC and 10K (where K is 1000 times) for MLC. In addition, the first read voltage Vread1 is a voltage corresponding to the power supply voltage VDD, which is about 3V to 4V. Substantially, considering the voltage drop due to the threshold voltage of the transistor present in the path leading to the bit line, the voltage delivered to the bit line is about 1V.

A path through which the first read voltage Vread1 is transferred to the selection bit line BLe will be described below. When the number of cycles of the erase and write operations in the read voltage generator 110 is less than the SLC reference 100K, only the read control signal Cread1 is enabled and the first switch SW1 is turned on. Accordingly, the first read voltage Vread1 is supplied to the drain of the precharge transistor P through the first switching unit SW1. At this time, as the precharge transistor P is turned on by the precharge signal PRECHARGE, the first read voltage Vread1 is transferred to the node SO. The first read voltage Vread1 transferred as described above is transferred to the select bit line BLe through the even-numbered bit line select transistor N3 of the bit line select unit 100.

Subsequently, at least one of an erase operation and a write operation is performed on the memory cell in a general manner (S11). At this time, the range of the erase and write operations is not limited. For example, the erase operation may be performed for only one block or for all blocks. In addition, the write operation may be performed only for one page (a plurality of items are configured in one block) or for all pages in one block.

Next, the number of cycles of the erase and write operations performed in step S11 is counted and detected (S12). In this case, the counting method may count the erase operation and the write operation independently once after each operation is completed, or may count once after both operations including the erase operation and the write operation are completed. In addition, in the case of the write operation, the count operation may be counted once after the write operation for all blocks is completed or counted once after the write operation for one block is completed. It may also count once after the write operation for one page is completed. In addition, in the case of the erasing operation, counting may be performed once after the erasing operation for all blocks is completed, or counting once after the erasing operation for one block is completed.

Subsequently, it is compared whether the cycle number Cpre of the erase and write operations detected in step S12 has reached the first reference number Cref1 (100K) (S13). That is, if the number of cyclings Cpre of the erase and write operations is equal to or greater than the first reference number of times Cref1 (Cpre? Cref1), the read voltage is boosted during the read operation (S13, S14). For example, a read operation is performed using the second read voltage Vread2 that is increased by about 0.5 to 1 V from the first read voltage Vread1. On the other hand, if the cycle number Cpre of the erase and write operations does not reach the first reference number Cref1 but is less than the number Cpre <Cref1, the read operation is performed using the first read voltage Vread1 as it is (S13). , S10). In this case, the second read voltage Vread2 may be less than 5V while exceeding 4V.

A path through which the second read voltage Vread2 is transferred to the selection bit line BLe will be described below. When the number of cycles of the erase and write operations in the read voltage generator 110 is greater than or equal to the SLC reference 100K, only the read control signal Cread2 is enabled and the second switching unit SW2 is turned on. Accordingly, the second read voltage Vread2 is supplied to the drain of the precharge transistor P through the second switching unit SW2. At this time, as the precharge transistor P is turned on by the precharge signal PRECHARGE, the second read voltage Vread2 is transmitted to the node SO. The second read voltage Vread2 thus transferred is transferred to the select bit line BLe through the even-numbered bit line select transistor N3 of the bit line select unit 100.

Subsequently, at least one of an erase operation and a write operation is performed on the memory cell in a general manner (S15). At this time, the range of the erase and write operations is not limited.

Subsequently, the number of cycles of the erase and write operations performed in step S15 is counted and detected (S16). At this time, the counting method is performed by the same method as that performed in step S13.

Subsequently, it is compared whether the cycling number Cpre of the erase and write operations detected in step S16 reaches the second reference number of times Cref2 150K (S17). That is, if the number of cyclings Cpre of the erase and write operations is equal to or greater than the second reference number of times Cref2 (Cpre? Cref2), the read voltage is boosted during the read operation (S17, S18). For example, a read operation is performed using the third read voltage Vread3 that is increased by about 0.5 to 1 V from the second read voltage Vread2. On the other hand, if the cycle number Cpre of the erase and write operations does not reach the second reference number Cref2 but is less than (Cref1 ≦ Cpre <Cref2), the read operation is performed using the second read voltage Vread2 ( S17, S14). In this case, the third read voltage Vread3 may be less than 6V while exceeding 5V.

A path through which the third read voltage Vread3 is transferred to the selection bit line BLe will be described below. When the number of cycles of the erase and write operations in the read voltage generator 110 is greater than or equal to the SLC reference 150K, only the read control signal Cread3 is enabled and the third switching unit SW3 is turned on. Accordingly, the third read voltage Vread3 is supplied to the drain of the precharge transistor P through the third switching unit SW3. In this case, as the precharge transistor P is turned on by the precharge signal PRECHARGE, the third read voltage Vread3 is transmitted to the node SO. The third read voltage Vread3 transferred as described above is transferred to the select bit line BLe through the even-numbered bit line select transistor N3 of the bit line select unit 100.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, in the embodiment of the present invention, a string consisting of 32 memory cells has been described as an example, but for convenience of description, the number of memory cells constituting the string is not limited. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is an equivalent circuit diagram showing a memory cell array of a typical NAND flash memory device.

2 is a diagram illustrating a threshold voltage distribution of a memory cell after a read operation according to the related art.

3 is a flowchart illustrating a method of driving a nonvolatile memory device according to an embodiment of the present invention.

4 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.

5 and 6 are configuration diagrams illustrating the read voltage generator shown in FIG. 4.

<Explanation of symbols for main parts of drawing>

WL0 ~ WL31: Word line BL0 ~ BLn: Bit line

DSL: Drain Select Line SSL: Source Select Line

DST: drain select transistor (first select transistor)

SST: source select transistor (second select transistor)

MC0 to MC31: Memory cell MCA: Memory cell array

PB: Page Buffer LT: Latch

100: bit line selector 110: read voltage generator

111: voltage divider 112, 122 selector

113, 123: fuse block 121: voltage drop

Claims (16)

A plurality of strings having a plurality of memory cells connected in series between first and second selection transistors, a plurality of word lines for selecting the memory cells, and a plurality of bit lines connected with the strings, respectively; In the method of reading a volatile memory device, In reading operation, And a read voltage supplied to a selected bit line among the bit lines is boosted and supplied according to the number of cycles of erase and write operations. A plurality of strings having a plurality of memory cells connected in series between first and second selection transistors, a plurality of word lines for selecting the memory cells, and a plurality of bit lines connected with the strings, respectively; In the method of driving a volatile memory device, Performing a read operation by applying a first read voltage to a selected bit line among the bit lines; Performing an erase and write operation on a selected memory cell among the memory cells; Detecting a cycling number of the erase and write operations; And Performing a read operation by supplying a second read voltage higher than the first read voltage to a selected bit line when the number of cycling of the erase and write operations is equal to or greater than a set first reference number of times; A method of driving a nonvolatile memory device having a. The method of claim 2, After performing the read operation by supplying the second read voltage to the select bit line, Performing an erase and write operation on a selected memory cell among the memory cells; Detecting a cycling number of the erase and write operations; And Performing a read operation by supplying a third read voltage higher than the second read voltage to a selection bit line if the number of cycling of the erase and write operations is greater than or equal to a second reference number greater than the first reference number of times; A method of driving a nonvolatile memory device further comprising. The method of claim 3, wherein Wherein the first read voltage is 3V to 4V, the second read voltage is more than 4V and less than 5V, and the third read voltage is more than 5V and less than 6V. The method of claim 3, wherein Wherein the first reference number is 100K and the second reference number is 150K. Where K is 1000 times. The method of claim 3, wherein Wherein the first reference number is 10K and the second reference number is 15K. Where K is 1000 times. A plurality of strings having a plurality of memory cells connected in series between the first and second selection transistors; A plurality of word lines to select the memory cells; A plurality of bit lines respectively connected to the strings; And A read voltage generation unit configured to supply a read voltage to a selected bit line among the bit lines, The read voltage generation unit is configured to supply the read voltage by boosting the read voltage according to the number of cycles of erase and write operations of a selected memory cell among the memory cells. The method of claim 7, wherein The read voltage generator, A voltage divider for distributing a high voltage and outputting a plurality of read voltages having different voltage magnitudes; And A selector which selects one of the plurality of read voltages and transfers the selected one to the selected bit line Nonvolatile memory device having a. The method of claim 8, And the voltage divider includes a plurality of resistors connected in series between a power supply voltage terminal and a ground voltage terminal. The method of claim 9, And the selector includes a plurality of switching units configured to select one of the read voltages applied to each of the plurality of resistors and transfer the selected voltage to the selected bit line. The method of claim 10, And the switching unit comprises a transistor. The method of claim 8, And a plurality of fuses connected between the voltage divider and the selector. The method of claim 7, wherein The read voltage generator, A voltage drop unit configured to distribute a high voltage to generate a plurality of read voltages having different voltage magnitudes; And A selector which selects one of the plurality of read voltages and transfers the selected one to the selected bit line Nonvolatile memory device having a. The method of claim 13, And the selector comprises a plurality of switching units configured to select one of the plurality of read voltages and transfer the selected one to the selected bit line. The method of claim 14, And the switching unit comprises a transistor. The method of claim 13, And a plurality of fuse portions connected between the voltage drop portion and the selection portion.

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