KR20100008112A - Flash memory device and manufacturing method the same - Google Patents

Abstract

PURPOSE: A flash memory device and manufacturing method the same are provided to manufacture the flash memory device having the reliability. CONSTITUTION: The second polysilicon pattern(216) is formed on the third oxide film. The mask pattern on the semiconductor substrate(100) is removed. Using the partial removal of the third oxide membrane, the third oxide film pattern(131) is formed in the lower part of the second polysilicon pattern. The second oxide film pattern, the primary nitride film pattern, and a part of the first oxide film pattern is removed. Therefore, the ONO (Oxide-Nitride-Oxide) film is formed in the lower part of the sidewall oxide film(107) and the first polysilicon pattern(116).

Description

Flash memory device and manufacturing method {Flash memory device and Manufacturing method the same}

Embodiments relate to a flash memory device and a method of manufacturing the same.

The flash memory device is a nonvolatile storage medium in which stored data is not damaged even when the power is turned off. However, the flash memory device has a relatively high processing speed for writing, reading, and deleting data.

Accordingly, the flash memory device is widely used for data storage of a PC bios, a set-top box, a printer, and a network server. Recently, the flash memory device is also widely used in digital cameras and mobile phones.

In flash memory devices, semiconductor devices using a silicon-oxide-nitride-oxide-silicon (SONOS) structure are used.

A SONOS memory device is a charge trapping device that uses a mechanism in which charge tunnels a thin oxide film on silicon by a gate voltage, and uses a mechanism of injecting or relaxing from a trap in a silicon nitride film instead of a floating gate using a conventional polycrystalline silicon. .

Among them, in a SONOS memory device having an oxide-nitride-oxide (ONO) film arranged in an 'L' shape, when electrons are injected by a method of hot electron injection, the bottom of the nitride film In addition, electrons are also present on the nitride film, and thus, the electrons on the upper side may not be removed during the erase operation of the electrons.

The flash memory device and the method of manufacturing the same according to the embodiment provide a reliable flash memory device and a method of manufacturing the same by forming an ONO film on a portion of the lower gate.

A method of manufacturing a flash memory device according to an embodiment may include forming a mask pattern including a first oxide pattern, a first nitride pattern, a second oxide pattern, and a first polysilicon pattern on a sidewall of a semiconductor substrate; Forming a third oxide film in the exposed region of the semiconductor substrate and forming a sidewall oxide film in the exposed region of the first polysilicon pattern; Forming a second polysilicon pattern on the third oxide layer so as to contact the sidewall oxide sidewalls; Removing the mask pattern on the semiconductor substrate on which the second polysilicon pattern is formed, and removing a portion of the third oxide layer to form a third oxide layer pattern under the second polysilicon pattern; And removing portions of the second oxide pattern, the first nitride layer pattern, and the first oxide layer pattern to form a fourth oxide layer pattern, a third nitride layer pattern, and a fifth oxide layer pattern under the first polysilicon pattern and the sidewall oxide layer. Forming the formed ONO film.

In an embodiment, a flash memory device may include a first oxide pattern formed on a semiconductor substrate; A first nitride film pattern, a second oxide film pattern, and a first polysilicon pattern formed on a first region of the first oxide film pattern; A second polysilicon pattern formed on a second region of the second oxide pattern; And a sidewall oxide film formed on the second oxide film pattern and formed between the first polysilicon pattern and the second polysilicon pattern.

In the flash memory device and the method of manufacturing the same, an electron trap is generated only in the ONO layer formed at a part of the lower gate, so that an erase operation can be easily performed to manufacture a reliable flash memory device.

In addition, by forming a plurality of contacts connected to both the first polysilicon pattern and the second polysilicon pattern, the same bias may be applied to the first polysilicon pattern and the second polysilicon pattern.

Hereinafter, embodiments will be described with reference to the accompanying drawings.

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure may be "on" or "under" the substrate, each layer (film), region, pad or pattern. "On" and "under" include both "directly" or "indirectly" formed through another layer, as described in do. In addition, the criteria for the above / above or below of each layer will be described with reference to the drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 to 19 are process plan views and stages of a flash memory device according to an embodiment.

As shown in FIG. 1, the first oxide film 101, the first nitride film 102, the second oxide film 103, and the second nitride film 104 are sequentially formed on the semiconductor substrate 100.

In this case, the first oxide film 101, the first nitride film 102, and the second oxide film 103 may be formed of a structure of Oxide-Nitride-Oxide (ONO) in a silicon-oxide-nitride-oxide-silicon (SONOS) structure. To form.

The first oxide film 101 and the second oxide film 103 may be formed of a silicon oxide film (SiO ₂ ), and the first nitride film 102 and the second nitride film 104 may be formed of a silicon nitride film (SiN). Can be.

As shown in FIG. 2, a mask layer 105 is formed on the second nitride film 104.

The mask layer 105 may be formed of a tetraethly orthosilicate (TEOS) film having a thickness of 1000 to 2500 kPa by performing a low pressure chemical vapor deposition (LPCVD) process.

In the present embodiment, the mask layer 105 is formed of a TEOS film, but the present invention is not limited thereto. The mask layer 105 may be a material that can be used as a mask when an etching process is performed on a polysilicon layer. All are applicable.

3, a first photoresist pattern 1 is formed on the mask layer 105, and a first etching process is performed using the first photoresist pattern 1 as a mask. The pattern 115 is formed.

As shown in FIG. 4, a second etching process is performed on the second nitride film 104 using the mask pattern 115 as a mask to form a second nitride film pattern 114, and then the first nitride film pattern 114 is formed. The photoresist pattern 1 is removed.

In this case, the first etching process and the second etching process may be a dry etching process, and the first photoresist pattern 1 may be removed by an ashing process.

Subsequently, as illustrated in FIG. 5, a first polysilicon layer 106 is formed on the semiconductor substrate 100 including the second nitride layer pattern 114 and the mask pattern 115.

The first polysilicon film 106 may be formed by performing an LPCVD process.

6, after the third etching process is performed on the first polysilicon layer 106 to form the first polysilicon pattern 116, the second oxide layer 103 and the second layer may be formed. A fourth etching process is performed on the first nitride film 102 to form the second oxide film pattern 113 and the first nitride film pattern 112.

The third etching process may be an anisotropic dry etching process, and the first polysilicon pattern 116 may be formed on sidewalls of the second nitride film pattern 114 and the mask pattern 115 by the third etching process. Can be.

The first polysilicon pattern 116 may be formed by the anisotropic dry etching process, and thus the plurality of first polysilicon patterns 116 having the same size may be formed on the semiconductor substrate 100.

In addition, a fourth etching process of sequentially etching the second oxide layer 103 and the first nitride layer 102 using the mask pattern 115 and the first polysilicon pattern 116 as a mask may be performed. A second oxide film pattern 113 and a first nitride film pattern 112 are formed under the 115 and the first polysilicon pattern 116.

In this case, the first oxide layer 101 is exposed through the fourth etching process for forming the second oxide layer pattern 113 and the first nitride layer pattern 112.

7, a fifth etching process is performed on the first oxide film 101 to form a first oxide pattern 111 so that the semiconductor substrate 100 is exposed.

As the first oxide film 101 is damaged by the fourth etching process, problems with the quality and thickness uniformity of the first oxide film 101 may occur, resulting in data retention and durability. Since it affects the reliability of the device having an endurance characteristic, the first oxide film 101 exposed by the fifth etching process is removed.

Subsequently, as shown in FIG. 8, a first heat treatment process is performed on the semiconductor substrate 100 to form a third oxide film 121 on the semiconductor substrate 100.

In this case, the sidewall oxide layer 107 is simultaneously formed in the exposed region of the first polysilicon pattern 116 by the first heat treatment process.

The sidewall oxide layer 107 is positioned on the second oxide layer pattern 113 and is positioned on the side and top surfaces of the first polysilicon pattern 116.

The third oxide film 121 is formed again in a region where the first oxide film 101 is removed by the fifth etching process by the first heat treatment process.

Next, as shown in FIG. 9, a second polysilicon film 206 is formed on the semiconductor substrate 100.

The second polysilicon film 206 may be formed by an LPCVD process.

As shown in FIG. 10, a sixth etching process, which is an anisotropic dry etching process, is performed on the second polysilicon layer 206 to form a second polysilicon pattern 216 on the sidewall of the sidewall oxide layer 107. ).

The second polysilicon pattern 216 may be formed on the third oxide layer 121 and partially disposed on the sidewall oxide layer 107.

The second polysilicon pattern 216 may be formed by a sixth etching process which is the anisotropic dry etching process, and thus the plurality of second polysilicon patterns 216 having the same size may be formed on the semiconductor substrate 100. have.

In this case, the sidewall oxide layer 107 is positioned between the first polysilicon pattern 116 and the second polysilicon pattern 216.

Subsequently, as shown in FIG. 11, a seventh etching process is performed on the semiconductor substrate 100 to remove the mask pattern 115.

During the seventh etching process for removing the mask pattern 115, exposed regions of the third oxide layer 121 are simultaneously removed to form a third oxide layer pattern 131 on the semiconductor substrate 100. A portion of the semiconductor substrate 100 is exposed.

Although not shown in the drawing, in the seventh etching process for removing the mask pattern 115, after the exposed region of the third oxide layer 121 is removed, the lower portion of the third oxide layer 121 is removed. The semiconductor substrate 100 positioned may also be partially etched.

The third oxide layer pattern 131 is disposed between the second polysilicon pattern 216 and the semiconductor substrate 100.

In addition, during the seventh etching process for removing the mask pattern 115, the insulating layer inside the device isolation region (not shown) formed on the semiconductor substrate 100 may be removed at the same time.

In addition, a first ion implantation process may be performed on the semiconductor substrate 100 on which the third oxide layer pattern 131 is formed.

12 is a plan view of the semiconductor substrate 100 that proceeds to the first ion implantation process.

The first polysilicon pattern 116, the sidewall oxide layer 107, and the second polysilicon pattern 216 may be formed on the semiconductor substrate 100 including an active area 303 and an isolation region 304. Is placed.

In addition, a first region 301 in which a first impurity region is formed is disposed in an exposed region of the semiconductor substrate 100, and a region in which the second nitride layer pattern 114 is formed is a second region in which ions are not implanted ( 302 is disposed.

The device isolation region 304 disposed in the first region 301 is a first impurity region formed by the first ion implantation process after the insulating film inside the device isolation region 304 is removed by the seventh etching process. The first region 301 may be connected to each other by the first impurity region.

That is, the first region 301 may be used as a common source.

As the first impurity region is formed through the first ion implantation process, the resistance of the first region 301 to be used as a common source may be lowered.

The second region 302 is a region where a drain is formed, and then impurities are injected into the active region 303 of the second region 302 to form a drain.

FIG. 13 is a side cross-sectional view of AA ′ of FIG. 12, and FIG. 14 is a side cross-sectional view of B-B ′ of FIG. 12.

As shown in FIG. 13, the first impurity region 201 is formed in the semiconductor substrate 100 between the second polysilicon patterns 216 by the first ion implantation process.

As shown in FIG. 14, during the seventh etching process for removing the mask pattern 115, an insulating layer in the device isolation region formed in the semiconductor substrate 100 is simultaneously removed and the first ion implantation is performed. The first impurity region 201 is formed in the trench 10 of the device isolation region from which the insulating film is removed.

In this case, the first ion implantation process may be performed with arsenic or phosphorus ions that are Group 5.

15, the second photoresist pattern 2 is formed on the semiconductor substrate 100, and the second photoresist pattern 2 and the first polysilicon pattern 116 are masked. The eighth etching process may be performed to form a fourth oxide film pattern 141, a third nitride film pattern 122, and a fifth oxide film pattern 123 under the first polysilicon pattern 116.

The second photoresist pattern 2 is formed to cover the first impurity region 201, the second polysilicon pattern 216, and the sidewall oxide layer 107.

The eighth etching process is performed by using the second photoresist pattern 2 and the first polysilicon pattern 116 as a mask and exposing the first oxide layer pattern 111 and the first exposed layer on the semiconductor substrate 100. The nitride layer pattern 112 and the second oxide layer pattern 113 are etched to form the fourth oxide layer pattern 141, the third nitride layer pattern 122, and the fifth oxide layer pattern 123.

Since only the exposed region on the semiconductor substrate 100 is etched, the fourth oxide layer pattern 141, the third nitride layer pattern 122, and the fifth oxide layer pattern 123 are disposed under the second polysilicon pattern 216. This will be left.

Subsequently, a second ion implantation process is performed on the semiconductor substrate 100 using the second photoresist pattern 2 and the first polysilicon pattern 116 as a mask to form a second impurity region on the semiconductor substrate 100. 202 is formed.

In this case, the second ion implantation process may be performed with arsenic or phosphorus ions that are Group 5.

Since the second photoresist pattern 2 is formed to cover the first impurity region 201, ion implantation is not performed in the first impurity region 201 during the second ion implantation process.

After forming the second impurity region 202, the second photoresist pattern 2 may be removed by an ashing process.

Subsequently, as illustrated in FIG. 16, spacers 136 are formed on sidewalls of the first polysilicon pattern 116 and the second polysilicon pattern 216, and a third impurity region is formed by a third ion implantation process. 203 and the fourth impurity region 204 are formed.

The spacer 136 may be formed by forming an oxide layer on the semiconductor substrate 100 and then performing a ninth etching process on the oxide layer, and the ninth etching process is an anisotropic etching process.

The third impurity region 203 may be a source region, and the fourth impurity region 204 may be a drain region.

In addition, a heat treatment process may be further performed to diffuse the impurity regions.

Subsequently, as shown in FIG. 17, a salicide process is performed on the semiconductor substrate 100 to form a first silicide layer 211 on the first polysilicon pattern 116. The second silicide layer 212 may be formed on the second polysilicon pattern 216.

The first silicide layer 211 and the second silicide layer 212 may be formed by performing a salicide process using a material such as Co (cobalt) on the semiconductor substrate 100, and forming a contact. It may be formed in the area to be.

Although not illustrated, the semiconductor substrate 100 may be formed in the semiconductor substrate 100 in the region where the third impurity region 203 and the fourth impurity region 204 are formed.

An interlayer insulating film including a contact may be formed on the semiconductor substrate 100.

18 is a plan view of the semiconductor substrate 100 on which an interlayer insulating film including the contact is formed.

The first polysilicon pattern 116 and the second polysilicon pattern 216 are connected to a cell contact 260 including a first contact 261, a second contact 262, and a third contact 263. The first contact 261, the second contact 262, and the third contact 263 may be formed at different positions.

 Since the first polysilicon pattern 116 and the second polysilicon pattern 216 are separated by the sidewall oxide layer 107, the first polysilicon pattern 116 and the second polysilicon pattern 216 are separated. The cell contact 260 is formed to contact both the first polysilicon pattern 116 and the second polysilicon pattern 216 to apply the same bias to the second polysilicon pattern 116.

That is, the positions of the first contact 261, the second contact 262, and the third contact 263 are adjusted to be connected to both the first polysilicon pattern 116 and the second polysilicon pattern 216. By doing so, even if misalignment occurs when forming the cell contact 260, the same bias may be applied to the first polysilicon pattern 116 and the second polysilicon pattern 216.

In the present embodiment, three contacts are formed, but additional contacts may be further formed.

Since the drain region connected to the fourth impurity region 204 is separated by the device isolation region 304, each of the drain contacts 250 is formed.

Although not shown, only one contact may be additionally formed in the first region 301 used as a common source.

19 is a side cross-sectional view of BB ′ shown in FIG. 18.

A fourth nitride film 245 and an interlayer insulating film 240 including the fourth contact 250 are formed on the semiconductor substrate 100, and the fourth contact 250 is the fourth impurity region 204. It is formed to connect with.

The fourth nitride layer 245 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, and may protect structures such as a polysilicon pattern formed on the semiconductor substrate 100.

The memory device fabricated as described above may be programmed using electrons by FN tunneling, hot carrier injection, hot electron injection, or hot electron injection. Erase may be performed by a hot hole injection (HHI) method.

In this case, the third nitride layer pattern 122 may be a layer for trapping.

19 is a cross-sectional view of a flash memory device according to an embodiment.

As illustrated in FIG. 19, a third oxide film pattern 131 and a fourth oxide film pattern 141 are disposed on the semiconductor substrate 100 including the source region 203 and the drain region 204.

A second polysilicon pattern 216 is formed on the third oxide layer pattern 131, and a third nitride layer pattern 122, a fifth oxide layer pattern 123, and a fifth layer are formed on the fourth oxide layer pattern 141. One polysilicon pattern 116 is arranged in sequence.

In this case, a sidewall oxide layer 107 is disposed between the first polysilicon pattern 116 and the second polysilicon pattern 216 on the fifth oxide layer pattern 123, and is disposed on the sidewall oxide layer 107. The first polysilicon pattern 116 and the second polysilicon pattern 216 are separated from each other.

A spacer 136 made of an oxide film is disposed on sidewalls of the first polysilicon pattern 116 and the second polysilicon pattern 216.

The source region 203 is formed in the semiconductor substrate 100 adjacent to the second polysilicon pattern 216, and the drain region 204 is formed in the semiconductor substrate adjacent to the first polysilicon pattern 116. 100).

The source region 203 and the drain region 204 are formed by implanting arsenic or phosphorus ions of a group 5 group.

The first silicide layer 211 may be formed on the first polysilicon pattern 116, and the second silicide layer 212 may be formed on the second polysilicon pattern 216.

On the semiconductor substrate 100 including the first silicide layer 211, the second silicide layer 212, and the spacer 136, a fourth nitride layer 245 and an interlayer insulating layer including a fourth contact 250 may be formed. 240 is disposed.

The fourth contact 250 is formed to be connected to the fourth impurity region 204, and the fourth nitride layer 245 may protect structures such as a gate formed on the semiconductor substrate 100.

In the above-described flash memory device and a method of manufacturing the same, an electron trap is generated only in the ONO layer formed under a portion of the gate, so that an erase operation is easy and a reliable flash memory device can be manufactured.

In addition, by forming a plurality of contacts connected to both the first polysilicon pattern and the second polysilicon pattern, the same bias may be applied to the first polysilicon pattern and the second polysilicon pattern.

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 19 are process cross-sectional views of a flash memory device according to an embodiment.

Claims (13)

Forming a mask pattern including a first oxide layer pattern, a first nitride layer pattern, a second oxide layer pattern, and a first polysilicon pattern on a sidewall of the semiconductor substrate; Forming a third oxide film in the exposed region of the semiconductor substrate and forming a sidewall oxide film in the exposed region of the first polysilicon pattern; Forming a second polysilicon pattern on the third oxide layer so as to contact the sidewall oxide sidewalls; Removing the mask pattern on the semiconductor substrate on which the second polysilicon pattern is formed, and removing a portion of the third oxide layer to form a third oxide layer pattern under the second polysilicon pattern; And A portion of the second oxide layer pattern, the first nitride layer pattern, and the first oxide layer pattern may be removed to form a fourth oxide layer pattern, a third nitride layer pattern, and a fifth oxide layer pattern under the first polysilicon pattern and the sidewall oxide layer. A method of manufacturing a flash memory device comprising forming an ONO film. The method of claim 1, A step of forming a mask pattern including a first oxide pattern, a first nitride pattern, a second oxide pattern, and a first polysilicon pattern on a sidewall of a semiconductor substrate may include: Forming a first oxide film, a first nitride film, and a second oxide film on a semiconductor substrate, and then forming a mask pattern on the second oxide film; Forming a first polysilicon pattern on sidewalls of the mask pattern on the second oxide film; And A first etching process is performed on the first oxide layer, the first nitride layer, and the second oxide layer to expose the semiconductor substrate, and the first oxide layer pattern, the first nitride layer pattern, and the first oxide layer are disposed under the first polysilicon pattern and the mask pattern. A method of manufacturing a flash memory device comprising the step of forming an oxide film pattern. The method of claim 1, And the mask pattern is formed by stacking a second nitride film pattern and a fourth oxide film. The method of claim 1, And the third oxide film and the sidewall oxide film are formed simultaneously by performing a heat treatment process on the semiconductor substrate. The method of claim 1, The second polysilicon pattern is formed by forming a second polysilicon film on the semiconductor substrate on which the sidewall oxide film is formed, and then performing a second etching process. The method of claim 1, And the sidewall oxide layer is formed between the first polysilicon pattern and the second polysilicon pattern. The method of claim 1, Forming a spacer on sidewalls of the first polysilicon pattern and the second polysilicon pattern formed on the semiconductor substrate. The method of claim 1, The semiconductor substrate includes an isolation layer made of an insulating material, When the mask pattern is removed, the exposed insulating material in the exposed device isolation layer is simultaneously removed. The method of claim 1, Forming an interlayer insulating film having a plurality of contacts formed on the semiconductor substrate on which the ONO film is formed, The flash memory device may include a plurality of contacts formed at different positions to apply the same bias to the first polysilicon pattern and the second polysilicon pattern. Method of preparation. A first oxide film pattern formed on the semiconductor substrate; A first nitride film pattern, a second oxide film pattern, and a first polysilicon pattern formed on a first region of the first oxide film pattern; A second polysilicon pattern formed on a second region of the second oxide pattern; And And a sidewall oxide film formed on the second oxide film pattern and formed between the first polysilicon pattern and the second polysilicon pattern. The method of claim 10, And a first polysilicon pattern and a second polysilicon pattern separated by the sidewall oxide layer. The method of claim 10, And a spacer formed on sidewalls of the first polysilicon pattern and the second polysilicon pattern. The method of claim 10, A source and a drain region formed in the semiconductor substrate; And the drain region is formed in the semiconductor substrate adjacent to the first polysilicon pattern, and the source region is formed in the semiconductor substrate adjacent to the second polysilicon pattern.

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