KR20100007254A - Non-volatile memory device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and method of fabricating the same are provided to improve the degree of integration. CONSTITUTION: The stack structure of the second control gate electrode(120b) and the first control gate electrode(120a) is offered with a plurality of lines. The stack structure of first control gate electrodes and stack structure of second control gate electrodes are by turns arranged. First control gate electrodes and second control gate electrodes are arranged two-dimensionally in on the plane. A plurality of interlayer dielectric layer(110) is offered between interval and the second semiconductor layer(160b) of the semiconductor layer(160a).

Description

Non-volatile memory device and method of manufacturing the same {Non-volatile memory device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a nonvolatile memory device capable of writing and erasing data using a charge storage layer, and a manufacturing method thereof.

Semiconductor products are getting smaller and require higher data throughput. Accordingly, it is necessary to increase the operation speed of the nonvolatile memory device used in such a semiconductor product and to increase the degree of integration. In this respect, a multi-layered nonvolatile memory device instead of the conventional single layer structure is advantageous for high integration.

Using a multilayer structure, memory cells may be vertically stacked on the same region as the single layer structure. However, the nonvolatile memory device having a multilayer structure may have various structures according to its stacked form. In addition, the multilayer nonvolatile memory device has a problem in that the manufacturing process increases and the cost increases as the number of stacked layers increases.

Accordingly, an object of the present invention is to provide a non-volatile memory device that is extended to a stacked structure and easily integrated.

Another object of the present invention is to provide an economical manufacturing method of the nonvolatile memory device.

A nonvolatile memory device of one embodiment of the present invention for achieving the above technical problem is provided. At least one first control gate electrode is provided, and at least one second control gate electrode is disposed opposite the at least one first control gate electrode. At least one isolation insulating layer is provided between the at least one first control gate electrode and the at least one second control gate electrode. At least one first semiconductor layer is provided between the at least one first control gate electrode and the at least one isolation insulating layer. At least one second semiconductor layer is disposed between the at least one second control gate electrode and the at least one isolation insulating layer and opposite the at least one first semiconductor layer with respect to the at least one isolation insulation layer. Is placed. At least one first charge storage layer is provided between the at least one first control gate electrode and the at least one first semiconductor layer. At least one second charge storage layer is provided between the at least one second control gate electrode and the at least one second semiconductor layer.

In one example of the nonvolatile memory device according to the present invention, the at least one first semiconductor layer includes a plurality of first semiconductor layers spaced apart along a direction in which the at least one first control gate electrode extends. The at least one second semiconductor layer may include a plurality of second semiconductor layers spaced apart along the extension direction of the at least one second control gate electrode.

In another example of the nonvolatile memory device according to the present invention, the at least one isolation insulating layer may include a plurality of isolation insulation layers between the plurality of first semiconductor layers and the plurality of second semiconductor layers. Can be.

In another example of the nonvolatile memory device according to the present invention, the at least one first control gate electrode includes a plurality of first control gate electrodes stacked on each other, and the at least one second control gate electrode is It may include a plurality of second control gate electrodes stacked on each other. Further, the at least one first semiconductor layer and / or the at least one first charge storage layer extend across the plurality of first control gate electrodes, and the at least one second semiconductor layer and / or the at least One second charge storage layer may extend across the plurality of second control gate electrodes.

A method for manufacturing a nonvolatile memory device of one embodiment of the present invention for achieving the above another technical problem is provided. At least one first control gate electrode and at least one second control gate electrode are disposed to face each other. At least one first charge storage layer is formed on sidewalls of the at least one first control gate electrode. At least one second charge storage layer is formed on a sidewall of the at least one second control gate electrode to face the at least one first charge storage layer. At least one first semiconductor layer is formed on the at least one first charge storage layer. At least one second semiconductor layer is formed on the at least one second charge storage layer so as to face the at least one first semiconductor layer. At least one isolation insulating layer is formed between the at least one first semiconductor layer and the at least one second semiconductor layer.

According to the nonvolatile memory device according to the present invention, the memory cells in the NAND string can be densely arranged and thus the degree of integration thereof can be increased. In addition, the memory cells may be arranged in a matrix array and / or a stacked structure, whereby the degree of integration of the nonvolatile memory device may be higher.

Further, according to the nonvolatile memory device according to the present invention, since word lines are not shared between adjacent NAND strings, stress due to repetitive operation can be reduced. Therefore, the operation reliability of the nonvolatile memory device can be increased.

In addition, according to the method of manufacturing a nonvolatile memory device according to the present invention, memory cells having a three-dimensional structure can be manufactured at the same time using a lamination process and a patterning process. Therefore, the manufacturing method of the nonvolatile memory device according to the present invention is more economical than the conventional method of separately forming the memory cells of each layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the components may be exaggerated in size for convenience of description.

Technical terms in the embodiments of the present invention can be understood according to what is known to those skilled in the art unless otherwise defined. For example, at least one means one or more. Thus, at least one may have one or more meanings.

1 is a perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II 'of the nonvolatile memory device of FIG. 1.

1 and 2, at least one first control gate electrode 120a and at least one second control gate electrode 120b disposed on the same plane are provided. The first control gate electrode 120a and the second control gate electrode 120b may be disposed to face each other on the same plane. For example, the first control gate electrode 120a and the second control gate electrode 120b may be spaced apart in parallel to each other, and thus the sidewalls may face each other.

In addition, the plurality of first control gate electrodes 120a may be stacked on each other, and the plurality of second control gate electrodes 120b may be stacked on each other. The first control gate electrodes 120a and the second control gate electrodes 120b may be spaced apart from each other. The number of the first control gate electrodes 120a and the second control gate electrodes 120b may be appropriately selected according to the capacity of the nonvolatile memory device, and thus does not limit the scope of this embodiment.

At least one isolation insulating layer 170 may be provided between the first control gate electrodes 120a and the second control gate electrodes 120b. The isolation insulating layer 170 may be disposed near the center of the sidewalls facing the first control gate electrodes 120a and the second control gate electrodes 120b. For example, the isolation insulating layer 170 may extend across the first control gate electrodes 120a and / or across the second control gate electrodes 120b.

At least one first semiconductor layer 160a may be provided between the first control gate electrodes 120a and the isolation insulating layer 170. For example, the first semiconductor layer 160a may be disposed on one sidewalls of the isolation insulating layer 170 and may extend across the first control gate electrodes 120a. For example, the first semiconductor layer 160a may be disposed to be orthogonal to the first control gate electrodes 120a.

At least one second semiconductor layer 160b may be provided between the second control gate electrodes 120b and the isolation insulating layer 170. For example, the second semiconductor layer 160b may be disposed on the opposite side of the first semiconductor layer 160a with respect to the isolation insulating layer 170, and may extend across the second control gate electrodes 120b. . For example, the second semiconductor layer 160b may be disposed to be orthogonal to the second control gate electrodes 120b.

At least one first charge storage layer 140a may be provided between the first semiconductor layer 160a and the first control gate electrodes 120a. For example, the first charge storage layer 140a may extend along the stretching direction of the first semiconductor layer 160a and / or may cross the first control gate electrodes 120a. As another example, a plurality of first charge storage layers (not shown) may be provided between the first control gate electrodes 120a and the first semiconductor layer 160a, respectively.

At least one second charge storage layer 140b may be provided between the second semiconductor layer 160b and the second control gate electrodes 120b. For example, the second charge storage layer 140b may extend along the stretching direction of the second semiconductor layer 160b and / or may cross the second control gate electrodes 120b. As another example, a plurality of second charge storage layers (not shown) may be provided between the second control gate electrodes 120b and the second semiconductor layer 160b, respectively.

The first charge storage layer 140a and the second charge storage layer 140b may be used as charge storage media for data programs. For example, the first charge storage layer 140a and the second charge storage layer 140b may operate as a floating gate type or a charge trap type. For example, the floating gate type may include a conductor such as a polysilicon layer, and the charge trap type may include a silicon nitride layer, quantum dots, or nanocrystals. Quantum dots or nanocrystals can be composed of conductors dispersed in an insulator, such as fine particles of a metal or a semiconductor. The charge trap type allows for local storage of charge, which can be used for multi-bit operation.

At least one first tunneling insulating layer 150a may be provided between the first charge storage layer 140a and the first semiconductor layer 160a. For example, the first tunneling insulating layer 150a may extend along the extending direction of the first semiconductor layer 160a and / or may cross the first control gate electrodes 120a. As another example, a plurality of first tunneling insulating layers (not shown) may be provided between the first semiconductor layer 160a and the first charge storage layer 140a, respectively.

At least one second tunneling insulating layer 150b may be provided between the second charge storage layer 140b and the first semiconductor layer 160b. For example, the second tunneling insulating layer 150b may extend along the extending direction of the second semiconductor layer 160b and / or may cross the second control gate electrodes 120b. As another example, a plurality of second tunneling insulating layers (not shown) may be provided between the second semiconductor layer 160b and the second charge storage layer 140b, respectively.

At least one first blocking insulating layer 130a may be provided between the first charge storage layer 140a and the first control gate electrodes 120a. For example, the first blocking insulating layer 130a may extend along the stretching direction of the first semiconductor layer 160a and / or may cross the first control gate electrodes 120a. As another example, a plurality of first blocking insulating layers (not shown) may be provided between the first charge storage layer 140a and the first control gate electrodes 120a, respectively.

At least one second blocking insulating layer 130b may be provided between the second charge storage layer 140b and the second control gate electrodes 120b. For example, the second blocking insulating layer 130b may extend along the extending direction of the second semiconductor layer 160b and / or may cross the second control gate electrodes 120b. As another example, a plurality of second blocking insulating layers (not shown) may be provided between the second charge storage layer 140b and the second control gate electrodes 120b, respectively.

 3 is an equivalent circuit diagram of a nonvolatile memory device according to an embodiment of the present invention.

1 to 3, the stacked structure of the first control gate electrodes 120a and the first semiconductor layer 160a may constitute the first memory cells MC1. The stacked structure of the second control gate electrodes 120b and the second semiconductor layer 160b may constitute the second memory cells MC2. The first control gate electrodes 120a may function as first word lines WL1, and the second control gate electrodes 120b may function as second word lines WL2. The first string S1 may include a NAND-type arrangement of the first memory cells MC1, and the second string S2 may include a NAND-type arrangement of the second memory cells MC2.

According to the nonvolatile memory device described above, height adjustment of the first control gate electrodes 120a and / or the second control gate electrodes 120b is free, and thus, the first memory cells MC1 and the second memory cell are freely adjusted. The fields MC2 may be densely arranged. Therefore, the lengths of the first string S1 and the second string S2 can be reduced, thereby increasing the degree of integration of the nonvolatile memory device.

In addition, since the first word lines WL1 and the second word lines WL2 are not shared, stress due to a repetitive operation between the first memory cells MC1 and the second memory cells MC2 may be reduced. Can be reduced. Therefore, the operation reliability of the nonvolatile memory device can be improved.

4 is a perspective view illustrating a nonvolatile memory device according to another exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line VV ′ of the nonvolatile memory device of FIG. 4. The nonvolatile memory device according to the present embodiment uses the nonvolatile memory device of FIGS. 1 to 3, and thus a redundant description thereof is omitted.

4 and 5, a stacked structure of the first control gate electrodes 120a and the second control gate electrodes 120b may be provided as a plurality of lines. The stack structure of the first control gate electrodes 120a and the stack structure of the second control gate electrodes 120b may be alternately disposed. This arrangement may correspond to the arrangement of FIG. 1 arranged in a matrix form. Accordingly, the first control gate electrodes 120a and the second control gate electrodes 120b may be two-dimensionally planarly stacked and further stacked three-dimensionally. The plurality of interlayer insulating layers 110 may be provided between the first semiconductor layers 120a and between the second semiconductor layers 120b.

 As described with reference to FIGS. 1 through 3, the first memory cells MC1 and the second memory cells are disposed between the adjacent two of the first control gate electrodes 120a and the second control gate electrodes 120b. MC2 may be disposed. Therefore, the first memory cells MC1 and the second memory cells MC2 may be arranged in the form of a three-dimensional matrix.

Accordingly, the plurality of first semiconductor layers 160a may be spaced apart from each other along the extending direction of the first control gate electrodes 120a. The plurality of second semiconductor layers 160a may be spaced apart along the extending direction of the second control gate electrodes 120b. The plurality of isolation insulating layers 170 may include first control gate electrodes 120a and / or second control gate electrodes 120b between the first semiconductor layers 160a and the second semiconductor layers 160b. It may be provided to stretch across). Accordingly, the first semiconductor layers 160a and the second semiconductor layers 160b may be disposed opposite to each other based on the isolation insulating layers 170.

The first tunneling insulating layers 150a, the first charge storage layers 140a, and / or the first blocking insulating layers 130a may extend across the first semiconductor layers 160a, and may further be stacked. It may extend across the first control gate electrodes 120a. The second tunneling insulating layers 150b, the second charge storage layers 140b, and / or the second blocking insulating layers 130b extend across the second semiconductor layers 160b and are further stacked. It may extend across the two control gate electrodes 120b.

Accordingly, the first memory cells MC1 of FIG. 3 and the second memory cells MC2 of FIG. 3 may be arranged in a three-dimensional matrix. Thus, the nonvolatile memory device according to this embodiment may have a high degree of integration and may be suitable for high capacity electronic products.

6 to 10 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 6, the interlayer insulating layers 110 and the conductive layers 120 may be alternately stacked. For example, the conductive layers 120 may include any one or a stacked structure of metal, metal silicide, and doped polysilicon.

Referring to FIG. 7, the plurality of trenches 115 may be formed by patterning the interlayer insulating layers 110 and the conductive layers 120. For example, trenches 115 may be formed using photolithography and etching techniques. Accordingly, the conductive layers 120 may be divided into first control gate electrodes 120a and second control gate electrodes 120b disposed opposite to each other based on the trenches 115.

Accordingly, the first control gate electrodes 120a and the second control gate electrodes 120b may be arranged in an array structure on the same plane and stacked in three dimensions. In addition, the first control gate electrodes 120a and the second control gate electrodes 120b may be simultaneously formed.

Referring to FIG. 8, the first blocking insulating layer 130a, the first charge storage layer 140a, and the first tunneling insulation are formed on the sidewalls of the first control gate electrodes 120a stacked inside the trenches 115. A stacked structure of the layer 150a can be formed. In addition, the second blocking insulating layer 130b, the second charge storage layer 140b, and the second tunneling insulating layer 150b are stacked on the sidewalls of the second control gate electrodes 120b inside the trenches 115. The structure can be formed.

For example, the first blocking insulating layers 130a and the second blocking insulating layers 130b may be simultaneously formed to face each other. The first charge storage layers 140a and the second charge storage layers 140b may be simultaneously formed to face each other. The first tunneling insulation layers 130a and the second tunneling insulation layers 130b may be simultaneously formed to face each other.

Referring to FIG. 9, first semiconductor layers may be formed on a stacked structure of a first blocking insulating layer 130a, a first charge storage layer 140a, and a first tunneling insulating layer 150a in the trenches 115. 160a may be formed. In addition, second semiconductor layers 160b may be formed on the stacked structure of the second blocking insulating layer 130b, the second charge storage layer 140b, and the second tunneling insulating layer 150b in the trenches 115. can do. In addition, the isolation insulating layers 170 may be formed to fill the trenches 115 between the first semiconductor layers 160a and the second semiconductor layers 160b.

The first semiconductor layers 160a and the second semiconductor layers 160b may be grown from separate seed layers (not shown) into epitaxial layers. As another example, the first semiconductor layers 160a and the second semiconductor layers 160b may be formed by chemical vapor deposition (CVD) amorphous layers, and then crystallized into a single crystal layer through heat treatment such as laser annealing. As another example, the first semiconductor layers 160a and the second semiconductor layers 160b may be formed of polycrystalline layers using chemical vapor deposition (CVD).

Referring to FIG. 10, the first semiconductor layers 160a, the isolation insulating layers 170, and the second semiconductor layers 160b may be patterned. Such patterning may use photolithography and etching techniques. Accordingly, the first semiconductor layers 160a and the second semiconductor layers 160b may be arranged in a matrix form.

According to the above-described manufacturing method, a nonvolatile memory device having a three-dimensional structure can be manufactured substantially simultaneously using a lamination process and a patterning process. Therefore, the manufacturing method according to this embodiment is more economical than the conventional method of forming the memory cells of each layer separately.

11 is a schematic diagram showing a card 500 according to an embodiment of the present invention.

Referring to FIG. 11, the controller 510 and the memory 520 may exchange electrical signals. For example, according to a command of the controller 510, the memory 520 and the controller 510 may exchange data. Accordingly, the card 500 may store data in the memory 520 or output data from the memory 520 to the outside. The memory 520 may have a structure with any one of the nonvolatile memory devices described with reference to FIGS. 1 to 5.

The card 500 may be used as a data storage medium of various portable devices. For example, the card 500 may include a memory card such as a multi media card (MMC) or a secure digital card (SD) card.

13 is a block diagram illustrating an electronic system 600 according to an embodiment of the present invention.

Referring to FIG. 13, the processor 610, the input / output device 630, and the memory 620 may perform data communication with each other using a bus 640. The processor 610 may execute a program and control the system 600. The input / output device 630 may be used to input or output data of the system 600. System 600 may be connected to an external device, such as a personal computer or a network, using input / output device 630 to exchange data with the external device.

The memory 620 may store code and data for the operation of the processor 610. For example, the memory 620 may have the same structure as any of the nonvolatile memory devices described with reference to FIGS. 1 to 5.

For example, such a system 600 may comprise various electronic control devices that require memory 620, such as mobile phones, MP3 players, navigation, solid state disks. SSD) or household appliances.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. Therefore, the present invention is not limited to the above embodiments, and various modifications and changes are possible in the technical spirit of the present invention by combining the above embodiments by those skilled in the art. It is obvious.

1 is a perspective view showing a nonvolatile memory device according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II 'of the nonvolatile memory device of FIG. 1; FIG.

3 is an equivalent circuit diagram of a nonvolatile memory device according to one embodiment of the present invention;

4 is a perspective view showing a nonvolatile memory device according to another embodiment of the present invention;

FIG. 5 is a cross-sectional view taken along line VV ′ of the nonvolatile memory device of FIG. 4; FIG.

6 to 10 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention;

11 is a schematic diagram showing a memory card according to an embodiment of the present invention; And

12 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Claims (19)

At least one first control gate electrode; At least one second control gate electrode disposed opposite the at least one first control gate electrode; At least one isolation insulating layer between the at least one first control gate electrode and the at least one second control gate electrode; At least one first semiconductor layer between the at least one first control gate electrode and the at least one isolation insulating layer; At least one second semiconductor disposed between the at least one second control gate electrode and the at least one isolation insulating layer, opposite the at least one first semiconductor layer with respect to the at least one isolation insulating layer layer; At least one first charge storage layer between the at least one first control gate electrode and the at least one first semiconductor layer; And And at least one second charge storage layer between the at least one second control gate electrode and the at least one second semiconductor layer. The semiconductor device of claim 1, further comprising: at least one first tunneling insulating layer between the at least one first charge storage layer and the at least one first semiconductor layer; And And at least one second tunneling insulating layer between the at least one second charge storage layer and the at least one second semiconductor layer. The semiconductor device of claim 1, further comprising: at least one first blocking insulating layer between the at least one first charge storage layer and the at least one first control gate electrode; And And at least one second blocking insulating layer between the at least one second charge storage layer and the at least one second control gate electrode. The semiconductor device of claim 1, wherein the at least one first semiconductor layer comprises a plurality of first semiconductor layers spaced apart along a direction in which the at least one first control gate electrode extends. And the at least one second semiconductor layer includes a plurality of second semiconductor layers spaced apart along the extending direction of the at least one second control gate electrode. The nonvolatile memory device of claim 4, wherein the at least one isolation insulating layer comprises a plurality of isolation insulating layers between the plurality of first semiconductor layers and the plurality of second semiconductor layers. The method of claim 1, wherein the at least one first control gate electrode comprises a plurality of first control gate electrodes stacked on each other, The at least one second control gate electrode includes a plurality of second control gate electrodes stacked on each other. 7. The nonvolatile memory device of claim 6, further comprising a plurality of interlayer insulating layers between the plurality of first control gate electrodes and between the plurality of second control gate electrodes. The semiconductor device of claim 6, wherein the at least one first semiconductor layer extends across the plurality of first control gate electrodes, And the at least one second semiconductor layer extends across the plurality of second control gate electrodes. The method of claim 6, wherein the at least one first charge storage layer extends across the plurality of first control gate electrodes, And the at least one second charge storage layer extends across the plurality of second control gate electrodes. The nonvolatile memory device of claim 6, wherein the at least one isolation insulating layer extends across the plurality of first control gate electrodes or the plurality of second control gate electrodes. The semiconductor device of claim 6, wherein the at least one first semiconductor layer comprises a plurality of first semiconductor layers spaced apart along a direction in which the plurality of first control gate electrodes extend. And the at least one second semiconductor layer comprises a plurality of second semiconductor layers spaced apart along the extending direction of the plurality of second control gate electrodes. The semiconductor device of claim 11, wherein the at least one first charge storage layer extends across the plurality of first semiconductor layers, And the at least one second charge storage layer extends across the plurality of second charge storage layers. Forming at least one first control gate electrode and at least one second control gate electrode disposed opposite each other; Forming at least one first charge storage layer on sidewalls of the at least one first control gate electrode; Forming at least one second charge storage layer on the sidewall of the at least one second control gate electrode to face the at least one first charge storage layer; Forming at least one first semiconductor layer on the at least one first charge storage layer; Forming at least one second semiconductor layer on the at least one second charge storage layer to face the at least one first semiconductor layer; And Forming at least one isolation insulating layer between the at least one first semiconductor layer and the at least one second semiconductor layer. The method of claim 13, wherein the at least one first control gate electrode and the at least one second control gate electrode are simultaneously formed, And the at least one first charge storage layer and the at least one second charge storage layer are formed simultaneously. The method of claim 13, wherein forming the at least one first control gate electrode comprises stacking a plurality of first control gate electrodes, The forming of the at least one second control gate electrode may include stacking a plurality of second control gate electrodes disposed to face the plurality of first control gate electrodes. Manufacturing method. The method of claim 15, wherein the stacking of the plurality of first control gate electrodes and the plurality of second control gate electrodes comprises: Stacking a plurality of conductive layers; And Etching the plurality of conductive layers to form at least one trench defining the first control gate electrodes and the second control gate electrodes. 17. The method of claim 16, further comprising forming a plurality of interlayer insulating layers alternately with the plurality of conductive layers before forming the at least one trench, And the at least one trench is formed by further etching the plurality of interlayer insulating layers. The method of claim 16, wherein the at least one first charge storage layer is formed on sidewalls of the first control gate electrodes inside the at least one trench, And the at least one second charge storage layer is formed on sidewalls of the second control gate electrodes in the at least one trench. The semiconductor device of claim 15, wherein the at least one first semiconductor layer is formed across the plurality of first control gate electrodes, And the at least one second semiconductor layer is formed across the plurality of second control gate electrodes.

Images