KR20100005836A - Device for converting frequency in a broadband wireless communication system - Google Patents

Abstract

PURPOSE: A broadband radio frequency signal down conversion device in a broadband wireless communications system is provided to secure low power and high linearity and convert broadband RF signal into difference signal simply. CONSTITUTION: A common source mode varistor(171) controls impedance according to differential RF(Radio Frequency) signal inputted from a differential input generator. A frequency conversion unit(173) is connected between a variable resistance unit and virtual high potential and down-converts the RF signal according to differential local signal. The load is installed between the virtual high potential and high potential. The current signal is changed into voltage.

Description

Down conversion device of broadband wireless communication system {DEVICE FOR CONVERTING FREQUENCY IN A BROADBAND WIRELESS COMMUNICATION SYSTEM}

The present invention relates to a broadband wireless communication system, and more particularly, to a down conversion apparatus of a broadband wireless communication system for directly converting a wideband RF signal received through an antenna into a baseband (baseband or low IF) signal. .

In a wireless communication system using radio waves in general, the frequency converter receives an RF signal of very small power input through an antenna and a quadrature LO signal output from a local oscillator inside the system. It converts the frequency signal of the baseband corresponding to the frequency difference. This frequency conversion can be accomplished simply through a nonlinear circuit that multiplies the two signals.

The receiving device of such a general wireless communication system is shown in FIG.

Referring to FIG. 1, all circuits applied in a receiving apparatus of a wireless communication system, such as a low noise amplifier 20 (LNA), a frequency converter 30, etc., may be formed in a single-ended structure or a differential structure. Can be implemented.

The circuit of the differential structure has been applied because it has a higher immunity characteristic from common mode noises due to the parasitic inductance component of the silicon substrate and the bonding wire than the single phase structure.

In addition, in the frequency converter 30, the local signal LO of the local oscillator appears as a leakage signal at the output of the frequency converter 30, thereby deteriorating the linearity of the receiving device, thereby minimizing the leakage of the local signal. balanced frequency converter 30 is used a lot. Here, the frequency converter 30 of the double balance structure requires a differential signal form for the input signal.

However, since the signal line of the antenna and the bandpass filter 10 in the receiving device can process the unit phase RF input signal, a balun to unbalance (Bunun) converts a single phase signal into a differential signal inside or outside the silicon chip. ) Requires a circuit.

Here, the balun circuit is located mainly between the bandpass filter 10 and the low noise amplifier 20, which significantly reduces the noise characteristics of the entire receiver due to the insertion loss of the balun circuit.

2 is a circuit diagram illustrating a frequency converter according to an example of the prior art.

As shown in FIG. 2, the first transistor S1 receives a DC bias voltage to the gate terminal to provide a DC bias to the circuit and serves as a common mode rejection. The common mode rejection refers to the degree to which the signal (noise) applied equally to the ground and input two wires of the differential amplifier is removed from the output.

The second and third transistors S2 and S3 are devices for converting a differential RF voltage input into a current.

The fourth to seventh transistors S4, S5, S6, and S7 switch the RF current signal to the IF current signal by switching the RF signal converted into current according to the differential voltage of the local signal LO.

Reference numerals L1 and L2 serve as a load and convert the frequency-converted IF current into a voltage.

The output is differentially drawn so that the local signal (LO) does not come out of the Low IF stage, making it suitable for the Direct Conversion Architecture.

Due to the characteristics of the broadband communication receiver configured as described above, it is necessary to receive the RF input of the frequency converter 30 as a differential input. Differential low-noise amplifiers or single to differential circuits are used to create differential RF signals, but these methods induce high power consumption. Another requirement of the broadband communication receiver is a high linearity characteristic. However, a method using a DC bias like the first transistor S1 has a disadvantage in that the linear characteristic is inferior.

That is, a circuit having a differential output at the front end of the frequency converter 30 is required, which causes a lot of power consumption, which delays the operation time of the circuit. In addition, the common source structure is not suitable for wideband matching, and the broadband wireless receiver must have high linearity, but the first transistor S1 has a differential amplifier structure with a bias noise, which causes a lot of problems in linearity. .

Since the wideband receiver receives all signals in a wide frequency band, an interference signal of 30 dB or more larger than a desired signal is simultaneously applied to the frequency mixer, so that nonlinear effects such as spurious signal generation due to intermodulation, sensitivity deterioration due to saturation, and blocking are more effective. Can occur significantly. Therefore, the development of a new frequency mixer that can have a high linearity while using a low supply voltage is required.

FIG. 3 is a circuit diagram illustrating a conventional frequency converter improved over the circuit of FIG. 2.

The first transistor S11 is a device that converts an RF signal into a current.

The second transistor S12 is a circuit for biasing, so that a DC current having the same magnitude as that of the first transistor S11 flows to the fifth and sixth transistors S15 and S16.

The third to sixth transistors S13, S14, S15, and S16 switch the RF current signal to a low IF current signal by switching an RF signal converted into a current according to the differential voltage of the local signal LO. .

In addition, reference numerals L11 and L12 serve as a load (Load) by converting the frequency-converted Low IF current to a voltage.

The outputs are pulled out differentially to prevent the local signal (LO) from coming to the IF stage, making it suitable for direct conversion architectures.

The frequency converter 30 improved from the existing structure reduces power consumption by simply implementing a differential structure, and improves linearity by not using a DC bias. However, it does not have a fully differential input structure, and the linearity improvement is also limited by the lower supply voltage according to the latest process.

That is, the frequency converter 30 of FIG. 3 accepts a single RF input but does not perform a fully differential operation, which is not suitable for a direct conversion architecture. In addition, there is a problem in that all the transistors operate in a saturation region and thus an optimal linearity cannot be secured.

Accordingly, in line with the trend of miniaturizing wireless communication systems with IC circuits, direct conversion architectures are widely used. In designing a wideband wireless receiver, the direct conversion architecture requires a linear receiver structure that is robust against DC offset and flicker noise. A key technique for determining these receiver characteristics is the frequency converter, which operates with high linear low power and requires the operation of differential signals.

An object of the present invention is to simply convert a single phase wideband RF signal received in a wideband wireless communication system into a differential signal, and to achieve low power and high linearity when downconverting the converted differential signal to baseband (baseband or low IF). The present invention provides a down conversion device of a broadband wireless communication system that can be secured.

Technical means according to the present invention for achieving the above object, a differential input generator for converting a single RF signal input to the differential RF signal and outputs, and down-converts the frequency of the differential RF signal input from the differential input generator to output With a frequency converter,

The frequency converter may include a variable resistor unit having a common source mode in which impedance is adjusted according to a differential RF signal input from the differential input generator; A frequency converter connected between the variable resistor unit and the virtual high potential to operate in a saturation region according to an externally input differential local signal to down convert an RF signal; And a load installed between the virtual high potential and the high potential to convert a current signal into a voltage.

In more detail, the variable resistor unit may include: a first transistor having a source terminal connected to a low potential and receiving a differential RF signal at a gate terminal; A third transistor connected in parallel with the first transistor and receiving the same RF signal as the first transistor through a gate terminal; A fifth transistor connected in parallel with the third transistor and receiving a differential RF signal through a gate terminal; And a seventh transistor connected in parallel with the fifth transistor and receiving the same RF signal as the fifth transistor.

The frequency converter may include a second transistor connected between the first transistor and a first node having a virtual high potential and receiving a differential local signal at a gate end thereof; A fourth transistor connected between the third transistor and a second node having a virtual high potential and receiving a differential local signal through a gate terminal; A sixth transistor connected between the fifth transistor and a second node having a virtual high potential and receiving the same differential local signal as a second transistor through a gate terminal; And an eighth transistor connected between the seventh transistor and the first node having a virtual high potential and receiving the same differential local signal as the fourth transistor through a gate terminal.

The transistors connected to each other in the transistors of the variable resistance unit and the transistors of the switching unit may be connected in a cascode manner.

The differential input generator may include a first transistor having a source terminal coupled to a low potential and receiving a first bias voltage at a gate terminal; A second transistor installed between the first transistor and a first node having a virtual high potential and receiving a second bias voltage through a gate terminal; A third transistor having a source terminal coupled to a low potential and receiving a single RF signal through a gate terminal; A fourth transistor provided between the third transistor and a second node having a virtual high potential and receiving a second bias voltage through a gate terminal; A first load coupled between the first node and a high potential; And a second load connected between the second node and the high potential.

The RF signal output from the low noise amplifier is applied to the drain terminal of the first transistor, wherein the first and second transistors, and the third and fourth transistors are each connected in a cascode manner. The differential input generator is characterized in that it has a class AB type input structure.

As described above, the present invention designs a device for generating a differential RF signal with a class AB type input structure capable of wideband input matching, and designs a frequency converter with a variable resistance to the differential RF signal, thereby reducing the RF signal. When converting, there is an advantage of ensuring low power and high linearity.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit block diagram illustrating a broadband wireless communication system according to the present invention, and includes a band pass filter 110, a low noise amplifier 130, a differential input generator 150, and a frequency converter 170.

The band pass filter 110 passes a signal of a predetermined frequency band among the RF signals received through the antenna, and the low noise amplifier 130 (LNA) reduces noise in the RF signal input from the band pass filter 110 and makes a signal. Is configured to amplify.

The differential input generator 150 is configured to process a single RF signal input from the low noise amplifier 130 to generate and output differential RF signals RF + and RF-. The differential input generator 150 has a class AB type input structure.

The frequency converter 170 is configured to operate on a differential RF signal input from the differential input generator 150 to down convert the differential RF signal into a differential Low IF signal and output the differential RF signal.

The wireless communication system according to the present invention has a structure in which a differential input generator 150 for converting a single RF input into a differential input and a high linear hybrid frequency converter 170 are combined to enable a frequency conversion at low power while ensuring high linearity. It is key.

In addition, the present invention relates to broadband wireless communication, for example, WPAN communication such as IEEE 802.15.1 (Bluetooth) and IEEE 802.15.3a (UWB), IEEE 802.15.3c (WiHD) and IEEE 802.15.4 (Zigbee) It is about a module.

5 is a circuit diagram illustrating a differential input generator according to an embodiment of the present invention.

As illustrated in FIG. 5, the differential input generator 150 may include first and second cascaded connections between a low potential Vss and a first node Nd1 that is a virtual high potential Vdd. Third and fourth transistors M3 and M4 connected in a cascode manner between the transistors M1 and M2, the low potential Vss and the second node Nd2 having a virtual high potential, and the first node Nd1. And a first load L1 connected between the high potential Vdd and a second load L2 connected between the second node Nd2 and the high potential Vdd.

In addition, a first bias voltage Bis1 is applied to the gate terminal of the first transistor M1, and an RF signal output from the low noise amplifier 130 is applied to the drain. The second bias voltage Bis2 is applied to the gate terminal of the second transistor M2.

The RF signal output from the low noise amplifier 130 is applied to the gate terminal of the third transistor M3, and the second bias voltage Bis2 equal to the bias applied to the second transistor M2 is applied to the fourth transistor M4. ) Is applied.

The first and second nodes Nd1 and Nd2, which are the virtual high potentials Vdd, are output terminals for outputting differential RF signals RF + and RF-.

The differential input generator 150 outputs a sophisticated differential signal and has a class AB type input structure for linearity and ultra-wideband input matching.

That is, the first transistor M1 provides a bias to the second transistor M2 according to the RF signal input to the drain terminal. The second transistor M2 is a common gate amplifier.

The third transistor M3 is a common source amplifier, and the fourth transistor M4 provides a bias so that the first and third transistors M1 and M3 have a symmetrical structure.

When the size of the input RF signal is small, both the second and third transistors M2 and M3 operate as amplifiers.

However, when a + signal having a large RF signal is input from the low noise amplifier 130 to the differential input generator 150, the third transistor M3 operates according to the voltage difference Vgs between the gate and the source terminal of each transistor. The second transistor M2 is turned off. On the other hand, when the -signal having a large RF signal is input to the differential input generator 150, the second transistor M2 operates according to the voltage difference Vgs between the gate and the source terminal of each transistor, but the third transistor ( M3) is turned off.

As a result, even when a large RF signal is received, the differential input generator 150 operates in a class AB form, and maintains high linearity by converting and outputting a single RF signal into a differential RF signal.

6 is a circuit diagram illustrating a frequency converter according to an embodiment of the present invention.

As shown in FIG. 6, the frequency converter 170 includes a variable resistor unit 171 of a common source mode in which impedance is adjusted according to differential RF signals RF + and RF− input from the differential input generator 150. A frequency converter 173 connected between the variable resistor unit 171 and the virtual high voltage Vdd and operating in a saturation region according to an externally input differential local signal LO + or LO- to convert the RF signal down. And a load stage 175 installed between the virtual high potential and the high potential Vdd to convert a current signal into a voltage.

As shown in the figure, the transistors of the frequency converter 173 connected to the transistors of the variable resistor unit 171 are connected to each other in a cascode manner.

That is, the first and second transistors M11 and M12 connected in a cascode manner between the low potential Vss and the first node Nd1 which is the virtual high potential Vdd and the low potential Vss. And the third and fourth transistors M13 and M14 connected in a cascode manner between the second node Nd2 and the virtual high potential.

The first transistor M11 and the third transistor M13 are a common gate amplifier, and the RF signal RF + output from the differential input generator 150 is input, and the second transistor M12 and the fourth transistor M12 are input. Differential local signals LO + and LO- are respectively input to the gate terminal of.

In addition, the virtual high potential first and second nodes Nd1 and Nd2 are output stages for outputting down-converted differential IF signals Low IF + and Low IF-, respectively.

In addition, the frequency converter 170 may include the fifth and sixth transistors M15 and M16 connected in a cascode manner between the low potential Vss and the second node Nd2 which is a virtual high potential Vdd. The seventh and eighth transistors M17 and M18 are cascaded between the low potential Vss and the first node Nd1 having a virtual high potential.

The fifth transistor M15 and the seventh transistor M17 are a common gate amplifier, and the RF signal RF− output from the differential input generator 150 is input, and the sixth transistor M16 and the eighth transistor M18. The differential local signals LO + and LO- are respectively input to the gate terminal of the circuit.

In addition, the load terminal 175 may include a first load L11 connected between the first node Nd1 and a high potential Vdd, and a second node connected between the second node Nd2 and a high potential Vdd. It consists of two loads (L12).

The frequency converter 170 configured as described above receives the differential RF signals RF + and RF- from the differential input generator 150 to operate at low power and down-converts the frequency.

That is, the first, third, fifth and seventh transistors M11, M13, M15, and M17 are resistance elements controlled by differential RF signals. The second, fourth, sixth, and eighth transistors M12, M14, M16, and M18 are amplifiers whose transfer conductance is changed by a local signal LO.

The first and second loads L11 and L12 are loads such as resistors for converting a current signal into a voltage.

The frequency conversion method is an active method of consuming a DC current that generates IF by turning on / off a switch of a local signal LO by converting it into an RF signal current as shown in FIG. 2 or FIG. 3, and converting an RF signal into a local switch. There is a passive way of switching only by.

In the proposed circuit of FIG. 6, the first, third, fifth and seventh transistors M11, M13, M15, and M17 operate as a resistor, and the second, fourth, sixth, and eighth transistors M12, M14, M16, and M18 are hybrid frequency converters operating in the saturation region.

The second, fourth, sixth, and eighth transistors M12, M14, M16, and M18 may include first, third, fifth, and seventh transistors M11, M13, M15, and M17 that operate as a resistor. The second, fourth, sixth and eighth transistors M12, M14, M16, and M18 operate as amplifiers having a source degenerated structure, and the degenerated resistors In synchronization with the RF signal, the RF is converted into an IF frequency (Low IF or substantially baseband).

As described above, the first, third, fifth and seventh transistors M11, M13, M15, and M17 operate as a resistor to minimize DC current consumption, thereby enabling low power frequency conversion and outputting an IF signal. Each of the transistors M12, M14, M16, and M18 of the frequency converter 173 is composed of a source degenerated amplifier, thereby ensuring high linearity and excellent linearity.

7A and 7B are circuit diagrams schematically illustrating an equivalent circuit of the frequency converter 170 of FIG. 6, and FIG. 7A is equivalent to the first transistor M11, the second transistor M12, and the first load L11. 7B is a circuit diagram illustrating the instantaneous operation mode of FIG. 7A.

That is, the first transistor M11 may be represented by a variable resistor R _S because the resistance is changed according to an input RF signal, and the second transistor M12 may be represented by a capacitor Cgs and a current source gm · Vgs. Since the first load L11 is a load, the first load L11 may be represented by a resistor R _L. The capacitor Cgs denotes a parasitic capacitance between the gate terminal and the source terminal of the second transistor M12, and gm denotes the amount of current change in the drain terminal with respect to the voltage change of the gate terminal as the transfer conductance of the second transistor M12. .

The output for the instantaneous operation mode as shown in FIG. 7B is simply represented by Equation 1 below.

Where R _L is the load resistance, Y _S is the admittance value of the variable resistor, and V _in is the input local signal.

Equation 1 is expressed as an equation for the admittance Y _S of the variable resistor Rs by the RF signal.

Where L is the channel length of the second transistor M12, Cox is the capacitance per unit area, W is the channel width of the second transistor, V _RF is the input voltage, Vt is the threshold voltage and α is the proportional constant.

Substituting Y _S obtained in Equation 2 into Equation 1, the final output voltage Vout is shown in Equation 3.

Accordingly, as shown in Equation 3, the output voltage Vout of the frequency converter 170 is a frequency that is the product of the voltage V _in of the local signal and the voltage V _RF of the RF signal input from the differential input generator 150. The difference between the two signal frequencies is output by a filter (not shown) to be connected to the rear end of the converter to complete the frequency conversion.

In the present invention, the RF signal serves to change the variable resistance (Rs) of Equation 2, unlike the structure that amplified the conventional RF signal, greatly increases the linearity of the frequency down converter.

Therefore, in the present invention, when a device for generating a differential RF signal is designed as a class AB type input structure capable of wideband input matching, and the frequency converter is designed to have a variable resistance to the differential RF signal, when downconverting the RF signal. Low power and high linearity can be secured.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit of the present invention. Therefore, such modifications, changes and additions should be determined not only by the claims below, but also by equivalents to those claims.

1 is a diagram illustrating a reception apparatus of a general wireless communication system.

2 is a circuit diagram showing a frequency converter according to the prior art.

3 is a circuit diagram showing a frequency converter according to another example of the prior art.

4 is a circuit block diagram illustrating a broadband wireless communication system according to the present invention.

5 is a diagram illustrating a detailed circuit of the differential input generator of FIG. 4 according to an embodiment of the present invention.

6 is a diagram illustrating a detailed circuit of the frequency converter of FIG. 4 according to an embodiment of the present invention.

7a and 7b schematically show an equivalent circuit of the frequency converter according to the present invention.

* Explanation of symbols for the main parts of the drawings

110: bandpass filter 130: low noise amplifier (LNA)

150: differential input generator 170: frequency converter

171: variable resistor 173: frequency converter

175: load stage

Claims (7)

And a differential input generator for converting and outputting a single input RF signal into a differential RF signal, and a frequency converter for down converting and outputting a frequency of the differential RF signal input from the differential input generator. The frequency converter may include a variable resistor unit having a common source mode in which impedance is adjusted according to a differential RF signal input from the differential input generator; A frequency converter connected between the variable resistor unit and the virtual high potential to operate in a saturation region according to an externally input differential local signal to down convert an RF signal; And a load installed between the virtual high potential and the high potential to convert a current signal into a voltage. 2. The method according to claim 1, The variable resistor unit may include a first transistor having a source terminal connected to a low potential and receiving a differential RF signal at a gate terminal; A third transistor connected in parallel with the first transistor and receiving the same RF signal as the first transistor through a gate terminal; A fifth transistor connected in parallel with the third transistor and receiving a differential RF signal through a gate terminal; And a seventh transistor connected in parallel with the fifth transistor and receiving the same RF signal as the fifth transistor. The method according to claim 2, The frequency converter may include a second transistor connected between the first transistor and a first node having a virtual high potential and receiving a differential local signal at a gate end thereof; A fourth transistor connected between the third transistor and a second node having a virtual high potential and receiving a differential local signal through a gate terminal; A sixth transistor connected between the fifth transistor and a second node having a virtual high potential and receiving the same differential local signal as the second transistor through a gate terminal; And an eighth transistor connected between the seventh transistor and a first node having a virtual high potential, and receiving a differential local signal identical to a fourth transistor through a gate terminal thereof. The method according to claim 3, And the transistors connected to each other in the transistors of the variable resistor section and the transistors of the switching section are connected in a cascode manner. The method according to claim 3, And the second, fourth, sixth and eighth transistors are amplifiers of a source degeneration structure. The method according to claim 1, The differential input generator may include a first transistor having a source terminal coupled to a low potential and receiving a first bias voltage at a gate terminal; A second transistor installed between the first transistor and a first node having a virtual high potential and receiving a second bias voltage through a gate terminal; A third transistor having a source terminal coupled to a low potential and receiving a single RF signal through a gate terminal; A fourth transistor provided between the third transistor and a second node having a virtual high potential and receiving a second bias voltage through a gate terminal; A first load coupled between the first node and a high potential; And a second load coupled between the second node and a high potential. The method according to claim 6, And a RF signal output from the low noise amplifier is applied to the drain terminal of the first transistor.

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