KR20100003961A - Non-volatile memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a manufacturing method thereof are provided to improve threshold voltage distribution for implementing a multi level cell by controlling a trap site and an amount of charges trapped in a charge storage layer. CONSTITUTION: A groove(140) is selectively formed on a substrate(100). A tunneling layer, a charge storage layer, and a shield layer are formed along the groove on the substrate. A control gate layer is formed on the shield layer. The control gate layer, the shield layer, the charge storage layer, and the tunneling layer are patterned to overlap a part of the groove.

Description

Non-volatile memory device and method for manufacturing the same {Non-volatile memory device and method for fabricating the same}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a nonvolatile memory device and a method of manufacturing the same.

The nonvolatile memory device may be classified into a floating gate type memory device and a floating trap type memory device. In particular, the floating trap type memory device is superior to the floating gate type memory device in terms of mutual interference and charge retention, and thus, is positioned in a major position in the field of nonvolatile memory devices.

As the integration degree of a flash memory device is further increased, a multi-level cell (MLC) structure for selectively storing a plurality of data in one memory cell has been proposed. A multi-level cell has one memory cell, unlike a single level cell (SLC) in which one memory cell has two states of program / erase, and has more than two bits, three bits and four bits. Data can be represented, enabling more than twice the memory capacity of a single-level cell. Since multi-level cells have three or more program states, the threshold voltage distribution of the memory cells in the program state must be uniform.

However, as the memory cell size of the flash memory device is reduced, it is difficult to secure the threshold voltage VT distribution of the cells required for the multi-level cells. For example, as the memory cell size is reduced, the distribution of threshold voltages VT of the memory cells is increased, and thus the variation width of the threshold voltage is increasing. In addition, in order to improve the threshold voltage distribution, when the program voltage (PV) between steps is reduced during the programming of the ISPP (Incremental Step Pulse Proram) method, the program time is increased to increase the performance of the flange memory device. It is acting as a factor to lower performance.

A method of manufacturing a nonvolatile memory device of a semiconductor device according to the present invention comprises the steps of selectively forming a groove in the device plate; Forming a tunneling layer, a charge storage layer, and a shielding layer along grooves formed in the substrate; Forming a control gate layer on the shielding layer; And patterning the control gate layer, the shielding layer, the charge storage layer, and the tunneling layer such that a portion of the groove overlaps.

Forming a groove in the substrate may include forming a buffer oxide film on the substrate; Forming a hard mask nitride layer pattern on the buffer oxide layer; Forming an oxide layer by performing an oxidation process of growing a portion of the buffer oxide layer exposed by the hard mask nitride layer pattern: removing the hard mask nitride layer pattern; And removing the exposed portion of the buffer oxide layer and the oxide layer by removing the hard mask nitride layer pattern.

After forming the control gate layer, the method may further include performing a planarization process on the control gate layer.

In the patterning of the control gate layer, the shielding layer, the charge storage layer, and the tunneling layer, the control gate layer, the shielding layer, the charge storage layer, and the tunneling layer are preferably patterned to overlap the groove.

The charge storage layer may be formed of a floating gate layer including a polysilicon layer or a charge trap layer including a silicon nitride layer.

A nonvolatile memory device according to the present invention includes a substrate on which grooves selectively recessed to a predetermined depth from a surface thereof are disposed; And a tunneling layer pattern, a charge storage layer pattern, a shielding layer pattern, and a control gate pattern disposed on the substrate to overlap a portion of the groove.

The tunneling layer pattern, the charge storage layer pattern, and the shielding layer pattern may be disposed to overlap the region where the groove is formed.

The substrate surface is preferably formed in a wave shape by the groove.

(Example)

Referring to FIG. 1, after forming the buffer oxide film 110 on the semiconductor substrate 100, the hard mask nitride film pattern 120 is formed on the buffer oxide film 110.

Specifically, after forming the buffer oxide film 110 and the hard mask nitride film on the semiconductor substrate 100, a resist film pattern (not shown) for selectively exposing the hard mask nitride film by performing a photolithography process The hard mask nitride film is formed by etching the resist film pattern as an etching mask. Then, the hard mask nitride film pattern 120 to selectively expose the buffer oxide film 110 is formed.

Here, the buffer oxide film 110 serves to relieve stress that the semiconductor substrate 100 receives due to the attraction of the hard mask nitride film. The portion of the buffer oxide film 110 exposed by the hard mask nitride film pattern 120 is a region in which a groove is formed to be concavely removed from the surface to a predetermined depth in the subsequent semiconductor substrate 100. The hard mask nitride film pattern 120 serves to prevent a portion of the semiconductor substrate 100 from being oxidized in an oxidation process for selectively forming a groove in a subsequent semiconductor substrate.

Referring to FIG. 2, a thermal oxidation process is performed on a portion of the buffer oxide layer exposed by the hard mask nitride layer pattern 120. Then, the exposed portion of the buffer oxide film 110 extends up and down, thereby forming a relatively thick oxide film 130. In this case, as the oxide film 130 expands up and down, a shape, for example, a bird's beak, which is formed to be long and penetrates into the edge of the hard mask nitride film pattern 120, may be generated.

At this time, the portion of the buffer oxide film 110 exposed by the hard mask nitride film pattern 120 is expanded to the thick oxide film 130 by the oxidation process, and reacts with a portion of the lower semiconductor substrate 100 to react with the oxide film 130. As the C) grows, a concave groove is formed in the semiconductor substrate 100.

Referring to FIG. 3, the hard mask nitride film pattern 120 (refer to FIG. 2) may be selectively removed. Then, a portion of the buffer oxide film (110 of FIG. 2) and the oxide film (130 of FIG. 2) may be wet etched. And selectively removed to expose the grooves 140 formed in the semiconductor substrate 100. For example, a part of the surface of the semiconductor substrate 100 becomes a convex portion 141 by the groove, and the region in which the groove 140 is formed is removed from the surface of the semiconductor substrate 100 by a predetermined thickness to become a concave portion.

Accordingly, as the groove 140 is formed in the semiconductor substrate 100, the surface of the semiconductor substrate 100 on which the subsequent gate electrode is to be formed has a wave profile. Meanwhile, after the oxide film 130 is selectively removed, an additional oxidation process is performed on the semiconductor substrate 100 on which the grooves 140 are formed, so that the semiconductor substrate 100 of the region where the grooves 140 are formed and the block 141 is formed. The surface can have a more gentle bend.

Referring to FIG. 4, the tunneling layer 150, the charge storage layer 160, and the shielding layer 170 are formed along the surface of the semiconductor substrate 100 on which the grooves 140 are formed. In this case, the tunneling layer 150, the charge trap layer 160, and the shielding layer 170 may be formed in a wave shape having a bend by the groove 140 on the surface of the semiconductor substrate 100.

The tunneling layer 150 may be formed by performing a radical oxidation process, a thermal dry oxidation process, or a thermal wet oxidation process. The tunneling layer 150 may be formed to a thickness sufficient to prevent degradation by tunneling of repeated charges.

The charge storage layer 160 may be formed as a charge trap layer or a floating gate layer. For example, the charge trap layer may be formed to include a silicon nitride film having a chemical formula of Si ₃ N ₄ or Si _x N _y , and the floating gate layer may be formed to include a polysilicon film. The floating gate layer or the charge trap layer serves as a charge storage layer that stores charges passing through the tunnel oxide layer or the tunneling layer from the channel region of the semiconductor substrate 100.

The shielding layer 170 may include an insulating film such as silicon oxide or a high dielectric film. The shielding layer 170 prevents the charge trapped on the charge storage layer 160 from moving to the upper layer, for example, the control gate electrode to be subsequently formed.

The control gate electrode layer 180 is formed on the shielding layer 170. The control gate electrode layer 180 may be formed of a metal layer or, in some cases, a double layer of a metal layer and a polysilicon layer. The metal layer may include a material film such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbon nitride (TaCN). The control gate electrode layer 180 is configured to apply a bias of a predetermined size so that the charges of the semiconductor substrate 100 pass through the tunneling layer 150 and are trapped in a trap site in the charge trap layer 160. The layer may perform a program and erase operation according to a bias applied to the control gate electrode layer 180.

 On the other hand, after the control gate electrode layer 180 is formed, a planarization, for example, a chemical mechanical polishing (CMP) process is performed. As the planarization process is performed, the surface of the control gate electrode layer 180 may be flattened, and subsequent gate patterning may be easily performed.

Referring to FIG. 5, a resist film pattern (not shown) is formed on the planarized control gate electrode layer 180, and a control gate layer, a shielding layer, a charge storage layer, and a tunneling layer exposing the resist film pattern as an etching mask. Etch selectively. Then, the control gate layer pattern 181, the shielding layer pattern 171, the charge storage layer pattern 161, and the tunneling layer pattern 151 are formed on the semiconductor substrate 100 so as to overlap a portion of the groove 140. .

In this case, the resist film pattern may be formed to overlap a portion of the groove 140 of the semiconductor substrate 100 or to overlap an area where the groove 140 is formed. Accordingly, the control gate layer pattern 181, the shielding layer pattern 171, the charge storage layer pattern 161, and the tunneling layer pattern 151 may be partially formed in the groove 140 according to the region where the resist layer pattern is formed. Each of the convex portions 140 may be formed to overlap each other by the groove 140, and may be formed to overlap with an area where the groove 140 is formed.

As shown in FIG. 5, the nonvolatile memory device may include a semiconductor substrate 100 having a groove 140 concave to a predetermined depth from a surface thereof, and a portion of the groove 140 on the semiconductor substrate 100. The tunneling layer pattern 151, the charge storage layer pattern 161, the shielding layer pattern 171, and the control gate pattern 191 are disposed to overlap each other. In this case, the surface of the semiconductor substrate 100 may have a wave shape in which concave grooves 140 and convex portions 141 are alternately formed. In addition, the tunneling layer pattern 151, the charge storage layer pattern 161, and the shielding layer pattern 171 may overlap the region in which the groove 140 is formed.

According to the nonvolatile memory device and the manufacturing method thereof according to the present invention, as the concave groove is disposed in the semiconductor substrate, the concave portion and the convex portion are included in the tunneling layer pattern, the charge trap layer pattern, and the shielding layer pattern. Accordingly, when a subsequent program voltage is applied, the threshold voltage distribution for implementing a multi-level cell can be improved by adjusting the amount of charge trapped in the charge storage layer and the trap site along the bend.

For example, when a program voltage is applied to the control gate electrode layer during a subsequent program operation, an electric field is strongly applied to the convex charge trap layer portion, compared to the groove region, so that charge starts to be programmed at a low program voltage. Subsequently, when the program voltage is increased, the electric field of the groove region is strongly applied, and charges are trapped in the entire charge trap layer. That is, the amount of charge stored in the charge storage layer is sensitively changed according to the program voltage. Accordingly, the amount of charge trapping according to each voltage during the programming according to the first program voltage, the second program voltage, and the third program voltage level of the multi-level cell is separated according to each level, and thus the threshold voltage according to each program voltage level. Distribution can be improved. In addition, since the channel length can be further extended, cell threshold voltage interference can be improved.

As mentioned above, although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Of course.

1 to 5 are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to the present invention.

Claims (8)

Selectively forming grooves in the substrate; Forming a tunneling layer, a charge storage layer, and a shielding layer along grooves formed in the substrate; Forming a control gate layer on the shielding layer; And Patterning the control gate layer, shielding layer, charge storage layer, and tunneling layer such that a portion of the groove overlaps. The method of claim 1, Forming a groove in the substrate, Forming a buffer oxide film on the substrate; Forming a hard mask nitride layer pattern on the buffer oxide layer; Forming an oxide layer by performing an oxidation process of growing a portion of the buffer oxide layer exposed by the hard mask nitride layer pattern; Removing the hard mask nitride layer pattern; And And removing the exposed portion of the buffer oxide layer and the oxide layer by removing the hard mask nitride layer pattern. The method of claim 1, And after the forming of the control gate layer, performing a planarization process on the control gate layer. The method of claim 1, The patterning of the control gate layer, the shielding layer, the charge storage layer, and the tunneling layer may include forming the control gate layer, the shielding layer, the charge storage layer, and the tunneling layer so as to overlap the groove. . The method of claim 1, And the charge storage layer is formed of a floating gate layer including a polysilicon layer or a charge trap layer including a silicon nitride layer. A substrate selectively disposed with a recess concave to a predetermined depth from the surface; And And a tunneling layer pattern, a charge storage layer pattern, a shielding layer pattern, and a control gate pattern disposed on the substrate to overlap a portion of the groove. The method of claim 6, The tunneling layer pattern, the charge storage layer pattern, and the shielding layer pattern may be disposed to overlap the region where the groove is formed. The method of claim 6, And the substrate surface has a wave shape by the groove.

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