KR20100002834A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display for preventing an indication error is provided to prevent a parasitic capacitance difference between gate sources according to the overlay deviation in a transistor manufacturing process. CONSTITUTION: A first insulating layer is located on a plurality of gate lines(120) and a plurality of common voltage lines. A plurality of data lines(130) includes a third line unit(131) arranged from a first electrode area(135). The first electrode domain is overlapped at two scanning lines in one side and the other side of the gate area. A second electrode domain is overlapped in one side and the other side of the gate region at two scanning lines. A contact area in which a plurality of metal electrodes is connected to the pixel electrode is had.

Description

Liquid Crystal Display

The present invention relates to a liquid crystal display device.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs), may be used. Usage is increasing. Among them, a liquid crystal display device capable of realizing high resolution and capable of large size as well as small size is widely used.

Such a liquid crystal display device is largely composed of a transistor array substrate and a color filter substrate. A subpixel including a transistor including a gate, a semiconductor layer, a source and a drain, and a pixel electrode connected to a source or a drain of the transistor is formed on the transistor array substrate. A color filter and a black matrix are formed on the color filter substrate.

On the other hand, the source and the drain during the transistor manufacturing process is formed based on the gate, there has been a problem that the source and the drain is slightly distorted by the overlay (overlay) in the prior art.

In addition to the description regarding the overlay deviation, in the case of transistors disposed in the same direction on the same substrate, the parasitic capacitance Cgs between the gate and the source may be formed the same even if the interlayer overlay is distorted. However, as shown in FIG. 1, when forming a source and a drain, the Cgs value between the subpixels varies depending on which direction the gate is formed when the source and the drain are formed. Here, the difference in the Cgs value eventually causes a difference in ΔVp. This problem causes a difference in the degree of voltage charging in the sub-pixels, resulting in display defects such as dim or specific spots. Therefore, improvement is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of preventing a parasitic capacitance (Cgs) difference between gate sources due to an overlay deviation during a transistor manufacturing process. It is to solve the problem that causes display defects such as dim or specific stains.

According to the above-described problem solving means, the present invention includes: a plurality of gate wirings disposed on a substrate and having a first wiring portion arranged in a first direction and a gate region extending from the first wiring portion to be orthogonal to the first direction; A plurality of common voltage wirings positioned on the substrate and spaced apart along the plurality of gate wirings; A first insulating film on the plurality of gate lines and the plurality of common voltage lines; A plurality of data lines disposed on the first insulating layer and having a third wiring portion arranged in a second direction and a first electrode region overlapping one side and the other side of the gate region for every two scanning lines; And a second electrode region on the first insulating layer, the second electrode region overlapping every two scanning lines on one side and the other side of the gate region so as to face the first electrode region, and a contact region connected to the pixel electrode, wherein the second electrode region is a gate region. A liquid crystal display device including a plurality of metal electrodes overlapping all of them is provided.

The second electrode region may be formed longer in the second direction than the contact region, and the contact region may be formed longer in the first direction than the second electrode.

The plurality of metal electrodes may be formed in a (v) or (v) shape.

The width of the gate region may be wider than the width of the first wiring portion.

As the first electrode region overlaps one side and the other side of the gate region every two scan lines, the second electrode region facing the first electrode region may alternately take different voltages every two scan lines.

The present invention provides a liquid crystal display device that can prevent the parasitic capacitance (Cgs) difference between the gate source due to the overlay deviation during the transistor manufacturing process, such as display such as dim (dim) or specific spots according to the voltage charging degree in the sub-pixel There is an effect that can solve the problem causing the defect.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment may include a light source 171 for emitting light. For the light source 171, for example, Cold Cathode Fluorescent Lamp (CCFL), Hot Cathode Fluorescent Lamp (HCFL), External Electrode Fluorescent Lamp (EEFL) and Luminescence One of a diode (Light Emitting Diode: LED) may be selected, but is not limited thereto.

The light source 171 may select any one of an edge type in which the lamp is located at one side outside, a dual type in which the lamp is located at both sides, and a direct type in which a plurality of lamps are arranged in a straight line, but is not limited thereto. The light source 171 as described above may be connected to an inverter to receive power by emitting power.

In addition, the liquid crystal display may include an optical film layer 176 for guiding light emitted from the light source 171. The optical film layer 176 may include a diffusion plate 172, a diffusion sheet 173, an optical sheet 174, and a protective sheet 175 positioned on the light source 171.

The optical sheet 174 may be, for example, a prism shape as shown, but may be positioned in a shape such as a lenticular lens or a micro lens. And such an optical sheet 174 may include a bead.

In addition, the liquid crystal display may include a liquid crystal panel 183 for displaying an image and an upper case 190 and a lower case 170 in which the light source 171 is accommodated. The lower case 170 may receive the light source 171. The liquid crystal panel 183 may be disposed on the light source 171 at a predetermined interval. The liquid crystal panel 183 and the light source 171 may be fixed and protected by the upper case 190 fastened to the lower case 170.

An opening for exposing an image display area of the liquid crystal panel 183 may be provided on an upper surface of the upper case 190. In addition, a mold frame (not shown) may be further included in which a peripheral portion of the optical film layer 176 positioned between the liquid crystal panel 183 and the light source 171 is seated.

The liquid crystal panel 183 may have a structure in which a substrate 110 having a transistor or the like and a substrate 180 having a color filter or the like are bonded to each other with a liquid crystal layer interposed therebetween. In the liquid crystal panel 183, sub-pixels driven independently by transistors are arranged in a matrix form.

The driving unit 189 may be connected to the substrate 110 of the liquid crystal panel 183. The driver 189 includes a plurality of film circuits 186 on which the substrate 110 and one side are connected by mounting a driving chip 187 for driving the data wirings and the gate wirings of the panel 183, respectively. It may include a printed circuit board 188 connected with the other side of the (186).

The film circuit 186 on which the driving chip 187 is mounted represents a chip on film (COF) or tape carrier package (TCP) method. Alternatively, the driving chip 187 may be directly mounted on the substrate 110 by a chip on glass (COG) method or may be formed and embedded on the substrate 110 in a transistor forming process.

The subpixels positioned on the substrate 110 of the liquid crystal panel 183 may receive a driving signal from the driving chip 187. The driving chip 187 may include a data driver for supplying a data signal to the subpixel and a scan driver for supplying a scan signal to the subpixel.

At least one of the data driver and the scan driver may be directly mounted on the substrate 110 by a chip on glass (COG) method, or may be formed and embedded on the substrate 110 in a transistor forming process.

According to such a structure, when a sub-pixel positioned on the substrate 110 is supplied with a scan signal, the liquid crystal array is arranged according to a difference voltage between a common voltage supplied to the common electrode and a data signal supplied to the pixel electrode connected to the transistor. Can be displayed by controlling the light transmittance.

Hereinafter, the arrangement structure of the sub pixels will be described with reference to some schematic diagrams of the Z area.

FIG. 2 is a partial schematic view of the Z region of FIG. 1. However, only the ones arranged on the part of the scan lines S1..S6 are schematically illustrated in the illustrated subpixels SP011..SP063.

As illustrated in FIG. 2, each sub-pixel SP011... SP063 may be positioned between the gate line 120 and the data line 130 intersecting on the substrate 110. Each of the sub-pixels SP011.. SP063 positioned at the intersection of the gate line 120 and the data line 130 may receive a scan signal from the gate line 120 and receive a data signal from the data line 130. A common voltage may be supplied from the common voltage line 150.

Each sub-pixel SP011 .. SP063 may include a transistor and a storage capacitor connected to the gate line 120 and the data line 130. Here, the transistor may be connected to the metal electrode 140 which transfers the data signal supplied through the source or drain to the pixel electrode.

On the other hand, an embodiment of the present invention is a liquid crystal display device implemented to be driven in a two-dot Z inversion method arranged in the structure shown in FIG.

In the liquid crystal display having the structure as described above, the data lines 130 are alternately wired so that the two scan lines S1, S2, S3, and S4 overlap one side and the other side of the gate region of the transistor. Accordingly, the transistors included in each of the subpixels SP011... SP063 are alternately disposed on one side and the other side of the two scan lines S1, S2, S3, and S4 based on the data line 130.

Therefore, the transistors positioned in the first and second scan lines S1 and S2 and the transistors located in the third and fourth scan lines S3 and S4 are arranged in left-right symmetry. When the transistors are arranged symmetrically in this manner, different voltages may be alternately applied to the two scan lines S1, S2, S3, and S4.

Hereinafter, the subpixel will be described with reference to FIG. 3.

3 is a schematic diagram of the subpixel illustrated in FIG. 2, and FIG. 4 is a cross-sectional view of an area A1-A2 of FIG. 3.

As shown in FIGS. 3 and 4, one subpixel includes a first wiring part 121 arranged in a first direction (x direction) and a first wiring part (orthogonal to the first direction (x direction)). It may include a plurality of gate wiring 120 having a gate region 125 extending from 121. In addition, the plurality of common voltage wires 150 may be disposed to be spaced apart along the plurality of gate wires 120. In addition, the first insulating layer 115 may be disposed on the plurality of gate lines 120 and the plurality of common voltage lines 150. In addition, the third wiring unit 131 disposed on the first insulating layer 115 and arranged in the second direction (y direction), and the first electrode region 135 overlapping one side and the other side of the gate region for every two scanning lines. ) May include a plurality of data lines 130. In addition, a second electrode region 141 and a pixel electrode disposed on the first insulating layer 115 and overlapping each scan line on one side and the other side of the gate region 125 so as to face the first electrode region 135. The second electrode region 141 may include a plurality of metal electrodes 140 having a contact region 145 connected to the 160 and overlapping the gate region 125.

Referring to FIG. 4, the transistor may include a gate region 125 formed on the first substrate 110. The gate region 125 is a region that substantially becomes a gate of the transistor among the gate lines 120. Materials for forming the gate are in the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be made of any one or an alloy thereof. In addition, any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be a multilayer consisting of an alloy of. It may also be a bilayer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

In addition, the transistor may include a first insulating layer 115 positioned on the gate region 125. The first insulating film 115 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

In addition, the transistor may include an active layer 116 positioned on the first insulating layer 115. In addition, the ohmic contact layer 117 may be disposed in the source region and the drain region defined on the active layer 116. The active layer 116 may be formed of a-Si or p-Si, and the ohmic contact layer 117 may be positioned to reduce electrical contact resistance.

In addition, the transistor may include a first electrode region 135 and a second electrode region 141 in contact with the active layer 116 and the ohmic contact layer 117. The first electrode region 135 and the second electrode region 141 are regions which become substantially a source or a drain of the data line 130 and the metal electrode 140. The source and drain may consist of a single layer or multiple layers. When the source and drain are monophosphorus, materials for forming them include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be made of any one or an alloy thereof selected from the group consisting of copper (Cu). On the other hand, when the source and drain are multiple layers, the material for forming the layer may be a double layer of molybdenum / aluminum-neodymium, a triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

In addition, the transistor may include a second insulating layer 119 positioned on the first electrode region 135 and the second electrode region 141. The second insulating layer 119 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating layer 119 may be a passivation layer.

In the transistor formed as described above, the contact region 145 of the metal electrode 140 may be connected to the pixel electrode 160 positioned on the second insulating layer 119 through the via hole VH. The pixel electrode 160 may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

The second electrode region 141 is formed longer in the second direction (y direction) than the contact region 145, and the contact region 145 is formed longer in the first direction (x direction) than the second electrode 141. Can be. That is, the plurality of metal electrodes 140 may be formed in a (ㅓ) or (ㅏ) shape.

Meanwhile, the width of the gate region 125 is wider than the width of the first wiring portion 121. As such, when the width of the gate region 125 is formed to be wide in the first direction (x direction), the first electrode region 135 and the second electrode region 141 serving as a source and a drain due to an overlay deviation may be formed. Even if the first direction (x direction) is shifted to the left or the right, parasitic capacitance Cgs between the gate sources of the transistor can be formed in the same manner.

In the case of the Cgs deviation of the transistor, the distortion in the second direction (y direction) is the same in the transistor structure arranged in the left-right symmetry so that the same Cgs difference occurs, so that the luminance difference between the subpixels does not occur. However, the distortion in the first direction (x direction) causes a large Cgs difference in the transistor structure arranged in a symmetrical manner, and thus a luminance difference between subpixels occurs.

In this case, when the width of the gate region 125 increases, the Cgs becomes slightly larger, and thus, ΔVp may be prevented from increasing by increasing the storage capacitor and the liquid crystal layer Clc in the subpixel design.

Hereinafter, the Cgs difference of the transistors in the occurrence of the overlay deviation will be described by comparing the present invention with the prior art.

5 and 6 are diagrams for explaining the difference in the Cgs of the transistor according to the overlay deviation between the prior art and the present invention. 5 and 6, reference numerals are written only to the main parts necessary for explanation.

5 and 6 are diagrams showing that the source and the drain of the transistor are twisted due to the overlay deviation. "OLn" in Figs. 5 and 6 indicates the deviation occurrence region of the transistor located in the nth scan line, and "OLn + k indicates the deviation occurrence region of the transistor located in the n + kth scan line.

In the case of the conventional transistor illustrated in FIG. 5, the width of the gate region 125 has a narrow width similar to that of the first wiring portion 121. Accordingly, when the overlay deviation occurs in the right arrow direction (x direction), when the first electrode region 135 and the second electrode region 141 serving as the source and the drain are formed to be oriented in the x direction, the transistor Cgs There will be a difference. That is, the Cgs value of the transistor located in the nth scan line and the Cgs value of the transistor located in the n + kth scan line may cause problems due to the DELTA Vp difference in relation to the degree of overlay deviation.

In contrast, in the transistor of the exemplary embodiment illustrated in FIG. 6, the width of the gate region 125 has a width larger than that of the first wiring part 121. Accordingly, when the overlay deviation occurs in the right arrow direction (x direction), even if the first electrode region 135 and the second electrode region 141 serving as the source and drain are formed to be oriented in the x direction, the gate region ( Since the first electrode region 135 and the second electrode region 141 are included in the 125, the Cgs difference between the transistors does not occur. That is, the Cgs value of the transistor located in the nth scan line and the Cgs value of the transistor located in the n + kth scan line are irrelevant to the degree of overlay deviation occurrence, thereby preventing a problem due to the DELTA Vp difference.

One embodiment of the present invention provides a liquid crystal display device that can prevent the parasitic capacitance (Cgs) difference between the gate source due to the overlay deviation during the transistor manufacturing process, so that the dim (Dim) There is an effect that can solve the problem that causes display defects such as certain stains.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a partial schematic view of the Z region of FIG. 1. FIG.

3 is a schematic diagram of the sub-pixel shown in FIG.

4 is a cross-sectional view of region A1-A2 of FIG. 3;

5 and 6 are diagrams for explaining the difference in the Cgs of the transistor according to the overlay deviation between the prior art and the present invention.

<Explanation of symbols on main parts of the drawings>

110: substrate 115: first insulating film

116: active layer 119: second insulating film

120: gate wiring 121: first wiring portion

125: gate region 130: data wiring

131: second wiring unit 135: first electrode region

140: metal electrode 141: second electrode region

145: contact region 150: common voltage wiring

160: pixel electrode VH: via hole

Claims (5)

A plurality of gate wirings disposed on a substrate and having a first wiring portion arranged in a first direction and a gate region extending from the first wiring portion to be orthogonal to the first direction; A plurality of common voltage lines positioned on the substrate and spaced apart from each other along the plurality of gate lines; A first insulating layer on the plurality of gate lines and the plurality of common voltage lines; A plurality of data lines disposed on the first insulating layer and having a third wiring portion arranged in a second direction, and a first electrode region overlapping one side and the other side of the gate region every two scan lines; And A second electrode region on the first insulating layer, the second electrode region overlapping every two scanning lines on one side and the other side of the gate region so as to face the first electrode region, and a contact region connected to the pixel electrode; And a plurality of metal electrodes overlapping all of the gate regions. The method of claim 1, The second electrode region is formed longer in the second direction than the contact region, And the contact region is formed longer in the first direction than the second electrode. The method of claim 1, The plurality of metal electrodes, A liquid crystal display device which is formed in a (iii) or (v) shape. The method of claim 1, The width of the gate region, And a width wider than the width of the first wiring portion. The method of claim 1, As the first electrode region overlaps one side and the other side of the gate region every two scanning lines, the second electrode region facing the first electrode region alternately applies different voltages every two scanning lines. LCD display device.

Images