KR20100001834A - Refresh characteristic test circuit - Google Patents

Abstract

PURPOSE: A refresh characteristic test circuit is provided test a refresh characteristic of a memory cell replaced by a redundancy cell by controlling enable of main word line signals. CONSTITUTION: In a device, a test signal generating unit(1) generates a first and the second test signal according to a selection signal and a test mode enable signal. A block signal generating unit(2) generates a plurality of block signals according to a first test signal and at least address signal. A main word line signal generator(3) generates a plurality of main word line signals according to a second test signal and at least second address signal. A sub word line signal generator(4) generates a plurality of sub word line signals according to the test mode enable signal, the second test signal, a plurality of third address signals. A first and the second test signal are enabled selectively in response to the selection signal while the test mode enable signal is activated.

Description

Refresh Characteristic Test Circuit

The present invention relates to a semiconductor memory device, and more particularly, to a refresh characteristic test circuit capable of testing a refresh fail.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. For example, the shortening of transistors is rapidly progressing due to the decrease in the width of the gate, and thus short channel effects are frequently generated. Due to the short channel effect, punch-through between the source and the drain of the transistor is seriously generated, which is recognized as a major cause of malfunction of the device. Therefore, in order to overcome the short channel effect, various methods for securing channel lengths without increasing design rules have been studied in various ways. In particular, a recess gate structure semiconductor device, which extends the channel length by recessing the semiconductor substrate under the gate as a structure that extends the channel length to a limited gate line width, has been in the spotlight.

Increasing the channel length reduces the amount of ion implantation for generating the threshold voltage, so that the semiconductor device of the recess gate structure can increase the refresh time compared to the semiconductor device of the planar gate structure. . Here, the refresh time is the charge stored in the capacitor of the storage node because of the generation / recombination current, that is, leakage current generated by the trap present in the depletion region of the storage node. Is lost, it can be said that it takes time until the sense amplifier does not properly sense the information stored in the capacitor.

 1 illustrates a cell array of a semiconductor device having a recess gate structure.

As shown, the semiconductor device of the recess gate structure includes neighbor gates N8-N10 and passing gates N3, N4, N11, and N12 that are inevitably generated to obtain a cell array. Here, the neighbor gates N8-N10 are gates formed in the same region as the selected gates N5-N7 when the second word line WL2 is selected and a voltage is applied thereto. The passing gates N3, N4, N11, and N12 are gates formed in regions different from the selected gates N5-N7. Adjacent gate in the turn-off state by a voltage applied to the second word line WL2 even when a voltage is not directly applied to the first word line WL1, the third word line WL3, and the fourth word line WL4. Neighbor Gates N8-N10 and Passing Gates N3, N4, N11, and N12 are changed to a sub-threshold state to increase leakage current. As such, the increase in leakage current through neighboring gates (N8-N10) and passing gates (N3, N4, N11, and N12) in the turn-off state may result in an adjacent / passing gate effect. It is called.

 When the adjacent / passing gate effect occurs, the amount of leakage current generated in the trap is rapidly increased by the trap-assisted tunneling effect. Increasing the amount of leakage current reduces the refresh time, which can result in a refresh fail.

The present invention provides a refresh characteristic test circuit for screening whether or not a refresh fail is generated by an adjacent / passing gate effect in a semiconductor device having a recess gate structure.

To this end, the present invention includes a test signal generation unit for receiving the selection signal and the test mode enable signal to generate the first and second test signals; A block signal generation unit receiving the first test signal and at least one first address signal and generating a plurality of block signals; A main word line signal generator configured to receive the second test signal and at least one second address signal and generate a plurality of main word line signals; And a subword line signal generator configured to receive the test mode enable signal, the second test signal, and a plurality of third address signals to generate a plurality of subword line signals.

In the present invention, it is preferable that the first and second test signals are selectively enabled in response to the selection signal in a state in which the test mode enable signal is enabled.

The test signal generation unit may include a logic unit configured to receive a test mode enable signal and a bank active signal and perform a logic operation; A buffer unit for outputting first and second control signals by buffering an output signal of the logic unit; A logic element configured to receive the first control signal and the output signal of the logic unit and perform logic operation; And a transfer unit for selectively transferring the second control signal or the output signal of the logic element in response to the selection signal.

In an embodiment, the buffer unit may include: a first inverter configured to generate the first control signal by inverting an output signal of the logic unit; And a second inverter generating the second control signal by inverting the output signal of the first inverter.

In the present invention, the transfer unit is a first transfer element for transmitting the second control signal in response to the selection signal; And a second transfer element transferring an output signal of the logic element in response to the selection signal.

In the present invention, the block signal generation unit preferably enables all of the plurality of block signals when the first test signal is enabled.

The block signal generation unit may include an address input unit configured to receive the first address signal and generate a block address signal in response to the first test signal; And a decoder for decoding the block address signal to generate the plurality of block signals.

The address input unit may include: a buffer configured to buffer and transfer the first address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the first test signal and perform logic operation.

In the present invention, the main word line signal generator may enable all of the plurality of main word line signals when the second test signal is enabled.

The main word line signal generator may include an address input unit configured to receive the second address signal in response to the second test signal and generate a main word line address signal; And a decoder for decoding the main word line address signal to generate the plurality of main word line signals.

The address input unit may include: a buffer configured to buffer and transfer the second address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the second test signal and perform logic operation.

The address input unit may include: a buffer configured to buffer and transfer the second address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; A second logic element configured to receive an inverted signal of the second test signal and the redundancy signal and perform a logic operation; And a third logic element configured to receive output signals of the first logic element and the second logic element and perform logic operation.

The subword line signal generation unit classifies the plurality of subword line signals into at least two groups according to the third address signal when the test mode enable signal and the second test signal are enabled. In addition, it is preferable to sequentially enable the subword lines included in the group.

The subword line signal generator may include a first address input unit configured to receive a partial address of the third address signal in response to the second test signal to generate a first subword line address; A second address input unit configured to receive a remaining address among the third address signals and generate a second subword line address in response to the test mode enable signal; And a decoder for decoding the first and second subword line addresses to generate the plurality of subword line signals.

In an embodiment, the first address input unit may include a buffer configured to buffer and transfer some of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the second test signal and perform logic operation.

The second address input unit may include a buffer configured to buffer and transfer the remaining addresses of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; A buffer unit configured to buffer the test mode enable signal in response to the test mode enable signal; And a second logic element configured to receive an output signal of the first logic element and an output signal of the buffer unit to perform logic operation.

In the present invention, the decoder classifies the plurality of subword line signals into at least two groups when the first subword line address is enabled, and classifies the subword lines included in the group into the second subword line. It is desirable to enable sequentially in response to the address.

The present invention may also include a test signal generation unit configured to generate first and second test signals selectively enabled in response to a selection signal in a state in which a test mode enable signal is enabled; A block signal generation unit configured to receive the first test signal and at least one first address signal and generate a plurality of block signals, wherein the plurality of block signals are all enabled when the first test signal is enabled; Generates a plurality of main word line signals by receiving the second test signal and at least one second address signal, wherein the plurality of main word line signals are all enabled when the second test signal is enabled A line signal generator; And generating a plurality of subword line signals by receiving the test mode enable signal, the second test signal, and the plurality of third address signals, wherein the test mode enable signal and the second test signal are enabled. According to the third address signal, the plurality of subword line signals are classified into at least two groups, and a sub word line signal generation unit for sequentially enabling the sub word lines included in the group provides a refresh characteristic test circuit do.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

The semiconductor memory device of the present embodiment is composed of 32 cell blocks (sometimes referred to as MATs), each cell block including 32 main word lines (MWL), each main word The line includes eight sub word lines (SWL).

2 is a diagram illustrating a configuration of a refresh characteristic test circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the refresh characteristic test circuit according to the present embodiment includes a test signal generator 1, a block signal generator 2, a main word line signal generator 3, and a subword line signal generator. It consists of (4).

The test signal generator 1 receives the selection signal MATSEL and the test mode enable signal TMEN to generate the first test signal TM1 and the second test signal TM2. In more detail with reference to FIG. 3, the test signal generator 1 receives an inverted signal of a test mode enable signal TMEN and a bank active signal BACTB and performs a logical product operation 10. ), A buffer unit 11 for buffering the output signal S1 of the logic unit 10 and outputting the first control signal S1B and the second control signal S2, the first control signal S1B, Selecting an output signal of the second control signal S2 or the NOR gate NR10 in response to the selection signal MATSEL in response to the selection signal MATSEL in response to the selection signal MATSEL The second test signal by buffering the transfer unit 12 to be transmitted to the buffer, the buffer 13 outputting the first test signal TM1 by buffering the output signal of the transfer unit 12, and the second control signal S2. It consists of the buffer 14 which outputs TM2.

The buffer unit 11 inverts the output signal S1 of the logic unit 10 to generate the first control signal S1B and the output signal of the inverter IV12 and inverter IV12 to invert the second control signal ( An inverter IV13 generating S2).

The transfer unit 12 transmits the transfer gate T10 for transmitting the second control signal S2 in response to the selection signal MATSEL, and the output signal for the north gate NR10 in response to the selection signal MATSEL. It is composed of a transfer gate T11.

As shown in FIG. 4, the block signal generation unit 2 receives the address signals ADD <1: 5> in response to the first test signal TM1 and receives the block address signals XADD <1: 5>. A first address input unit 20 for generating a plurality of blocks and a first decoder 22 for generating a plurality of block signals MAT <1:32> by decoding the block address signals XADD <1: 5>. do.

As illustrated in FIG. 5, the first address input unit 20 includes an inverter IV21 for inverting and transmitting the address signals ADD <1: 5> in response to the input enable signal XAEB, and input enable. In response to the signal XAEB, a latch 200 for latching an output signal of the inverter IV21, an inverted signal of the input enable signal XAEB, and an output signal of the latch 200 are input to perform an AND operation. The NAND gate ND20, the output signal of the NAND gate ND20, and the inverted signal of the first test signal TM1, and perform an AND logic operation to output a block address signal XADD <1: 5>. It consists of a NAND gate ND21. When the first test signal TM1 of the high level is input, the first address input unit 20 generates the block address signals XADD <1: 5> which are all enabled at the high level.

The first decoder 22 is implemented by a general decoder circuit to decode the block address signals XADD <1: 5> to generate a block signal MAT <1:32> that is selectively enabled. When all of the block address signals XADD <1: 5> enabled at the high level are input, the first decoder 22 generates the block signals MAT <1:32> enabled at the high level.

As illustrated in FIG. 6, the main word line signal generator 3 receives an address signal ADD <6: 9> in response to the second test signal TM2, and receives the main word line address signal XADD <6. And a main address line address signal XADD <10> by receiving the address signal ADD <10> in response to the second test signal TM2 and the second address input unit 30 for generating the &lt; 9 &gt; A second decoder 34 which decodes the third address input unit 32 and the main word line address signal XADD <6:10> to generate a plurality of main word line signals MWL <1:32>. It consists of.

As illustrated in FIG. 7, the second address input unit 30 includes an inverter IV31 for inverting and transmitting the address signals ADD <6: 9> in response to the input enable signal XAEB, and input enable. In response to the signal XAEB, a latch 300 for latching an output signal of the inverter IV31, an inverted signal of the input enable signal XAEB, and an output signal of the latch 300 are input to perform an AND operation. The NAND gate ND30, the output signal of the NAND gate ND30, and the inverted signal of the second test signal TM2, and perform an AND logic operation to perform a negative AND operation to perform a main word line address signal XADD <6: 9>. It is composed of a NAND gate (ND31) for outputting. When the second test signal TM2 of the high level is input, the second address input unit 30 generates the main word line address signals XADD <6: 9> which are all enabled at the high level.

As illustrated in FIG. 8, the third address input unit 32 includes an inverter IV36 for inverting and transmitting the address signal ADD <10> in response to the input enable signal XAEB, and the input enable signal ( A NAND that receives a latch 320 for latching an output signal of the inverter IV36 in response to XAEB, an inverted signal of the input enable signal XAEB, and an output signal of the latch 320 and performs an AND logic operation. A NAND gate ND33 that receives an inverted signal of the redundancy signal RED that is enabled when the gate ND32 and the second test signal TM2 and the defective cell are replaced with the redundancy cell, and performs an AND logic operation, The NAND gate ND34 receives the output signals of the NAND gate ND32 and the NAND gate ND33 and performs a negative logic product to output a main word line address signal XADD <10>. The third address input unit 32 does not replace the defective cell with the redundancy cell, so that when the high level second test signal TM2 is input while the redundancy signal RED is low level, the main word line address enabled with the high level is enabled. Generate signal XADD <10>. At this time, when the redundancy cell is replaced with the redundancy cell and the redundancy signal RED transitions to a high level, the address signal ADD <10> is transmitted to the main word line address signal XADD <10>.

The second decoder 34 is implemented by a general decoder circuit to decode the main word line address signal XADD <6:10> to generate the main word line signals MWL <1:32> that are selectively enabled. . When the second decoder 34 receives the main word line address signal XADD <6:10> which is all enabled at the high level, the second decoder 34 all the main word line signals MWL <1:32> are enabled at the high level. ) Meanwhile, when the bad cell is replaced with the redundancy cell, when the address signal ADD <10> is input at the low level, some of the main word line signals MWL <1:32> are at the low level.

As illustrated in FIG. 9, the subword line signal generator 4 receives the address signal ADD <11> in response to the second test signal TM2 and receives the subword line address signal XADD <11>. The sub address line address signal XADD <12:13> is received by receiving the address signal ADD <12:13> in response to the fourth address input unit 40 and a test mode enable signal TMEN. A third decoder 44 for generating a plurality of subword line signals SWL <1: 8> by decoding the generated fifth address input unit 42 and the subword line address signals XADD <11:13>. It is composed of The subword line signals SWL <1: 8> are a first group of subword line signals SWL <1: 4> and a second group of subword line signals SWL <5: 8>. Are classified into groups.

As illustrated in FIG. 10, the fourth address input unit 40 includes an inverter IV41 for inverting and transmitting the address signal ADD <11> in response to the input enable signal XAEB, and the input enable signal ( A NAND that receives a latch 400 for latching an output signal of the inverter IV41 in response to XAEB, an inverted signal of the input enable signal XAEB, and an output signal of the latch 400 and performs an AND logic operation. The gate ND40, the output signal of the NAND gate ND40, and the inverted signal of the second test signal TM2 are input to perform an AND logic operation to output a subword line address signal XADD <11>. It consists of a NAND gate ND41. When the second test signal TM2 of the high level is input, the second address input unit 30 generates the subword line address signal XADD <11> enabled to the high level.

As illustrated in FIG. 11, the fifth address input unit 42 includes an inverter IV46 for inverting and transmitting the address signals ADD <12:13> in response to the input enable signal XAEB, and input enable. In response to the signal XAEB, a latch 420 for latching the output signal of the inverter IV46, an inverted signal of the input enable signal XAEB, and an output signal of the latch 420 are input to perform an AND operation. The NAND gate ND42 and the buffer unit 422 for buffering the test mode enable signal TMEN in response to the test mode enable signal TMEN, and the outputs of the NAND gate ND42 and the buffer unit 22. The NAND gate ND43 receives a signal and performs a negative logic product to output a subword line address signal XADD <12:13>. When the high level test mode enable signal TMEN is input, the fifth address input unit 42 decodes the subword line address signal XADD <11:13> to decode the subword line signals SWL <of the first group. 1: 4>) and the second group of subword line signals SWL <5: 8> are selectively enabled.

The second decoder 34 is implemented by a general decoder circuit to decode the subword line address signals XADD <11:13> to generate subword line signals SWL <1: 8> which are selectively enabled. . For example, when the subword line address signal XADD <11> is high level and the subword line address signal XADD <12:13> is 'low level and low level', respectively, the sub group of the first group In a state where the word line signal SWL <1> and the sub word line signal SWL <5> of the second group are enabled at a high level, and the subword line address signal XADD <11> is at a high level. When the subword line address signals XADD <12:13> are 'low level and high level', respectively, the first group of subword line signals SWL <2> and the second group of subword line signals SWL < 6>) can be enabled to a high level.

The operation of the refresh characteristic test circuit configured as described above will be described, but the description will be made by dividing the selection signal MATSEL into a high level and a low level.

When the selection signal MATSEL is applied at a high level, the operation of the refresh characteristic test circuit is as follows.

First, the test signal generator 1 receives the selection signal MATSEL and the test mode enable signal TMEN to generate the first test signal TM1 and the second test signal TM2. When the test mode enable signal TMEN is applied at the high level for the refresh characteristic test and the bank active signal BACTB transitions to the low level, the output signal of the logic unit 10 becomes high level, and the buffer unit 11 The first control signal S1B output from the signal becomes low level, and the second control signal S2 becomes high level. At this time, since the transfer gate T11 is turned on by the high level selection signal MATSEL, the first test signal TM1 becomes low and the second test signal TM2 becomes high.

Next, the block signal generator 2 receives the address signals ADD <1: 5> in response to the first test signal TM1 and generates the block address signals XADD <1: 5>. Since the first test signal TM1 is at the low level, the first address input unit 20 transmits the address signal ADD <1: 5> to the block address signal XADD <1: 5>, and the first decoder ( 22 generates a block signal MAT <1:32> that is selectively enabled at a high level in response to the address signal ADD <1: 5>. In this case, the number of enabled block signals MAT <1:32> may be variously set according to an embodiment. For example, when only the block signal MAT <1> is enabled at a high level, a first block (not shown) is selected.

Next, the main word line signal generator 3 receives the address signal ADD <6:10> in response to the second test signal TM2 and receives the main word line signals MWL <1:32>. Create Since the second test signal TM2 is at the high level, the second address input unit 30 generates the main word line address signal XADD <6: 9>, all of which is enabled at the high level, and the third address input unit 32. ) Generates the main word line address signal XADD <10> enabled to a high level. Since the main word line address signals XADD <6:10> are all at the high level, the second decoder 34 generates the main word line signals MWL <1:32> enabled at the high level. As described above, when only the block signal MAT <1> is enabled at a high level and the first block is selected, all of the main word line signals MWL <1:32> included in the first block are enabled. do.

Next, the subword line signal generator 4 generates the subword line address signal XADD <11:13> in response to the second test signal TM2 and the test mode enable signal TMEN. Since the second test signal TM2 is at the high level, the fourth address input unit 40 generates the subword line address signal XADD <11> enabled at the high level. On the other hand, the fifth address input unit 42 transmits the address signal ADD <12:13> to the subword line address signal XADD <12:13> by the high level test mode enable signal TMEN. .

The second decoder 34 receives the high level subword line address signal XADD <11> and receives the first group and the subword line signals including the subword line signals SWL <1: 4>. Selects the second group including SWL <5: 8>, and responds to the address signal ADD <12:13> and the subword line signals SWL <1: 4> and the second group of the first group; The signal to be enabled among the subword line signals SWL <5: 8> of the group is determined and output. For example, when the address signals ADD <12:13> are 'low level' and 'low level', the first group of subword line signals SWL <1> and the second group of subword line signals, respectively. When SWL <5> is enabled and generated at a high level, and the address signals ADD <12:13> are 'low level and high level', respectively, the first group of subword line signals SWL <2 &Quot;) and the second group of subword line signals SWL <6> are generated at a high level. As in the above-described example, when all of the main word line signals MWL <1:32> included in the first block are enabled, the sub included in each of the main word line signals MWL <1:32> may be used. The word line signals SWL <1: 8> are sequentially enabled according to the address signal ADD <12:13>.

When the selection signal MATSEL is applied at a low level, the operation of the refresh characteristic test circuit is as follows.

First, the test signal generator 1 receives the selection signal MATSEL and the test mode enable signal TMEN to generate the first test signal TM1 and the second test signal TM2. When the test mode enable signal TMEN is applied to the high level for the refresh characteristic test and the bank active signal BACTB transitions to the low level, the output signal of the logic unit 10 becomes high level, and the buffer unit 11 ), The first control signal S1B outputs the low level, and the second control signal S2 becomes the high level. At this time, since the transfer gate T10 is turned on by the low level selection signal MATSEL, the first test signal TM1 becomes high and the second test signal TM2 becomes high.

Next, the block signal generator 2 receives the address signals ADD <1: 5> in response to the first test signal TM1 and generates the block address signals XADD <1: 5>. Since the first test signal TM1 is at the high level, the first address input unit 20 generates the block address signals XADD <1: 5> which are all enabled at the high level, and the first decoder 22 blocks. The address signal XADD <1: 5> is input to generate a block signal MAT <1:32> which is all enabled at a high level. Therefore, all blocks are selected by the block signals MAT <1:32>.

Next, the main word line signal generator 3 receives the address signal ADD <6:10> in response to the second test signal TM2 and receives the main word line signals MWL <1:32>. Create Since the second test signal TM2 is at the high level, the second address input unit 30 generates the main word line address signal XADD <6: 9>, all of which is enabled at the high level, and the third address input unit 32. ) Generates the main word line address signal XADD <10> enabled to a high level. Since the main word line address signals XADD <6:10> are all at the high level, the second decoder 34 generates the main word line signals MWL <1:32> enabled at the high level. As described above, since all blocks are selected, the main word line signals MWL <1:32 included in each block by the high-level enabled main word line signals MWL <1:32>. >) Are all enabled.

Next, the subword line signal generator 4 generates the subword line address signal XADD <11:13> in response to the second test signal TM2 and the test mode enable signal TMEN. Since the second test signal TM2 is at the high level, the fourth address input unit 40 generates the subword line address signal XADD <11> enabled at the high level. Meanwhile, the fifth address input unit 42 transmits the address signal ADD <12:13> to the subword line address signal XADD <12:13> by the high level test mode enable signal TMEN. .

The second decoder 34 receives the high level subword line address signal XADD <11> and receives the first group and the subword line signals including the subword line signals SWL <1: 4>. Selects the second group including SWL <5: 8>, and responds to the address signal ADD <12:13> and the subword line signals SWL <1: 4> and the second group of the first group; The signal to be enabled among the subword line signals SWL <5: 8> of the group is determined and output. For example, when the address signals ADD <12:13> are 'low level' and 'low level', the first group of subword line signals SWL <1> and the second group of subword line signals, respectively. When SWL <5> is enabled and generated at a high level, and the address signals ADD <12:13> are 'low level and high level', respectively, the first group of subword line signals SWL <2 &Quot;) and the second group of subword line signals SWL <6> are generated at a high level. As described above, when all of the main word line signals MWL <1:32> included in each cell block are enabled, the subwords included in each of the main word line signals MWL <1:32> are enabled. The line signals SWL <1: 8> are sequentially enabled according to the address signal ADD <12:13>.

As described above, the refresh characteristic test circuit according to the present exemplary embodiment may select and enable two subword lines among the eight subword lines included in the main word line. Therefore, by using the refresh characteristic test circuit of the present embodiment, two subword lines are selected and enabled, and data stored in the remaining subword lines is read to see whether a refresh fail occurs due to leakage current due to the adjacent / passing gate effect. You can check whether it is.

In addition, the refresh characteristic test circuit according to the present exemplary embodiment may selectively perform a refresh characteristic test on all or some blocks by the selection signal MATSEL.

In addition, the refresh characteristic test circuit according to the present exemplary embodiment may test the refresh characteristic of a memory cell in which a defective cell is generated and replaced with a redundant cell. In the above-described embodiment, when the redundancy cell RED is replaced with the redundancy cell and the redundancy signal RED transitions to a high level, the address signal ADD <10> is transmitted to the main word line address signal XADD <10>. Accordingly, the level of the main word line address signal XADD <10> is adjusted according to the address signal ADD <10>, and accordingly, the main word line signals MWL <1: generated by the second decoder 34 are adjusted. The refresh characteristics can be tested for memory cells that have been replaced with redundancy cells by adjusting the enable of.

1 illustrates a cell array of a semiconductor device having a recess gate structure.

2 is a diagram illustrating a configuration of a refresh characteristic test circuit according to an exemplary embodiment of the present invention.

3 is a circuit diagram of a test signal generator included in FIG. 2.

4 is a block diagram illustrating a configuration of a block signal generation unit included in FIG. 2.

FIG. 5 is a circuit diagram of a first address input unit included in FIG. 4.

6 is a block diagram illustrating a configuration of a main word line signal generator included in FIG. 2.

FIG. 7 is a circuit diagram of a second address input unit included in FIG. 6.

FIG. 8 is a circuit diagram of the third address input unit included in FIG. 6.

FIG. 9 is a block diagram illustrating a configuration of a subword line signal generator included in FIG. 2.

FIG. 10 is a circuit diagram of a fourth address input unit included in FIG. 9.

FIG. 11 is a circuit diagram of a fifth address input unit included in FIG. 6.

<Description of the symbols for the main parts of the drawings>

1: test signal generator 2: block signal generator

20: first address input unit 22: first decoder

3: main word line signal generation unit 30: second address input unit

32: third address input unit 34: second decoder

4: subword line signal generation unit 40: fourth address input unit

42: fifth address input unit 44: third decoder

Claims (24)

A test signal generator configured to receive the selection signal and the test mode enable signal and generate first and second test signals; A block signal generation unit receiving the first test signal and at least one first address signal and generating a plurality of block signals; A main word line signal generator configured to receive the second test signal and at least one second address signal and generate a plurality of main word line signals; And And a subword line signal generator configured to receive the test mode enable signal, the second test signal, and a plurality of third address signals to generate a plurality of subword line signals. The refresh characteristic test circuit of claim 1, wherein the first and second test signals are selectively enabled in response to the selection signal in a state in which the test mode enable signal is enabled. The method of claim 1, wherein the test signal generation unit A logic unit configured to receive the test mode enable signal and the bank active signal and perform a logic operation; A buffer unit for outputting first and second control signals by buffering an output signal of the logic unit; A logic element configured to receive the first control signal and the output signal of the logic unit and perform logic operation; And a transfer unit configured to selectively transfer the second control signal or the output signal of the logic element in response to the selection signal. The method of claim 3, wherein the buffer unit A first inverter for inverting an output signal of the logic unit to generate the first control signal; And And a second inverter for inverting the output signal of the first inverter to generate the second control signal. The method of claim 3, wherein the delivery unit A first transfer element transferring the second control signal in response to the selection signal; And And a second transfer element transferring an output signal of the logic element in response to the selection signal. The refresh characteristic test circuit of claim 1, wherein the block signal generation unit enables all of the plurality of block signals when the first test signal is enabled. The method of claim 1, wherein the block signal generation unit An address input unit configured to receive the first address signal and generate a block address signal in response to the first test signal; And And a decoder for decoding the block address signal to generate the plurality of block signals. The method of claim 7, wherein the address input unit A buffer that buffers and delivers the first address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the first test signal and perform logic operation. 2. The refresh characteristic test circuit of claim 1, wherein the main word line signal generation unit enables all of the plurality of main word line signals when the second test signal is enabled. The method of claim 1, wherein the main word line signal generation unit An address input unit configured to receive the second address signal in response to the second test signal and generate a main word line address signal; And And a decoder for decoding the main word line address signal to generate the plurality of main word line signals. The method of claim 10, wherein the address input unit A buffer that buffers and delivers the second address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the second test signal and perform logic operation. The method of claim 10, wherein the address input unit A buffer that buffers and delivers the second address signal in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; A second logic element configured to receive an inverted signal of the second test signal and the redundancy signal and perform a logic operation; And And a third logic element configured to receive the output signals of the first logic element and the second logic element and perform a logic operation. The method of claim 1, wherein the subword line signal generator is configured to group the plurality of subword line signals according to the third address signal when the test mode enable signal and the second test signal are enabled. The refresh characteristic test circuit classified into and sequentially enabling the subword lines included in the group. The method of claim 1, wherein the subword line signal generator A first address input unit configured to receive a portion of the third address signals in response to the second test signal to generate a first subword line address; A second address input unit configured to receive a remaining address among the third address signals and generate a second subword line address in response to the test mode enable signal; And And a decoder which decodes the first and second subword line addresses to generate the plurality of subword line signals. 15. The method of claim 14, wherein the first address input unit A buffer that buffers and transfers some of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to perform a logical operation by receiving an inverted signal of the input enable signal and an output signal of the latch; And And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the second test signal and perform logic operation. 15. The method of claim 14, wherein the second address input unit A buffer that buffers and delivers the remaining addresses of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; A buffer unit configured to buffer the test mode enable signal in response to the test mode enable signal; And And a second logic element configured to receive an output signal of the first logic element and an output signal of the buffer unit, and perform a logic operation. 15. The method of claim 14, wherein the decoder classifies the plurality of subword line signals into at least two groups when the first subword line address is enabled, and subword lines included in the group to the second subword. A refresh characteristic test circuit which enables sequentially in response to a word line address. A test signal generation unit configured to generate first and second test signals that are selectively enabled in response to the selection signal while the test mode enable signal is enabled; A block signal generation unit configured to receive the first test signal and at least one first address signal and generate a plurality of block signals, wherein the plurality of block signals are all enabled when the first test signal is enabled; Generates a plurality of main word line signals by receiving the second test signal and at least one second address signal, wherein the plurality of main word line signals are all enabled when the second test signal is enabled A line signal generator; And The test mode enable signal, the second test signal, and the plurality of third address signals are input to generate a plurality of subword line signals, and the test mode enable signal and the second test signal are enabled when the And a subword line signal generator configured to classify the plurality of subword line signals into at least two groups according to a third address signal and to sequentially enable the subword lines included in the group. 19. The apparatus of claim 18, wherein the test signal generator A logic unit configured to receive the test mode enable signal and the bank active signal and perform a logic operation; A buffer unit for outputting first and second control signals by buffering an output signal of the logic unit; A logic element configured to receive the first control signal and the output signal of the logic unit and perform logic operation; And a transfer unit configured to selectively transfer the second control signal or the output signal of the logic element in response to the selection signal. 19. The apparatus of claim 18, wherein the main word line signal generator An address input unit configured to receive the second address signal in response to the second test signal and generate a main word line address signal; And And a decoder for decoding the main word line address signal to generate the plurality of main word line signals. 19. The apparatus of claim 18, wherein the subword line signal generator A first address input unit configured to receive a portion of the third address signal in response to the second test signal and generate a first subword line address; A second address input unit configured to receive a remaining address among the third address signals and generate a second subword line address in response to the test mode enable signal; And And a decoder which decodes the first and second subword line addresses to generate the plurality of subword line signals. The method of claim 21, wherein the first address input unit A buffer that buffers and transfers some of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and an inverted signal of the second test signal and perform logic operation. The method of claim 21, wherein the second address input unit A buffer that buffers and delivers the remaining addresses of the third address signals in response to an input enable signal; A latch for latching an output signal of the buffer in response to the input enable signal; A first logic element configured to receive an inverted signal of the input enable signal and an output signal of the latch and perform a logic operation; A buffer unit configured to buffer the test mode enable signal in response to the test mode enable signal; And And a second logic element configured to receive an output signal of the first logic element and an output signal of the buffer unit, and perform a logic operation. 22. The method of claim 21, wherein the decoder classifies the plurality of subword line signals into at least two groups when the first subword line address is enabled, and classifies the subword lines included in the group into the first subword line. A refresh characteristic test circuit which enables sequentially in response to a word line address.

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