KR20090124101A - Non volatile memory device and method of operating the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and an operation method thereof are provided to improve reliability of a data reading process by offering the other read voltage according to a program state of a memory cell as well as temperature. CONSTITUTION: A memory cell array(210) comprises cell strings consisting of a plurality of memory cells. A page buffer part(220) is connected to a bit line. The page buffer part comprises page buffer circuits for reading stored data through the bit line. A Y decoder offers a data input/output path of the page buffer circuits. An X decoder(240) offers a path of supplying voltage for an operation by selecting word lines of the memory cell array. A voltage offer part(250) generates operating voltage offered to the word line by the X decoder. A controller controls the voltage offer part, the X decoder, the page buffer part and the Y decoder.

Description

Nonvolatile memory device and method of operation

The present invention relates to an apparatus for generating a read voltage of a nonvolatile memory device, and more particularly to a nonvolatile memory device capable of separately providing a read voltage changed according to a temperature according to a program state of a memory cell, and a method of operating the same.

A flash memory device, which is one in a nonvolatile memory device, is generally configured to include a plurality of strings in which a plurality of memory cells are connected in series. Such flash memory devices are widely used in various semiconductor devices such as notebooks, personal digital assistants (PDAs), mobile electronic devices such as mobile phones, computer bios, printers, and universal serial bus (USB) drivers.

A memory cell array of a typical flash memory device has a structure in which memory cells are serially connected between a bit line (BL) and a cell source line (CSL). In addition, the NAND flash memory device may be referred to as a drain select line (DSL) and a source selective line (SSL) to electrically connect the memory cell to the bit line BL and the cell source line CSL. Two transistors are connected.

In addition, in order to increase the capacity of data that can be stored in nonvolatile memory devices, a number of products using multi-level cells (MLCs) capable of storing multiple bit data in one memory cell are increasing. A nonvolatile memory device employing a multi-level cell has increased capacity because one bit of data can be stored in a memory cell. However, if one memory cell is programmed, the threshold voltage distribution is divided into several programs. Increased time to do Therefore, various techniques have been developed to reduce the program time.

On the other hand, the memory cell constituting the nonvolatile memory device has a characteristic that the threshold voltage is changed with respect to temperature. Therefore, the threshold voltage of the memory cell may vary greatly due to a temperature difference when the program is executed and when the stored data is read. Therefore, when reading data with the set read voltage, there is a problem that incorrect data may be read.

Accordingly, a technical problem of the present invention is to provide a read voltage generator for generating a read voltage corresponding to an ambient temperature according to a program state of a memory cell, thereby providing a read voltage according to the program state of the memory cell as well as the temperature. And a method of operation thereof.

Nonvolatile memory device according to a feature of the present invention,

A plurality of read voltage generators for generating different read voltages according to the program state of the logical page of the word line to which the memory cells are connected, the plurality of read voltage generators are controlled to vary the degree of output voltage changes according to temperature A voltage generator; And a controller configured to selectively enable the plurality of read voltage generators according to a program state of the memory cell to control the output of the data read voltage.

The voltage generator is configured to store n bits of information so that when the word line includes n pages logically, n read voltage generators generate read voltages according to logical page programs. Characterized in that it comprises a.

The n read voltage generators are configured such that a change amount in which the read voltages output from the n read voltage generators is changed according to the ambient temperature is different.

Method of operating a nonvolatile memory device according to a feature of the present invention,

Determining a program state of a selected word line according to a data read command; Generating a read voltage set according to the determination result to be changed according to a temperature variable set differently according to a voltage level of each read voltage; And reading data by using the generated read voltage.

The determining of the program state of the selected word line may include checking a page in which a program is progressed among logical pages included in the word line.

Different read voltages are set for each of the logical pages.

The degree of change according to the ambient temperature is set differently according to each read voltage level.

As described above, the nonvolatile memory device and the method of operating the same according to the present invention have different apparatuses for generating the read voltage according to the program state in order to compensate for the influence of the ambient temperature according to the program state of the memory cell. In addition, by setting the influence of each read voltage generating device differently from the ambient temperature, the read voltage is provided differently according to the program state of the memory cell as well as the temperature, thereby increasing the reliability of data reading.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 illustrates a shift in threshold voltage distribution of a multi-level cell.

Referring to FIG. 1, it is possible to check the shift of the threshold voltage distribution as a program progresses in a multi-level cell (MLC) capable of storing 4-bit information.

That is, when the LSB (Least Significant Bit) program for programming the first bit information is executed, the threshold voltage distribution is divided into two. When the CSB program for programming the second bit information is executed, the two threshold voltage distributions are changed to four.

The MSB (Most Significant Bit) program for programming the third bit information changes the four threshold voltage distributions to eight, and the eight MSV programs for the fourth bit information changes the eight threshold voltage distributions to sixteen. .

As the program proceeds as described above, the number of threshold voltage distributions to be divided increases, thereby narrowing the width between the threshold voltages, thereby narrowing the margin for reading data.

In addition, the threshold voltage of the memory cell is changed according to the ambient temperature according to the characteristics of the memory cell. To compensate for this, the data read voltage that is changed according to the ambient temperature is used.

2A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2A, the nonvolatile memory device 200 may include a memory cell array 210, a page buffer unit 220, a Y decoder 230, an X decoder 240, a voltage provider 250, and a controller 260. ).

In the memory cell array 210, memory cells for data storage are connected by word lines and bit lines. The memory cell of the nonvolatile memory device 200 according to an embodiment of the present invention is a multi-level cell capable of storing 4-bit information.

The page buffer unit 220 is connected to a bit line and includes page buffer circuits for storing data to be programmed and transferring the data to the bit line to be programmed in a selected memory cell, or reading and storing data stored through the bit line.

The Y decoder 230 provides a data input / output path of the page buffer circuits, and the X decoder 240 selects word lines of the memory cell array 210 to provide a path for providing a voltage for an operation.

The voltage provider 250 generates an operating voltage provided to the word line by the X decoder 240. In this case, the voltage providing unit 250 generates and provides a read voltage outputting different read voltages according to the ambient temperature and the program degree of the selected word line. The control unit 260 is where the operation control of the voltage providing unit 250 is performed.

The controller 260 controls not only the voltage providing unit 250 but also the X decoder 240, the page buffer unit 220, and the Y decoder 230 to program data in the memory cell array 210 and store the stored data. To be read.

An apparatus for providing a read voltage of the voltage provider 250 is described in detail as follows.

FIG. 2B is a partial block diagram of the voltage provider of FIG. 2A.

In particular, FIG. 2B illustrates some circuits between the memory cell array 210, the page buffer unit 220, the X decoder 240, and the voltage generator 250 of the nonvolatile memory device 200 according to an embodiment of the present invention. Indicates.

2B, the memory cell array 210 includes cell strings composed of a plurality of memory cells. In the cell string, a plurality of memory cells are connected in series between a drain select transistor (DST) and a source select transistor (SST).

The drain terminal of the drain select transistor DST of the cell string is connected to the bit line BL.

The bit lines connected to the cell strings are divided into an even bit line and an odd bit line, and a pair of bit lines formed of one even bit line and one odd bit line is a page buffer circuit of the page buffer unit 220. Connected with.

The page buffer circuit includes first to third NMOS transistors N1 to N3 and a latch unit. The first NMOS transistor N1 is connected between the even bit line BLe and the node SO1, and the second NMOS transistor N2 is connected between the odd bit line BLO and the node SO1.

An even bit line select signal Select BLe (SBLe) is input to the gate of the first NMOS transistor N1, and an odd bit line select signal Select BLo SBLo is input to the gate of the second NMOS transistor N2.

The third NMOS transistor N3 is connected between the node SO1 and the latch unit, and a sensing control signal PBSENSE for sensing a bit line voltage is input to a gate of the third NMOS transistor N3. The latch unit latches data to be programmed or latches data to be read.

Gates of the drain select transistors DST of the memory cell array 210 are commonly connected to a drain select line DSL, and gates of the source select transistors SST are source select line SSL. Is connected in common. Each of the memory cells is connected to word lines.

The X decoder 240 includes the drain select line DSL, the source select line SSL, the word lines WL, and the global drain select line GDSL and the global source select of the voltage provider 250. And high voltage switches connected between a global source select line (GSSL) and a global word line (GWL) to perform a switching operation by a control signal.

The voltage providing unit 250 includes first to fourth read voltage generators 251 to 254 for reading data. The first read voltage generator 251 changes the read voltage at the time of reading the page in which the first bit information is programmed according to the ambient temperature and outputs the read voltage as the first read voltage VREAD1.

The second read voltage generator 252 changes the read voltage at the time of reading the page in which the second bit information is programmed according to the ambient temperature and outputs the read voltage as the second read voltage VREAD2. The third read voltage generator 253 changes the read voltage when reading the page in which the third bit information is programmed, according to the ambient temperature, and outputs the read voltage as the third read voltage VREAD3.

The fourth read voltage generator 254 changes the read voltage at the time of reading the page in which the fourth bit information is programmed according to the ambient temperature, and outputs the read voltage as the fourth read voltage VREAD4.

Referring to a page programmed with the first to fourth bit information, a multi-level cell in which a memory cell of the nonvolatile memory device 200 programs 4-bit information according to an embodiment of the present invention will be described. Therefore, one word line includes four pages logically.

That is, each word line is composed of first to fourth pages for the first to fourth bit information programs. The first to fourth read voltage generators 251 to 254 output the read voltages to the word lines through which the program is performed on the first to fourth pages, respectively.

The first to fourth read voltage generators 251 to 254 are circuits for outputting a read voltage which is changed according to an ambient temperature, and each of the first to fourth read voltage generators 251 to 254 is configured such that a change rate according to temperature is differently applied according to a program degree.

Representatively, a circuit configuration of the first read voltage generator 251 will be described below.

FIG. 2C is a circuit diagram of the first read voltage generator of FIG. 2B.

Referring to FIG. 2C, the first read voltage generator 251 may include the first to third comparators COM1 to COM3, the first and second resistors R1 and R2, the variable resistors Rf, Rg, and Rt. The first NMOS transistor N1 is included.

The first and second comparators COM1 and COM2 function as buffers for directly outputting an input voltage. To this end, the first comparator COM1 has a voltage VBG input to the non-inverting terminal + and the inverting terminal − is connected to the node K1 which is an output terminal. In the second comparator COM2, the voltage of the node K2 is input to the non-inverting terminal +, and the inverting terminal − is connected to the node K3, which is an output node.

The variable resistor Rf and the variable resistor Rg are connected in series between the node K1 and the ground node. The variable resistor Rf is a variable resistor for dividing and outputting the voltage VBG to a reference voltage level, and the variable resistor Rg is a variable voltage for dividing and outputting the voltage VBG at the read voltage VRD level. .

The first NMOS transistor N1 and the variable resistor Rt are connected in series between a power supply node and a ground node. The reference voltage output by the variable resistor Rf is input to the gate of the first NMOS transistor N1. In addition, the variable resistor Rt is a variable resistor for distributing and outputting a power supply voltage applied when the first NMOS transistor N1 is turned on according to a temperature.

The voltage of the node K2, which is changed according to the ambient temperature, is input to the non-inverting terminal + of the second comparator COM2 and output to the node K3.

The first resistor R1 is connected between the node K3 and the node K4 connected to the inverting terminal (−) of the third comparator COM3. The second resistor R2 is connected between the inverting terminal (−) of the third comparator COM3 and the node K5 which is the output terminal.

The read voltage VRD output by the variable resistor Rg is input to the non-inverting terminal + of the third comparator COM3. The first read voltage VREAD1 is output through the node K5, which is an output terminal of the third comparator COM3.

The variable resistor Rg is set to output a read voltage VRD corresponding to the first read voltage VREAD level. The variable resistors Rg of the second to fourth read voltage generators 252 to 254 are set to output read voltages corresponding to levels corresponding to respective page programs.

In addition, the variable resistor Rt causes a voltage to be changed according to a temperature. The variable resistor Rt is different because the degree of influence of temperature varies depending on the voltage level of the second to fourth read voltages VREAD2 to VREAD4. Is set.

The first read voltage VREAD1 output through the node K5 becomes a voltage level according to the following equation.

As described above, since the state of the read voltage, which is differently output according to the program state of the memory cell, varies according to the temperature, the read voltage is adjusted so that each voltage is affected differently according to the temperature.

Meanwhile, FIG. 2C is a circuit capable of generating a read voltage that changes with temperature, and may be set as various temperature compensation circuits that output a voltage that changes with temperature. However, by setting only the variable value according to the temperature according to each voltage level can be implemented to be affected differently depending on the temperature for each read voltage.

The following is a data reading method of the nonvolatile memory device 200 described above.

3 is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the controller 260 of the nonvolatile memory device 200 receives a data read command and address information for reading data (S301).

The controller 260 checks the program state of the word line WL selected for data reading (S303). The method for checking the program state may be implemented in various ways, including a method for checking the program state using a flag cell.

According to an embodiment of the present disclosure, the controller 260 checks which page of the first to fourth pages the selected word line is programmed. The controller 260 enables one of the first to fourth read voltage generators 251 to 254 according to the checked program state (S305). That is, if the selected word line is programmed to the first page (the LSB program state of FIG. 1), the first read voltage generator 251 is enabled.

One of the enabled first to fourth read voltage generators 251 to 254 generates a voltage VBG and generates and outputs first to fourth read voltages VREAD1 to VREAD4 that are changed according to temperature. (S307).

One of the generated first to fourth read voltages VREAD1 to VREAD4 is applied to the selected word line, and data reading is performed (S309). The data read process is performed according to a data read process of a nonvolatile memory device in which a voltage for reading is provided to a selected word line and a pass voltage is applied to the remaining word lines.

As described above, when the read voltage is changed and input according to the programmed degree of the memory cell connected to the word line, a read voltage generator configured to generate respective read voltages is configured differently, and each read voltage generator is changed according to temperature. Is set differently. Accordingly, an error in reading data may be reduced by applying a read voltage that is controlled not only for temperature but also for a programmed state of memory cells.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 illustrates a shift in threshold voltage distribution of a multi-level cell.

2A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2B is a partial block diagram of the voltage provider of FIG. 2A.

FIG. 2C is a circuit diagram of the first read voltage generator of FIG. 2B.

3 is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

200: nonvolatile memory device 210: memory cell array

220: page buffer unit 230: Y decoder

240: X decoder 250: voltage providing unit

260 control unit

Claims (7)

A plurality of read voltage generators for generating different read voltages according to the program state of the logical page of the word line to which the memory cells are connected, the plurality of read voltage generators are controlled to vary the degree of output voltage changes according to temperature A voltage generator; And A controller configured to selectively enable the plurality of read voltage generators according to a program state of the memory cell to control an output of the data read voltage Nonvolatile memory device comprising a. The method of claim 1, The voltage generator, And n read voltage generators for storing n bits of information so that when the word line logically includes n pages, a read voltage generator generates a read voltage according to a logical page program degree. Nonvolatile memory device. The method of claim 2, The n read voltage generators are non-volatile memory device, characterized in that the amount of change that each of the output read voltage changes according to the ambient temperature is set differently. Determining a program state of a selected word line according to a data read command; Generating a read voltage set according to the determination result to be changed according to a temperature variable set differently according to a voltage level of each read voltage; And Reading data by using the generated read voltage Method of operating a nonvolatile memory device comprising a. The method of claim 4, wherein The determining of the program state of the selected word line may include identifying a page in which a program is progressed among logical pages included in the word line. The method of claim 5, And a different read voltage is set for each of the logical pages. The method of claim 6, A method of operating a nonvolatile memory device, characterized in that the degree of change according to the ambient temperature is set differently according to each read voltage level.

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