KR20090111134A - Graphic accelerator integrating 2D and 3D, Application process comprising the same graphic accelerator, and graphic accelerating method in same application - Google Patents

Abstract

PURPOSE: A two dimensional and three dimensional graphic accelerator, an application processor including the accelerator and a graphic accelerator method of an application processor are provided to improve the availability of a memory share and reduce the area of a chip design. CONSTITUTION: A two dimensional and three dimensional graphic accelerator, an application processor including the accelerator include the two dimensional and three dimensional graphic accelerator, a command processor and a register. A two dimensional and three dimensional graphic accelerator includes a geometry engine and a rendering engine(140). The pre-processor geometry engine and post processing rendering engine are formed by a pipeline.

Description

Graphic accelerator integrating 2D and 3D, application process comprising the same graphic accelerator, and graphic accelerating method in same application}

The present invention relates to a graphics accelerator, and more particularly, to a 2D and 3D integrated graphics accelerator capable of performing 2D and 3D graphics processing integrally.

In general, 3D graphics processing is the most essential part of building a multimedia environment, and requires a high performance dedicated 3D graphics accelerator such as OpneGL / ES to support more realistic 3D images.

3D graphics accelerators are largely divided into geometry processing and rendering. Geometry processing mainly refers to a process of converting an object of a 3D coordinate system according to a viewpoint and projecting it into a 2D coordinate system, and rendering refers to a process of determining a color value in an image of a 2D coordinate system and storing it in a frame buffer. In order to increase performance, the geometry processing unit and the rendering unit are each pipelined.

After the execution of all 3D data input for one frame is finished, the color value stored in the frame buffer is sent to the display.

The 3D graphics accelerator is divided into an object order method and an image order method according to an input primitive processing order.

Object ordering method is a method of sending primitives and rendering process in order of input primitives, which is advantageous for high performance because it can pipeline the geometric process and rendering process per primitive. Accordingly, most current high performance 3D graphics accelerators employ this object ordering method.

The image ordering method is a method of processing primitives belonging to a corresponding position according to the position order of an image rather than sequentially processing input primitives, which is advantageous in terms of cost reduction rather than high performance.

Primitives include points, lines, and polygons, and in most common applications, polyhedrons make up the majority of primitives, and hardware accelerators are configured to process these polyhedrons at high speed.

On the other hand, vector graphics accelerators such as OpenVG, which are mainly used for 2D graphics processing, arrange lines or shapes in a given two-dimensional or three-dimensional space and create digital images through a series of instructions or mathematical expressions.

Currently, the 2D vector graphics accelerator is embedded separately from the 3D graphics accelerator in a mobile communication terminal and is driven using contents that are completely different from those used in the 3D graphics accelerator.

However, when looking at the pipelines of 2D vector graphics accelerators and 3D graphics accelerators, modules that perform the same functions, such as modules used in preprocessing sections and modules that fill the final scan line with color in the pixel buffer, are commonly included. It can be seen that. Accordingly, in the conventional mobile communication terminal including each graphic accelerator, the chip design area of the processor (GPU) for graphic acceleration is wide, and waste of memory, cache, frame buffer, etc. due to the use of each controller and content is eliminated. There was a serious problem.

The problem to be solved by the present invention is to minimize the design area by combining the geometry processing section that the 2D (Vector) graphics accelerator and the 3D graphics accelerator use the same in one processor, and find and combine the same pipeline in the rendering process. In addition, 2D and 3D integrated graphics accelerators that can share the final frame buffer, reduce memory waste, and integrate and process both content through a unified instruction processor, the application processor including the accelerator and the application processor It is to provide a graphic acceleration method.

In other words, the object of the present invention is to combine the arithmetic, memory and instruction controllers used in each graphics accelerator into one, and to generate the final pixel, for the purpose of operating the binary graphics acceleration processor in one integrated application processor. The present invention aims to present a structure that can integrally operate triangle setup, projection processing, and realization that handle the same operation among rendering parts.

In order to achieve the above object, the present invention is a geometry (Geometry) engine which is a preprocessing unit formed in a three-dimensional pipe (Pipe-Line) structure; And a rendering engine which is a post-processing unit formed of a three-dimensional pipeline structure and having a gradient module and a path generation module for 2D (Vector) graphics acceleration. Features 2D and 3D integrated graphics accelerators.

In the present invention, the geometry engine includes a World Transform module, a Lightening module, a View Transform module, a Projection Transform module, and a Clipping module. The rendering engine includes the gradient module, the pass generation module, a triangle setup module, a span processing module, and a realization module, wherein the view transformation of the geometry engine is performed. A transform module, the projection transform module and the clipping module, the triangle setup module of the rendering engine, the span processing module and the realization module may be used together for the 2D graphics acceleration.

The rendering engine may include a mapping module, a blending module, and a rasterization module commonly used for the 2D and 3D graphics processing as the realization module.

The mapping module may include a texture mapping unit and a light mapping unit that perform texture and light processing, and the gradient module may include a bitmap unit and a straight and circular gradient (eg, a bitmap type graphic processing). And a linear / radical portion for color change processing, and the blending module includes a texture blending portion, an image blending portion, and an alpha blending portion for performing texture, image, and alpha blending, and the raster The riser module may include an alpha tester and a depth tester for testing an alpha value and a Z-depth value, and an image interpolation part for 2D vector image interpolation.

In the present invention, when processing the 3D graphics, the texture and light mapping unit of the mapping module, the texture blending unit of the blending module, the alpha test unit and depth test unit of the rasterizer module, the image of the blending module After storing the pixel data generated through the blending and alpha blending unit in the pixel cache, and finally storing the pixel data in the frame buffer, and processing the 2D graphics, the light mapping unit is not used, the depth test The image interpolation unit may be used instead of the unit, and the image blending unit may perform the image blending in conjunction with the image interpolation unit and the gradient module unit.

Meanwhile, the pass generation module may generate 2D pass data for solids, images, and patterns for each module in response to the setup of the triangle module of the 3D graphics accelerator. In addition, the 2D and 3D integrated graphics accelerator may further include a register set for storing instructions for 2D and 3D graphics acceleration.

The present invention also comprises an instruction processing unit for processing instructions and data for 2D and 3D graphics acceleration to achieve the above object; A register set for storing instructions for accelerating the 2D and 3D graphics; And a 2D and 3D integrated graphics accelerator configured to receive the command of the command processor to integrally process the 2D and 3D graphics acceleration.

In the present invention, the command processing unit is a command core that is a set of instructions delivered from an advanced high-performance bus (AHB) slave, and a command parser that parses the commands. The register set may include an S-register that stores a state of whether 2D or 3D graphics is accelerated.

The 2D and 3D integrated graphics accelerators may further include modules for 2D graphics processing used only for the 2D graphics acceleration, based on the 3D graphics accelerator as described above. The 2D and 3D integrated graphics accelerator performs 3D or 2D graphics acceleration according to the state information stored in the S register in the register set, and in the case of the 2D graphics acceleration, the same functions as the 3D graphics acceleration are the 3D graphics accelerator. Inner modules can be processed together, and other functions can be processed using the 2D processing module.

The 2D processing modules may include a gradient module and a path generation module as described above, and if the 2D and 3D integrated graphics accelerators include a Gouraud Shading module In this case, the gradient may be performed during the 2D graphic acceleration by using the go-loud shading module.

Meanwhile, in the present invention, the graphic acceleration integrated application processor may store the same data in the same cache and use the 2D and 3D graphics acceleration processes.

Furthermore, in order to achieve the above object, the present invention comprises the steps of checking the idle state of the hardware (H / W) processor; Initializing the 2D and 3D integrated graphics accelerator to a 2D or 3D graphics acceleration mode; Performing 2D or 3D graphics acceleration; And terminating the 2D and 3D integrated graphics accelerators.

The method may further include determining a type of graphic to be executed in the 2D and 3D integrated graphic accelerators before the initializing step, wherein the performing of the acceleration comprises: dirty checking a cache used to execute the 2D or 3D graphic; Executing a geometry engine that is a preprocess of graphics processing; And executing a rendering engine that is a post-process of the graphic processing. In addition, after the initialization step, the clear operation on the frame buffer may be separately performed.

The processor may receive an instruction processor for processing instructions and data for 2D and 3D graphics acceleration, a register set for storing instructions for 2D and 3D graphics acceleration, and an instruction processor for the 2D and 3D graphics acceleration. Including the 2D and 3D integrated graphics accelerator to process, the acceleration in the acceleration step may be performed according to the command transmitted from the command processor.

In addition, the 2D and 3D integrated graphics accelerator, based on the 3D graphics accelerator, includes 2D processing modules used only for the 2D graphics acceleration, in the case of the 2D graphics acceleration, the same functions as the 3D graphics acceleration, the 3D The modules in the graphics accelerator can be processed together, and other functions can be processed using the 2D processing module.

According to the present invention, a 2D and 3D integrated graphics accelerator, an application processor including the accelerator, and a graphics acceleration method in the application processor are designed by integrating a preprocessor and a post processor to which 2D and 3D graphics processing are applied in the same manner, thereby providing a chip. It can reduce the design area and increase the utilization of memory sharing.

In addition, by changing the graphics acceleration process to a unified structure, the waste of resources in the application processor can be reduced.

On the other hand, by using a common pipeline, by storing the results of the two different content in one frame buffer, it is possible to develop the integrated content mixed with 2D graphic vector content and 3D graphic content in the future.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention; In the following description, when a component is described as being connected to another component, it may be directly connected to another component, but a third component may be interposed therebetween. In addition, in the drawings, the structure or size of each component is exaggerated for convenience and clarity of explanation, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. On the other hand, the terms used are used only for the purpose of illustrating the present invention and are not used to limit the scope of the invention described in the meaning or claims.

FIG. 1 is a block diagram illustrating the same pipe line structure of a 3D graphics accelerator and a 2D graphics accelerator, and shows a part that can be equally used for 2D vector acceleration based on the pipeline of the 3D graphics accelerator. (Two-dot chain line part of a rectangle).

Referring to FIG. 1, the 3D graphics accelerator includes a geometry engine A which is a preprocessor and a rendering engine B which is a postprocessor.

The geometry engine A includes a World Transform module 10, a Lightening module 20, a View Transform module 30, and a Projection Transform module 40. And a clipping module 50.

The world transform module 10 reorients the model vertices from model space to world space, and the lightening module 20 controls the effect of light from the light source on the vertices. By vector operation, the view transform module 30 converts the world space into a view space centered on the view of the camera. The projection transform module 40 converts the view space into the projection space with the information about the depth, and the clipping module 50 removes the vertices of the portions that are not visible on the screen.

The rendering engine B includes a triangle setup module 60, a span processing module 70, and a realization module 80. Meanwhile, the 2D and 3D integrated graphics accelerator of the present invention further includes a gradient module and a path generation module for only 2D graphics as the rendering engine B, which will be described in more detail with reference to FIG. 3.

Triangle setup module 60 sets up the basic coordinate values of each object. That is, the area and the delta value are calculated based on the three-dimensional coordinate information read from the memory. The span processing module 70 calculates the slope and length of the object generated through the triangle setup, and the realization module 80 interpolates and outputs the color information of the final object and the average value of each object. On the other hand, such a function is referred to as a rendering process, the realization module 80 may be referred to as a rendering module, and based on it, the entire post-processing unit is referred to as a rendering engine. The result calculated and output through the realization module 80, that is, data about the final object is stored in the final frame buffer.

The view transform, projection transform, and clipping modules 30, 40, and 50 of the geometry engine A are equally applicable to the 2D vector graphics accelerator. Accordingly, other modules except for the world transform and lightening modules 10 and 20 in the geometry engine A of the 3D graphics accelerator can equally be used for 2D vector graphics acceleration.

However, the transcendental functions and matrix operations used in the geometry calculation during the preprocessing are the same as the conventional three-dimensional graphic processing, and thus detailed description thereof is omitted. As an example, the matrix operation of the 2D vector accelerator uses the same column-based matrix processor as that used in three-dimensional graphics processing. That is, as a 3x3 matrix operator, only the elements of 1,2,3,5,6,7 terms are used, and the values of 0,0,1 are used for the 9, 10, and 11 terms. As such, the matrix operation of the 2D vector accelerator can be accomplished by taking only the necessary parts of the software and setting the rest of the terms in registers as default values.

Meanwhile, each module of the rendering engine B may also be commonly used for 2D vector graphics acceleration. The rendering engine B will be described in more detail later with reference to FIG. 3.

Thus, by incorporating modules used only for 2D vector graphics acceleration on the basis of the 3D graphics accelerator, 2D and 3D integrated graphics accelerators can be realized. The modules for 2D vector graphics included in the integrated graphics accelerator also need to form a pipeline structure with the existing modules.

Meanwhile, the 2D and 3D integrated graphics accelerators may be accommodated in an application processor for graphic sharing acceleration processing, embedded in a mobile communication terminal, and managed by a software driver in charge of each process. Each of these software drivers can use the integrated frame buffer by interworking with the Embedded Graphic Library (EGL) according to the standards of OpenGL / ES and OpenVG, which are APIs corresponding to the characteristics.

As a result, the 2D and 3D integrated graphics accelerator according to the present invention can share the graphics acceleration with different characteristics to the same processor to drive the design area, and simultaneously use the frame buffer to increase the memory efficiency Can be.

2A is a block diagram of an integrated graphics acceleration application processor according to an embodiment of the present invention.

Referring to FIG. 2A, the integrated graphics acceleration application processor according to the present embodiment includes a 2D and 3D integrated graphics accelerator 100, an instruction processor 200, and a register set 300.

The 2D and 3D integrated graphics accelerator 100 includes a geometry engine 120 and a rendering engine 140. The geometry engine 120 is identical to the geometry engine 120 of FIG. 1. Meanwhile, in the case of the rendering engine 140, the rendering engine of FIG. 1 further includes modules for accelerating 2D vector graphics. The rendering engine 140 will be described in more detail with reference to FIG. 3.

The command processor 200 may include a command core 220 that executes data and instructions transmitted from an advanced high-performance bus (AHB) slave, and a command parser that parses the instructions. Command Parser, 240). The instruction processor 200 processes data and instructions for controlling the integrated graphics accelerator 100. Here, the AHB slave is a bus for high-performance signal processing connected between an ARM core and an application processor, and transfers commands and data for controlling the application processor. The received data and instructions are stored in respective registers or are transmitted to the command core 22 engine of the instruction processor 200 and parsed through the command parser 240.

The register set 300 stores instructions for accelerating 2D and 3D graphics. On the other hand, the register set 300 includes an S-register (Status Register) 320 that stores the status of whether 2D or 3D graphics acceleration of the 2D and 3D integrated graphics accelerator. Therefore, the 2D and 3D integrated graphics accelerators initialize the graphics mode to 2D or 3D graphics mode according to the graphics information stored in the S-register 320 to perform 2D vector graphics acceleration or 3D graphics acceleration.

That is, the command core 220 reads the register value for the graphics state stored in the S-register 320 and accordingly refers to the 2D vector graphics register value or the 3D graphics register values stored in the register set with reference to the integrated graphics accelerator 100. ) Performs 2D vector graphics acceleration or 3D graphics acceleration. The command core 220 refers to the S-register value until the last instruction execution for any one graphic processing.

The integrated graphics acceleration application processor of the present invention includes an integrated instruction processor 200, an S-register 320, and a 2D and 3D graphics integrated accelerator 100 to integrate 2D vector graphics acceleration and 3D graphics acceleration. Can be.

2B is a block diagram of an integrated graphics acceleration application processor according to another embodiment of the present invention.

Referring to FIG. 2B, the integrated graphics acceleration application processor of the present embodiment is similar to FIG. 2A, but has a structure in which the register set 300 is included in the 2D and 3D integrated graphics accelerator 100a. It goes without saying that register set 300 includes an S-register 320 that stores graphics state information to be executed.

Since each component or function of the present embodiment is the same as in FIG. 2A, a description thereof will be omitted.

3 is a block diagram illustrating the rendering engine of FIG. 2A in more detail.

Referring to FIG. 3, the rendering engine 140 may include a mapping module 110, a gradient module 160, a blending module 130, a path generation module 170, And a rasterization module 150. Of course, the rendering engine 140 further includes a triangle setup module and a span processing module, but illustration thereof is omitted.

The mapping module 110 includes a texture mapping unit 112 and a light mapping unit 114 that perform texture mapping and light mapping. Here, the light mapping unit 114 is not used at the time of 2D graphics acceleration. Therefore, in the case of 3D graphics acceleration, the image entered through the preprocessing unit reads the corresponding image data from the texture cache 410 and the light cache 420 and processes the mapping through the texture mapping unit 112 and the light mapping unit 114, respectively. In the case of 2D vector graphics acceleration, only texture mapping is performed.

On the other hand, the gradient module 160 includes a bitmap unit 162 for processing color in a bitmap manner and a linear and circular unit 164 for linear and circular gradient processing. Here, the gradient processing refers to a smooth processing while creating a boundary of colors by looking at a given input color (register value processed by the preprocessor) and giving an offset value to the same color for each section. Since the gradient processing is used to give the effect of color in the 2D vector graphics processing, the gradient module 160 is used only for 2D graphics acceleration.

Meanwhile, when the 3D graphics accelerator includes a Gouraud Shading module, the gradient module may be processed by using the Gourad shading, and thus the gradient module may be omitted.

The blending module 130 may include a texture blending unit 132, an image blending unit 134, and an alpha blending unit 136 that perform texture, image, and alpha blending processing through a shader 500. It includes. The blending module 130 functions to mix the final image color color of each object during the 2D and 3D graphics processing and to store it in the frame buffer. Here, alpha blending is a kind of blending technique that gives a projection effect when combining two textures, and is a process for giving a property of a transparent medium such as water or glass.

Meanwhile, the functions of texture blending used in 3D graphics processing and image blending used in 2D vector graphics processing are similar, but they are separately processed. This is because the 2D vector graphics processor can accommodate various image formats, and also because the interval for generating a bitmap image of the gradient module 160, which is the upper block, is different from 3D graphics processing, and furthermore, the image blending is 2D. This is because it is preferable to process image blending separately because attributes are assigned in close association with a part (path generation) that generates a path in vector graphics processing.

The pass generation module 170 plays a central role in 2D vector graphics processing. The pass data cache 440 reads the values of the x and y axes for 2D graphics processing, and views each value stored in the register set. Generate 2D path data according to the module type.

That is, the path generation module 170 uses the data of the path data cache 440 to correspond to the setup process of the triangle module of the 3D graphics accelerator, and uses the data of the solid, image, and pattern for each module 172, 174, and 176. Generate 2D pass data for). These path data are of course used for image blending earlier.

On the other hand, the pass data cache 440 used in the pass generation module 170 is designed and used in the same way as reading the 3D data from the memory in 3D graphics acceleration. This is because 2D vector graphics accelerators do not require z-axis coordinates (depth coordinates), unlike 3D graphics accelerators. Thus, when the same cache is used, the speed of reading and processing data is much faster than that of three dimensions. In addition, when the pass data cache 440 is used in common, memory can be saved, and by reducing the read / write instruction, there is a great advantage in terms of acceleration speed.

The rasterizer module 150 includes an image interpolation 156 for interpolating a 2D vector image with an alpha tester 152 and a depth tester 154 that test an alpha value and a z-depth value. It includes).

Here, the alpha tester 152 integrates and tests the alpha values of the 2D and 3D graphics, and the alpha tester 252 also does not need the z-axis value in the 2D vector graphics, so the alpha test in the existing 3D graphics is performed. Compared to the 2D alpha test can be faster. As a result, integrated alpha test processing of 2D and 3D graphics is possible through one alpha test unit 252 without designing a separate block.

The pipeline flow through all the modules in the blending engine 140 finally stores the final pixel data in the frame buffer 600, which is used in the same manner, and then outputs the final pixel data through an interface to a screen such as an LCD. .

Looking at the function of the rendering engine 140 configured in this way,

First, in the case of processing 3D graphics, texture and light mapping are performed through the texture and light mapping units 112 and 114 of the mapping module 110, and then the texture blending unit 132 of the blending module 130 is performed. ) To perform texture blending. Next, after the alpha test and the depth test in the rasterizer module 150, image blending is performed in the image blending unit 134 of the blending module 130, and alpha blending is performed in the alpha blending unit 136. After alpha blending is performed, the generated pixel data is stored in the pixel cache 430, and finally, the pixel data is stored in the frame buffer 600.

On the other hand, even in the case of processing 2D graphics, the process proceeds similarly to 3D graphics processing. However, the light mapping unit 114 is not used, and the image interpolation unit 156 is used instead of the depth test unit 154. In addition, the image blending unit 134 performs the image blending in conjunction with the image interpolation unit 156 and the gradient module unit 160.

The integrated graphics acceleration application processor according to the present invention includes a unified rendering engine. That is, the rendering engine largely includes a 3D graphics accelerator module and a module for 2D vector graphics acceleration. Accordingly, the conventional 3D graphics accelerator module and the 2D vector graphics accelerator, which are made up of individual blocks, can solve problems such as waste of design area, memory waste, and the like. By storing the results in one frame buffer, it is possible to develop integrated content in which 2D graphic vector content and 3D graphic content are mixed in the future.

4 is a flowchart illustrating an integrated graphics processing process using an integrated graphics acceleration application processor according to another embodiment of the present invention.

Referring to FIG. 4, first, an idle state of a hardware (H / W) processor is checked (S100). Here, the idle check refers to determining whether the corresponding hardware processor is operating or resting. On the other hand, a hardware processor refers to a 2D and 3D integrated graphics acceleration application including the aforementioned 2D and 3D integrated graphics accelerator, an integrated instruction processor, and a register set.

If the hardware processor is in the idle state, it determines the type of graphics to be executed in the 2D and 3D integrated graphics accelerator (S110). That is, the S-register included in the register set mentioned above is checked to determine whether the graphics processing to be executed is 2D (OpenVG) graphics processing or 3D (OpenGLES) graphics processing.

According to the check of the S-register, the 2D and 3D integrated graphics accelerators are initialized to the 2D or 3D graphics acceleration modes (S120a and S120b). In other words, if the S-register value is in 2D graphics mode, the 2D and 3D integrated graphics accelerator is initialized to 2D graphics mode. If the S-register value is in 3D graphics mode, the 2D and 3D integrated graphics accelerator is initialized to 3D graphics mode. do.

Next, a dirty check of the cache used to execute 2D or 3D graphics is performed (S130). Here, dirty check refers to determining whether to reprocess a command that has been driven once. The reason for performing such a dirty check before executing an accelerator is that the repeated command among the already processed commands does not need to be processed again through the accelerator. In order to process the data quickly using cache data.

After the dirty check, the actual graphics processing is performed, that is, the geometry engine that is a preprocess of the graphics processing is executed (S140), and the rendering engine that is the postprocessing of the next graphics processing is executed (S150). Here, in the case of 2D graphics, the geometry engine processing may mean a scissor processing of cutting out only necessary graphic portions. That is, in the case of 2D graphics, the data for the procedure is read, the state is determined, and the corresponding part is cut.

In the rendering processing step, as described above with reference to FIGS. 1 to 3, final pixel data of an object to be represented as an image is generated and stored in a frame buffer through respective modules in the 2D and 3D integrated graphics accelerators. Here, it is referred to as rendering in the drawing, which is a concept that includes all the processes of triangle setup, gradient, path generation, and the like, and is used as a concept that includes a geometry process.

When 2D or 3D graphics processing is completed, the 2D and 3D integrated graphics accelerators are terminated (S160a and S160b). This 2D and 3D integrated graphics accelerator termination is also performed by referring to the graphics mode state of the S-register. As shown in the figure, when the 2D and 3D integrated graphics accelerator is finished, it is checked whether another 2D or 3D graphics processing is required (S170), and if another graphics processing is required, the process returns to the processor idle check step (S100) again. Completely terminate graphics processing.

Meanwhile, after the initialization steps S120a and S120b, a clear operation of clearing the frame buffer is performed separately from the graphic processing (S180). This clear operation is performed during the graphic processing, and when the graphic processing is completed, the clear operation is also terminated.

On the other hand, among the execution of each step, the idle check, clear operation, the end of the integrated accelerator is continuously performed when it is not finished by referring to the register value at the acceleration engine level whether or not the end of driving by block. That is, as shown in the figure, a continuous loop back function is performed.

The graphics acceleration integrated application processor and the graphics acceleration method of the present invention are based on a dual structure of a 3D graphics accelerator such as OpenGL / ES and a vector 2D graphics accelerator such as OpenVG serviced by an application processor embedded in a mobile communication terminal. Unified to a unified structure, integrated graphics acceleration. That is, the internal blocks of the same part of the 3D graphics accelerator and the 2D graphics accelerator are shared, so that the 3D graphics processing and the 2D vector acceleration processing can be processed in conjunction with each other.

In addition, the graphic acceleration integrated application processor of the present invention is embedded in a mobile communication terminal that is driven to accommodate it, is managed by a software driver (Software Driver) in charge of each process, each software driver API corresponding to its characteristics By interworking with EGL according to the standards of OpenGL / ES and OpenVG, it is possible to increase the memory efficiency by using the integrated frame buffer and reduce the design area by sharing the graphic processor.

So far, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram illustrating the same pipe line structure of a 3D graphics accelerator and a 2D graphics accelerator.

2A is a block diagram of an integrated graphics acceleration application processor according to an embodiment of the present invention.

2B is a block diagram of an integrated graphics acceleration application processor according to another embodiment of the present invention.

3 is a block diagram illustrating the rendering engine of FIG. 2A in more detail.

4 is a flowchart illustrating an integrated graphics processing process using an integrated graphics acceleration application processor according to another embodiment of the present invention.

Claims (30)

Geometry engine, which is a preprocessing unit formed in a pipe-line structure; And 2D and 3D integrated graphics accelerator including a rendering engine formed of a pipeline structure and a post-processing unit having a gradient module and path generation module for 2D graphics acceleration. According to claim 1, The geometry engine includes a World Transform module, a Lightening module, a View Transform module, a Projection Transform module, and a Clipping module. The rendering engine includes the gradient module, the pass generation module, a triangle setup module, a span processing module, and a realization module. The View Transform module, the projection transform module and the clipping module of the geometry engine, the triangle setup module, the span processing module and the realization module of the ending engine are adapted to the 2D graphics acceleration. 2D and 3D integrated graphics accelerator, characterized in that used together. According to claim 1, The rendering engine, 2D and 3D integrated graphics accelerator comprising a mapping module, blending module, and rasterization module commonly used for 2D and 3D graphics processing. The method of claim 3, wherein The mapping module includes a texture mapping unit and a light mapping unit that perform texture mapping and light mapping, The gradient module includes a bitmap part for color processing in a bitmap method and a straight line and circular part for linear and circular gradient (color change) processing. The blending module includes a texture blending unit, an image blending unit, and an alpha blending unit which performs a texture, an image, and an alpha blending process. The rasterizer module includes an alpha tester and a depth tester for testing an alpha value and a Z-depth value, and an image interpolation part for interpolating 2D vector images. Integrated graphics accelerator. The method of claim 4, wherein When processing the 3D graphics, The texture and light mapping unit of the mapping module, the texture blending unit of the blending module, the alpha test unit and depth test unit of the rasterizer module, and the image blending and alpha blending unit of the blending module are generated. After storing the pixel data in the pixel cache, finally storing the pixel data in a frame buffer, In the case of processing the 2D graphics, the light mapping unit is not used, the image interpolation unit is used instead of the depth test unit, and the image blending unit performs the image blending in conjunction with the image interpolation unit and the gradient module unit. 2D and 3D integrated graphics accelerator. The method of claim 4, wherein The pass generation module generates 2D pass data for module-specific solids, images, and patterns in response to the setup processing of the triangle module of the 3D graphics accelerator. According to claim 1, 2D and 3D integrated graphics accelerator further comprising a register set for storing instructions for 2D and 3D graphics acceleration. An instruction processor configured to process instructions and data for 2D and 3D graphics acceleration; A register set for storing instructions for accelerating the 2D and 3D graphics; And And a 2D and 3D integrated graphics accelerator configured to receive the command of the command processor to integrally process the 2D and 3D graphics acceleration. The method of claim 8, The command processing unit includes a command core for executing instructions delivered from an advanced high-performance bus (AHB) slave, and a command parser for parsing the instructions. , And said register set includes an S-register that stores state for 2D or 3D graphics acceleration. The method of claim 8, The 2D and 3D integrated graphics accelerator is based on a 3D graphics accelerator, further comprising 2D graphics processing modules that are used only for the 2D graphics acceleration. The method of claim 10, The 2D and 3D integrated graphics accelerator performs 3D or 2D graphics acceleration, according to the state information stored in the S register in the register set, In the case of the 2D graphics acceleration, the same functions as the 3D graphics acceleration are processed using a module in the 3D graphics accelerator together, and other functions are processed using the 2D graphics processing module. Processor. The method of claim 11, wherein The 2D graphics processing modules include a gradient module and a path generation module. The method of claim 11, wherein When the 2D and 3D integrated graphics accelerator includes a Gouraud Shading module, performing the gradient during the 2D graphics acceleration is performed using the Goard Shading Module. . The method of claim 10, The 2D and 3D integrated graphics accelerators include geometry with a World Transform module, Lightening module, View Transform module, Projection Transform module and Clipping module. A rendering engine with a Geometry engine, a Triangle Setup module, a Span Processing module, and a Realization module, The view transform module, the projection transform module and the clipping module of the geometry engine, the triangle setup module, the span processing module and the realization module of the rendering engine are used together for the 2D graphics acceleration. Integrated graphics acceleration application processor. The method of claim 14, And said modules are formed in a pipelined structure. The method of claim 14, The rendering engine, A mapping module, the gradient module, a blending module, the path generation module, and a rasterization module, The mapping module, the blending module, and the rasterizer module are commonly used for 2D and 3D graphic acceleration. And the gradient module and the pass generation module are used only for 2D graphics acceleration. The method of claim 16, The mapping module includes a texture mapping unit and a light mapping unit that perform texture mapping and light mapping, The gradient module includes a bitmap unit for bitmap-based graphics processing and a linear and radial unit for linear and circular gradient processing. The blending module includes a texture blending unit which performs a texture, an image, and an alpha blending process, an image blending unit, and an alpha blending unit. The rasterizer module includes an integrated graphic acceleration unit including an alpha test unit and a depth test unit for testing an alpha value and a z-depth value and an image interpolation unit for interpolating 2D vector images. Application processor. The method of claim 17, When processing the 3D graphics, The texture and light mapping unit of the mapping module, the texture blending unit of the blending module, the alpha test unit and depth test unit of the rasterizer module, and the image blending and alpha blending unit of the blending module are generated. After storing the pixel data in the pixel cache, finally storing the pixel data in a frame buffer, In the case of processing the 2D graphics, the light mapping unit is not used, the image interpolation unit is used instead of the depth test unit, and the image blending unit performs the image blending in conjunction with the image interpolation unit and the gradient module unit. Graphic accelerated integrated application processor, characterized in that. The method of claim 16, And the pass generation module generates 2D pass data for module-specific solids, images, and patterns in response to the setup processing of the triangle setup module of the 3D graphics accelerator. The method of claim 8, The same type of data is stored in the same cache (Cache) and the graphics acceleration integrated application processor, characterized in that for the 2D and 3D graphics acceleration processing. Checking an idle state of a hardware (H / W) processor; Initializing the 2D and 3D integrated graphics accelerator to a 2D or 3D graphics acceleration mode; Performing 2D or 3D graphics acceleration; And Terminating the 2D and 3D integrated graphics accelerators. The method of claim 21, Determining a type of graphic to be executed in the 2D and 3D integrated graphics accelerator before the initializing step, The acceleration performance step, The accelerating step may include: dirty checking a cache used to execute the 2D or 3D graphics; Executing a geometry engine that is a preprocess of graphics processing; And Executing a rendering engine that is a post-process of the graphics processing. The method of claim 21, And performing a clear operation on the frame buffer separately after the idle state check step. The method of claim 21, The processor may receive an instruction processor for processing instructions and data for 2D and 3D graphics acceleration, a register set for storing instructions for 2D and 3D graphics acceleration, and an instruction processor for the 2D and 3D graphics acceleration. The 2D and 3D integrated graphics accelerator, And performing acceleration in the acceleration performing step according to the command transmitted from the command processing unit. The method of claim 24, The 2D and 3D integrated graphics accelerators are based on 3D graphics accelerators and include modules for 2D graphics processing that are used only for the 2D graphics acceleration, In the case of the 2D graphics acceleration, the same functions as the 3D graphics acceleration are processed using a module in the 3D graphics accelerator together, and other functions are processed using the 2D graphics processing module. . The method of claim 25, The 2D and 3D integrated graphics accelerator includes a World Transform module, a Lightening module, a View Transform module, a Projection Transform module, and a Clipping module. A rendering engine having a geometry engine, a triangle setup module, a span processing module, and a realization module; Wherein the view transform module, the projection transform module and the clipping module of the geometry engine, the triangle setup module, the span processing module and the realization module of the rendering engine are used together for the 2D graphics acceleration. Integrated graphics acceleration method. The method of claim 25, The rendering engine, Including a mapping module, a gradient module, a blending module, a path generation module, and a rasterization module, The mapping module, the blending module and the rasterizer module are commonly used for 2D and 3D graphics acceleration, And the gradient module and the pass generation module use only 2D graphics acceleration. The method of claim 27, The mapping module includes a texture mapping unit and a light mapping unit. The gradient module includes a bitmap part and a linear and radial part. The blending module includes a texture blending unit, an image blending unit, and an alpha blending unit. The rasterizer module includes an alpha tester, a depth tester, and an image interpolation unit. When processing the 3D graphics, The texture and light mapping unit of the mapping module, the texture blending unit of the blending module, the alpha test unit and depth test unit of the rasterizer module, and the image blending and alpha blending unit of the blending module are generated. After storing the pixel data in the pixel cache, finally storing the pixel data in a frame buffer, In the case of processing the 2D graphics, the light mapping unit is not used, the image interpolation unit is used instead of the depth test unit, and the image blending unit performs the image blending in conjunction with the image interpolation unit and the gradient module unit. Integrated graphics acceleration method characterized in that. The method of claim 27, And the path generation module generates 2D path data for each module of solids, images, and patterns in response to the setup processing of the triangle setup module of the 3D graphics accelerator. The method of claim 21, And homogeneous data is stored in the same cache and used for the 2D or 3D graphic acceleration process.

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