KR20090110556A - Integrated circuit and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: An integrated circuit and a method for manufacturing the same are provided to realize a stacked capacitor after a process of manufacturing a PRAM chip, thereby maximizing a capacitor area according to simply process addition. CONSTITUTION: An integrated circuit includes a cell array area(D), a peripheral circuit area(E), and a ferroelectric capacitor area. The cell array area includes a phase change resistance device. The peripheral circuit area is a part except the cell array area. The ferroelectric capacitor area is formed in the cell array and an upper layer of the peripheral circuit area. The ferroelectric capacitor area includes a ferroelectric capacitor device.

Description

Integrated circuit and method for manufacturing

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a chip layout diagram of a typical PRAM.

5 is a detailed circuit diagram showing a capacitor used in a pump circuit in a general PRAM chip.

6 is a process sectional view of a general PRAM.

7 is a configuration diagram of a cell array of a conventional phase change memory device.

8 is a detailed circuit diagram illustrating a ferroelectric capacitor used in a pump circuit in an integrated circuit according to the present invention.

9 is a layout view in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

10 is a cross-sectional view illustrating a process in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

11 and 12 show other embodiments of an integrated circuit in accordance with the present invention.

The present invention relates to an integrated circuit and a method of forming the same, and more particularly, to an integrated circuit in which a phase change memory device and a ferroelectric capacitor region are stacked to maximize a capacitor capacitor without increasing layout area. Technology.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material consisting of Ge-Sb-Te (Ge2Sb2Te5). ).

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

On the other hand, integrated circuit (Integrated Circuit) is a basic element that is basically used in various electronic devices, such as computer systems or communication systems. Such integrated circuits may include, for example, a myriad of circuits such as a memory device, a digital signal processor (DSP), a system on chip (SoC), an RFID tag (Radio Frequency Identification Tag), and the like. These integrated circuits are designed with as many capacitors as possible, as long as the layout of the chip allows.

For example, a nonvolatile ferroelectric capacitor (FeRAM) is attracting attention as a next-generation memory device because of its data processing speed as much as DRAM (DRAM) and data is preserved even when the power is turned off. have. FeRAM is a memory device having a structure similar to that of DRAM, and uses a ferroelectric material as a capacitor material, and uses high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

In addition, an integrated circuit device such as a conventional memory device, an RFID device, a system on chip, or a FeRAM is disposed in an area in which a peripheral circuit area and a capacitor area are separately divided on the same layer. That is, a MOS capacitor, a PIP (Polysilicon-Insulator-Polysilicon) or a MIM (Metal-Insulator-Metal) capacitor has the same process level as the peripheral circuit area. Accordingly, in the conventional integrated circuit, the capacitor region and the peripheral circuit region may not be stacked in order to reduce the overall layout area.

For example, a DRAM uses a cell capacitor for a memory cell and uses a MOS capacitor or a PIP or MIM structure capacitor described above in a peripheral circuit area. Accordingly, since the circuit region and the capacitor using the complementary metal-oxide-semiconductor (CMOS) circuit are formed at the same process level, they cannot be stacked.

Therefore, in the conventional integrated circuit, the capacitor is disposed on the same layer as the peripheral circuit area in a separate area from the peripheral circuit. Accordingly, the area of the entire layout is determined by the sum of the layout of the peripheral circuit area and the layout of the capacitor area, thereby increasing the overall layout area of the integrated circuit.

On the other hand, as the capacity of the phase change memory device (PRAM) becomes larger, the operating voltage becomes smaller and power noise increases. However, the capacity of a capacitor required for a power pump for generating various internal voltages such as the pumping voltage VPP and the back bias voltage VBB is increased.

In addition, the capacity of the decoupling capacitor of the output stage and the power stage of the pump is increased. Therefore, the area by the capacitor and decoupling capacitor associated with the pump cannot be reduced.

In particular, a phase change memory device (PRAM) using the phase change resistor (PCR) element described above uses a capacitor element to stabilize the operation of the cell. In addition, since the phase change memory device consumes a large amount of power, a pumping operation using a capacitor element is performed to solve this problem.

As a result, the capacitor and the pumping capacitor occupy most of the area of the PRAM. Thus, there is a need to reduce the chip size of phase change memory devices in which the capacitor occupies most of the total memory area.

It is an object of the present invention to provide an integrated circuit in which the capacitor area is maximized without increasing the layout area.

An object of the present invention is to provide an integrated circuit that maximizes a capacitor area by implementing a multilayer capacitor on top of a phase change memory device so that a separate capacitor area is unnecessary.

It is an object of the present invention to provide an integrated circuit that realizes the maximization of a capacitor area according to a simple process addition by implementing a multilayer capacitor after a manufacturing process of a phase change memory device.

SUMMARY OF THE INVENTION An object of the present invention is to use a ferroelectric capacitor in a circuit using a large capacitor in a phase change memory device to reduce chip area and cost, and to reduce a delay path to perform high speed operation.

It is an object of the present invention to reduce power noise by using ferroelectric capacitors in a circuit in which a large capacitor is used in a phase change memory device.

An object of the present invention is to reduce the area of the phase change memory device by eliminating the area required for the pump capacitor and the decoupling capacitor.

An integrated circuit of the present invention for achieving the above object, the cell array region including a phase change resistance element; A peripheral circuit region excluding a cell array region; And a ferroelectric capacitor region formed on the upper layer of the cell array region and the peripheral circuit region and including the ferroelectric capacitor device.

In addition, the integrated circuit forming method of the present invention includes forming a peripheral circuit region including a CMOS circuit region and a cell array region including a phase change resistance element on the substrate; Forming a metal line on the cell array region and the peripheral circuit region; And forming a ferroelectric capacitor region including a ferroelectric capacitor on the metal line.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a chip layout diagram of a general PRAM.

The bank 0 to bank 3 regions of the PRAM represent a cell array region of the PRAM. The peripheral circuit region represents a circuit region including a pump capacitor and a decoupling capacitor.

5 is a detailed circuit diagram illustrating a capacitor used in a pump circuit in a general PRAM.

The pump driver region 30 of the PRAM includes drivers 32 and 36 and a pump capacitor 34. The pump driver region 30 drives the pump enable signal Pump_en to output the pump output signal Pump_out.

Here, the pump capacitor 34 is used in the pump circuit region of the PRAM. The decoupling capacitors 40 and 42 are used in the output terminal and the power terminal in which the pump output signal Pump_out is output. In a conventional PRAM, a pump capacitor 34 and a decoupling capacitor 40 and 42 are implemented using a CMOS capacitor (gate capacitor).

6 is a process sectional view showing the structure of a general PRAM.

The manufacturing process of the phase change memory device is largely composed of a CMOS process, a PRAM process, and a metal line process. In a general CMOS process, a pump capacitor and a decoupling capacitor are formed using a CMOS capacitor as shown in area (A).

In the PRAM process, a phase change resistance element, a word line WL, and a global bit line GBL are formed. In the metal line process, the metal line M1 is formed through the contact node CN1, and the metal line M2 connected to the contact node CN2 is formed on the metal line M1.

However, a typical PRAM having such a configuration has a very small dielectric constant of a CMOS capacitor (gate capacitor), which requires a large layout area in order to realize the required capacity.

7 is a configuration diagram illustrating a cell array of a conventional phase change memory device.

The conventional cell array includes a unit cell C in an area where a plurality of bit lines BL1 to BL4 and a plurality of word lines WL1 to WL4 intersect. The unit cell C includes a phase change resistance element PCR and a diode D. Here, the diode D is made of a PN diode element.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL.

In the present invention, a low voltage is applied to the selected word line WL in the read mode. The read voltage Vread is applied to the bit line BL to cause the set current or the reset current Ireset to flow toward the word line WL through the bit line BL, the phase change resistance element PCR and the diode D. do.

The sense amplifier S / A senses the cell data applied through the bit line BL and compares the data "1" with the data "0" by comparing with the reference voltage ref. The reference current Iref flows through the reference voltage ref applying terminal. The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

8 is a detailed circuit diagram illustrating a ferroelectric capacitor used in a pump circuit of an integrated circuit according to the present invention.

Pump driver region 100 of the PRAM includes drivers 102 and 106 and ferroelectric pump capacitor 104. The pump driver region 100 drives the pump enable signal Pump_en to output the pump output signal Pump_out.

In the pump circuit region of the PRAM, a ferroelectric pump capacitor 104 is used. In addition, the ferroelectric decoupling capacitors 200 and 202 are used in the output terminal and the power stage where the pump output signal Pump_out is output, and the ferroelectric decoupling capacitors 200 and 202 use a mixed process based ferroelectric capacitor.

Here, the ferroelectric pump capacitor 104 mainly performs a function of boosting the input voltage. The power decoupling ferroelectric capacitors 200 and 202 remove power noise and stabilize a voltage.

The ferroelectric capacitors 104, 200, and 202 have a high capacity and are relatively simple to process and have a simple capacitor structure. In addition, the ferroelectric capacitors 104, 200, and 202 may easily implement a stacked structure and may easily realize high capacitance. Accordingly, when the ferroelectric capacitors 104, 200, and 202 are stacked on the PRAM region, the ferroelectric capacitors 104, 200, and 202 may be stacked on the PRAM region to maximize the capacitor region without increasing the layout area.

9 is a layout diagram illustrating a memory device in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

The bank 0 to bank 3 areas of the PRAM represent PRAM cell array areas. In addition, the peripheral circuit region represents a region in which a switching element or an active and passive element including a CMOS are formed.

In addition, the region C stacked on the banks 0 to 3 and the peripheral circuit region becomes a region in which the ferroelectric capacitor region can be stacked. This region (C) becomes a layout region in which a ferroelectric pump capacitor or a ferroelectric decoupling capacitor, which is stacked in a single layer or multiple layers, is formed.

The integrated circuit of the present invention having such a configuration is formed by stacking a ferroelectric capacitor region (C) including a ferroelectric capacitor on the cell array region and the peripheral circuit region. Here, since the peripheral circuit region and the cell array region of the PRAM have different process levels from the ferroelectric capacitor, the ferroelectric capacitor region C may be stacked on the peripheral circuit region and the cell array region.

In the ferroelectric capacitor region (C), a ferroelectric capacitor having a relatively higher dielectric constant than that of a general dielectric capacitor and a MOS capacitor is used in the ferroelectric capacitor region (C) to reduce the area of the capacitor to reduce the overall layout area of the PRAM chip. do.

10 is a cross-sectional view illustrating a memory device in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

The manufacturing process of the phase change memory device according to the present invention is largely composed of a CMOS process, a PRAM process, a metal line process, and a ferroelectric capacitor process. In the cell array region D of the PRAM, an N + region, a phase change resistance element, a word line WL, a global bit line GBL, and the like are formed. Then, the peripheral circuit region E of the PRAM is formed using the CMOS capacitor. In the peripheral circuit region E, a switching device or a CMOS device including a P + region and a gate is formed on the substrate.

In the metal line process, the metal line M1 and the peripheral circuit region E are connected through the contact node CN1. In addition, the metal line M2 is connected to the metal line M1 through the contact node CN2. The metal line M2 is connected to the metal line M3 through the contact node CN3.

In addition, a ferroelectric capacitor region F is formed on the CMOS circuit region including the switching element, the CMOS element, and the metal lines M1 and M2, that is, the peripheral circuit region E and the cell array region D. . Here, the ferroelectric capacitor region F is used as a pump capacitor and a decoupling capacitor. The ferroelectric capacitor region F can be used as a pump and decoupling capacitor in any region including the cell array region D and the peripheral circuit region E of the PRAM.

In the ferroelectric capacitor region F, a contact node CN4 is formed on the metal line M3, which is a lower electrode connection line. The lower electrode connection line is connected to the lower electrode BE of the ferroelectric capacitor FC through the contact node CN4. The ferroelectric FE and the upper electrode TE are sequentially stacked on the lower electrode BE, and the contact node CN5 is formed on the upper electrode TE. The metal line M4, which is the upper electrode connecting line, is formed on the contact node CN5.

In the present invention, the capacitor formed on the upper portion of the cell array region D is formed of a ferroelectric capacitor FC, but the present invention is not limited thereto, but the high-k dielectric such as a high-k dielectric is not limited thereto. It may be formed as.

11 is another embodiment of a memory device in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

The manufacturing process of the phase change memory device according to the present invention is largely composed of a CMOS process, a PRAM process, a metal line process, and a ferroelectric capacitor process. In the cell array region D of the PRAM, an N + region, a phase change resistance element, a word line WL, a global bit line GBL, and the like are formed. Then, the peripheral circuit region E of the PRAM is formed using the CMOS capacitor. In the peripheral circuit region E, a switching element or a CMOS element including an N + region and a gate is formed on the substrate.

In the metal line process, the metal line M1 and the peripheral circuit region E are connected through the contact node CN1. In addition, the metal line M2 is connected to the metal line M1 through the contact node CN2. The metal line M2 is connected to the metal line M3 through the contact node CN3.

The ferroelectric capacitor region H is formed on the cell array region D, the peripheral circuit region E, and the metal process region in a stacked form. Here, the ferroelectric capacitor region H is used as a pump capacitor and a decoupling capacitor in the cell array region D and the peripheral circuit region E of the PRAM.

In the ferroelectric capacitor region H, a contact node CN4 is formed on the metal line M3, which is a lower electrode connection line. The lower electrode connection line is connected to the lower electrode BE of the ferroelectric capacitor FC through the contact node CN4. The ferroelectric FE and the upper electrode TE are sequentially stacked on the lower electrode BE, and the contact node CN5 is formed on the upper electrode TE. The metal line M4, which is the upper electrode connecting line, is formed on the contact node CN5. The ferroelectric capacitor FC is provided in plurality between the upper electrode connection line and the lower electrode connection line on the same layer.

12 is another embodiment of a memory device in which a PRAM and a ferroelectric capacitor region are stacked in an integrated circuit according to the present invention.

In the integrated circuit according to the exemplary embodiment of FIG. 12, the ferroelectric capacitor region J is formed on the cell array region D, the peripheral circuit region E, and the metal process region. Here, the ferroelectric capacitor region J is used as a pump capacitor and a decoupling capacitor in the cell array region D and the peripheral circuit region E of the PRAM.

In the ferroelectric capacitor region J, a contact node CN4 is formed on the metal line M3 that is the first electrode connection line. The first electrode connection line is connected to the lower electrode BE of the ferroelectric capacitor FC through the contact node CN4. The ferroelectric FE and the upper electrode TE are sequentially stacked on the lower electrode BE, and the contact node CN5 is formed on the upper electrode TE. The metal line M4, which is the second electrode connection line, is formed on the contact node CN5.

In addition, a contact node CN6 is formed on the metal line M4 that is the second electrode connection line. The second electrode connection line is connected to the lower electrode BE of the ferroelectric capacitor FC through the contact node CN6. The ferroelectric FE and the upper electrode TE are sequentially stacked on the lower electrode BE, and the contact node CN7 is formed on the upper electrode TE. The metal line M5, which is the first electrode connection line, is formed on the contact node CN7.

The ferroelectric capacitor FC is formed by stacking a plurality of layers between the metal line M5 and the metal line M3. The metal lines M3 and M5, which are the first electrode connection lines, commonly use the metal line M4, which is the second electrode connection line. In addition, the ferroelectric capacitor FC having a stacked structure selectively uses metal lines M3 and M5 depending on whether ferroelectric capacitors FC disposed at left and right sides are used.

As described above, the present invention has described RFID, system-on-chip, FeRAM, and PRAM as integrated circuits, but the present invention is not limited thereto, and may be applied to a process such as a smart card or another integrated circuit.

As described above, the integrated circuit according to the present invention has the following effects.

First, the present invention enables to maximize the capacitor area without increasing the layout area.

Second, the present invention implements a stacked capacitor on top of the PRAM chip so that a separate capacitor area is unnecessary, thereby maximizing the capacitor area.

Third, the present invention can realize the maximization of the capacitor region by the simple process addition by implementing the multilayer capacitor after the manufacturing process of the PRAM chip.

Fourth, the present invention uses a ferroelectric capacitor in a circuit in which a large capacity capacitor is used in a PRAM, thereby enabling high-speed operation by reducing chip area and reducing a delay path.

Fifth, the present invention can reduce power noise by using ferroelectric capacitors in a circuit in which a large capacitor is used in a PRAM.

Sixth, the present invention provides an effect of reducing the area of the PRAM chip circuit by eliminating the area required for the pump capacitor and the decoupling capacitor.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (16)

A cell array region including a phase change resistance element; A peripheral circuit region excluding the cell array region; And And a ferroelectric capacitor region formed in the upper layer of the cell array region and the peripheral circuit region and including a ferroelectric capacitor element. The integrated circuit according to claim 1, wherein a pump capacitor used in the pump circuit region of the peripheral circuit region is used as the ferroelectric capacitor element. The integrated circuit according to claim 1, wherein a decoupling capacitor used at the output of the pump circuit region of the peripheral circuit region is used as the ferroelectric capacitor element. The integrated circuit according to claim 1, wherein a decoupling capacitor used for the power stage of the peripheral circuit region is used as the ferroelectric capacitor element. 2. The integrated circuit of claim 1 wherein the integrated circuit is a phase change memory device (PRAM). 2. The integrated circuit of claim 1, wherein the peripheral circuit region is a CMOS circuit region composed of active and passive elements including CMOS. The integrated circuit of claim 1, wherein the ferroelectric capacitor region is formed in a stacked type on an upper layer of the cell array region and the peripheral circuit region. 2. The integrated circuit of claim 1, wherein the ferroelectric capacitor region includes a plurality of the ferroelectric capacitor elements on the same layer. A phase change memory device including a bank area including a phase change resistance element and a peripheral circuit area except the bank area; And A ferroelectric capacitor region formed in an upper layer of the phase change memory device in a cross-sectional structure, the ferroelectric capacitor region including a ferroelectric capacitor element; And a decoupling capacitor used for the pump capacitor area used in the pump circuit area of the phase change memory device and an output terminal and the power end of the pump circuit area as the ferroelectric capacitor element. 10. The integrated circuit of claim 9, wherein the peripheral circuit region is a CMOS circuit region composed of active and passive elements including CMOS. 10. The integrated circuit of claim 9, wherein the ferroelectric capacitor region is formed in a stacked layer on an upper layer of the phase change memory device. 10. The integrated circuit of claim 9, wherein the ferroelectric capacitor region includes a plurality of the ferroelectric capacitor elements on the same layer. Forming a peripheral circuit region including a CMOS circuit region on the substrate and a cell array region including a phase change resistance element; Forming a metal line on the cell array region and the peripheral circuit region; And Forming a ferroelectric capacitor region including a ferroelectric capacitor on the metal line. The method of claim 13, wherein the forming of the region of the ferroelectric capacitor Forming a lower electrode connection line connected to the metal line; Forming the ferroelectric capacitor including a lower electrode, a ferroelectric layer, and an upper electrode on the lower electrode connection line; And Forming an upper electrode connection line on the ferroelectric capacitor. 15. The method of claim 14, wherein the ferroelectric capacitor region is formed with a plurality of ferroelectric capacitor elements on the same layer. 15. The method of claim 14, wherein the ferroelectric capacitor region is formed by stacking a plurality of ferroelectric capacitor elements on the metal line.

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