KR20090110270A - OFDM receiving apparatus and mode detecting method thereof - Google Patents

Abstract

PURPOSE: An OFDM receiving apparatus and a mode detecting method thereof are provided to reduce chip size by designing the usage of memory through a simple mode detection method. CONSTITUTION: A mode detecting method at the OFDM receiver is as follows. The accumulated values about primary correlative values are found. The maximum accumulated value is produced among accumulated values. The first mode is detected from the maximum accumulated value. The corresponding second delayed signal is selected according to the primary correlative value corresponding to the detected first mode of second delayed signals. The accumulated value for the second modes is produced by adding and subtracting the selected second delayed signal and the primary correlative value(S932). The second mode is detected from the calculated accumulated value.

Description

OPDM receiving apparatus and mode detecting method thereof

The present invention relates to mode detection in an initial synchronization process of an orthogonal frequency division multiplex (OFDM) receiving apparatus. In particular, the FFT mode is first detected for the same signal, and then the GI mode is detected using the result. The present invention relates to an OFDM receiver and a mode detection method thereof capable of performing fast mode detection and further reducing chip size.

In general, a broadcasting system of digital high definition television (HDTV) compresses about 1 Gbps of digital data obtained from a high definition image source into 15 to 18 Mbps of data, thereby compressing dozens of Mbps of digital data into a limited band channel of 6 to 8 MHz. Send it through.

As such, the modulation scheme used in high-definition television broadcasting systems requires high band efficiency because it transmits tens of Mbps of digital data through a limited band channel of 6 to 8 MHz. In addition, since high-definition television broadcasting adopts a terrestrial simultaneous broadcasting method using a VHF / UHF band channel allocated for conventional analog television broadcasting, it has to have a strong characteristic against co-channel interference caused by analog television signals.

In order to improve transmission efficiency per bandwidth and prevent interference, orthogonal frequency division multiplexing (hereinafter referred to as "OFDM") among digital modulation schemes has been adopted as a next generation high-definition television terrestrial broadcasting scheme. The OFDM method converts a symbol string input in serial form into parallel data of a predetermined block unit, and then multiplexes the parallelized symbols with different subcarrier frequencies.

OFDM uses multiple carriers, and carriers have orthogonality with each other. When the product of two carriers becomes '0', the two carriers are said to be orthogonal. Orthogonal carriers are used to increase the spectral efficiency by overlapping the spectrum of carriers.

In order to extract digital data from the signal modulated by the OFDM scheme, the receiver first performs synchronization with the transmitter. One of the synchronization operations with the transmitter at the receiver is to detect the Fast Fourier Transform (FFT) mode and the Guard Interval (GI) mode from the received signal.

As described above, since the data to be transmitted by the transmitter is converted and transmitted by the inverse fast Fourier transform scheme, the receiver demodulates the received signal through the Fast Fourier transform scheme. Therefore, the receiver needs to know the starting point and the interval (effective data interval) of the symbol to be fast Fourier transformed.

 The starting point of the symbol and the valid data interval depend on the FFT mode and GI mode of the system. Here, the FFT mode refers to an interleaving method that is performed to minimize the influence of an error that may occur in a signal transmission and reception process. For example, the FFT mode is determined as one of 2K, 4K, and 8K modes.

In addition, the GI mode is based on the length of the guard interval inserted between each symbol to prevent interference between symbols. The guard interval is provided by copying lower predetermined bit values of data of the valid data interval. In this case, the GI mode is determined to be one of 1/4, 1/8, 1/16, and 1/32 modes according to how many guard bits are provided for the length of the lower number of valid data.

However, there is a problem that the receiver takes a lot of time in detecting the mode of the system. In addition, since the respective modes are detected using signals received through different channels, errors in mode detection may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide an OFDM receiver and a mode detection method in the OFDM receiver capable of performing accurate and fast mode detection and further reducing chip size.

According to an aspect of the present invention, there is provided a mode detection method in an OFDM receiver, using first delay signals for delaying a received signal and first correlation values for the received signal. Detecting a first mode of the signal; And a second of the received signal by using second delayed signals having a predetermined delay of a first correlation value corresponding to the first mode among the first correlation values and a first correlation value corresponding to the first mode. Detecting a mode.

According to another aspect of the present invention, there is provided an OFDM receiver according to an embodiment of the present invention, using first delayed signals for delaying a received signal and first correlation values for the received signal. A first mode detector detecting a mode; And a second of the received signal by using second delayed signals having a predetermined delay of a first correlation value corresponding to the first mode among the first correlation values and a first correlation value corresponding to the first mode. And a second mode detector for detecting a mode.

In the OFDM receiver and its mode detection method according to the present invention, the FFT mode is first detected for the same signal, and then the GI mode is detected using the result, thereby enabling accurate and fast mode detection, and furthermore, relatively simple. By suggesting a mode detection method and efficiently designing the memory usage, the chip size can be reduced.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a transmitter and a receiver of an OFDM communication system.

Referring to FIG. 1, in the communication system of the present invention, a channel coding unit 121, a mapper 122, a pilot inserting unit 123, an inverse fast Fourier transformer 124 (IFFT), and a CP are inserted into a transmitter 120. A unit 125, a DAC unit 126, and an RF transmitter 127, and the receiver 140 includes an RF receiver 141, an ADC unit 142, a frequency offset compensator 143, and a CP remover. 145, fast Fourier transformer 146 (FFT), channel estimator 160, demapper 148, and channel decoder 149.

On the other hand, the receiver 140 is a pre-FFT unit 144 for obtaining a synchronization for the symbol between the frequency offset compensation unit 143 and the CP removing unit 145, a distributed pilot detector 147 for extracting a distributed file. More).

The transmitter 120 first performs channel coding on the input data X to be transmitted by the channel coding unit 121, and then modulates the data according to a corresponding modulation scheme in the mapper 122. Next, pilots are inserted through the pilot inserting unit 123, and an inverse fast Fourier transform (IFFT) is performed by the inverse fast Fourier transformer 124, and then the CP is repeated by the CP inserting unit 125. Insert Cyclic Prefix). Finally, after digital-to-analog conversion is performed in the DAC unit 126, the signal X is output through the channel of the corresponding bandwidth from the RF transmitter 127.

The receiver 140 receives the signal Y from the transmitter 120 through the RF receiver 141. The relationship between the received signal Y and the input data X may be defined as in Equation 1 below.

Y = H * X + n

Here, H represents a channel and n represents noise.

The receiver 140 estimates the channel H and estimates the input data using the estimated channel. This is described in more detail.

The receiver 140 first performs analog-to-digital conversion on the signal Y received through the RF receiver 141 in the ADC unit 142 and then performs a sampling frequency offset in the frequency offset compensator 143. offset). Next, the CP removal unit 145 removes the CP, and the fast Fourier transformer 146 (hereinafter referred to as an "FFT unit") performs fast Fourier transform.

Next, the distributed pilot detector 147 detects pilots included in respective symbols of the channel (147), and the channel is estimated by the channel estimator 160 based on the detected pilots (160). When the channel is estimated, the input data X is estimated using the channel. Finally, the demapper 148 and the channel decoding unit 149 extract the input data X through the demapping process and the channel decoding process.

An operation of estimating input data X in the receiver 140 may be represented by Equation 2 below.

X '= Y / H' = H * X / H '+ n / H'

Where X 'is the estimated input data and H' represents the estimated channel.

However, before performing the above operation in the receiver of the OFDM communication system, the FFT mode and the GI mode of the system should be detected from the received signal. As described above, it is necessary to know the interleaving method (FFT mode) and the length of the guard interval inserted between symbols (GI mode) during the inverse Fourier transform of the receiver, so that accurate input data can be estimated.

An interleaving scheme and a guard interval setting method in an OFDM communication system will be briefly described.

2 is a diagram briefly illustrating a method for setting a guard interval in an OFDM system.

Referring to FIG. 2, the transmitter 120 of the OFDM system inserts guard intervals GIi and GIj according to the GI mode to prevent inter-symbol interference between adjacent symbols SYMi and SYMj. At this time, since each guard period (GIi, GIj) is created by copying a portion (hatched) of the end of the corresponding symbol (SYMi, SYMj), the value is the same as the end of the symbol (SYMi, SYMj) Value.

Here, Tsym represents a valid symbol interval in the FFT mode, and this valid symbol interval varies depending on all FFTs. In addition, Tu represents a guard interval, which also depends on the GI mode. As described above, the OFDM signal is demodulated through the fast Fourier transform method. For this purpose, detection of the FFT mode and the GI mode of the starting point and the interval (effective data interval) of the symbol must be preceded. The detection operation for the FFT mode and the GI mode may be performed by the initial synchronizer PRE_FFT 144 of the receiver 140 in the OFDM communication system of FIG. 1. Hereinafter, the mode detection operation in the OFDM receiver according to the present invention will be described in detail.

3 is a block diagram illustrating an OFDM receiver according to an embodiment of the present invention.

Referring to FIG. 3, the OFDM receiver 400 according to an embodiment of the present invention includes a first mode detector 420 and a second mode detector 440.

The first mode detector 420 uses the first delayed signals DSIG11, DSIG12, and DSIG13 having the predetermined delay of the received signal InSIG and the first correlation values CORR1 to CORR3 for the received signal InSIG. The first mode MOD1 of the received signal InSIG is detected. In this case, the first mode MOD1 may be an FFT mode. Hereinafter, the case where the first mode MOD1 is the FFT mode will be described.

In order to detect the FFT mode MOD1, the first mode detector 420 may include first delay circuits DLY11 to DLY14, a condenser conj1, multipliers X1 to X3, and adders RCA1 to RCA3. And a first mode detector MOD1 DETC.

The first delay circuits DLY11 to DLY14 delay the reception signal InSIG to generate the first delay signals DSIG11 to DSIG13. As described above, the FFT mode may have a value of one of 2K, 4K, and 8K. Preferably, the first delay circuits DLY11 to DLY14 may be provided in numbers corresponding to the type of the FFT mode MOD1.

According to the OFDM receiver 400 of the present embodiment, the first delay circuits DLY11 to DLY14 may each perform a 2K sample delay. Accordingly, the eleventh delay signal DSIG11 is a signal in which the received signal InSIG is delayed by 2K by the eleventh delay circuit DLY11, and the twelfth delay signal DSIG12 delayed by the twelfth delay circuit DLY12 is received. The signal InSIG is a signal delayed by 4K by the twelfth delay circuit DLY12. Similarly, the thirteenth delay signal DSIG13 is a signal in which the received signal InSIG is delayed by 8K by the thirteenth delay circuit DLY13 and the fourteenth delay circuit DLY14. In the case of the thirteenth delay signal, although the thirteenth delay circuit DLY13 and the fourteenth delay circuit DLY14 are used together to delay 2K samples, one delay circuit for delaying 4K samples may be used. .

The condenser conj1 generates the complex conjugate signal CSIG of the received signal InSIG, and the multipliers X1, X2, and X3 multiply the corresponding first delay signal and the conjugate complex signal CSIG by the first. Output as correlation values CORR1 to CORR3. In addition, the adders RCA1 to RCA3 obtain cumulative values A1 to A3 for corresponding first correlation values CORR1 to CORR3. Details of these adders will be described in more detail with reference to FIGS. 5 to 7.

Meanwhile, the first mode detector MOD1 DETC determines the FFT mode by detecting a maximum value among the accumulated values A1 to A3 output from the adders RCA1 to RCA3. The detection of the FFT mode by the maximum cumulative value relates to a matter that can be easily performed by those skilled in the art to which the present invention pertains, and a detailed description thereof will be omitted.

As a result, the OFDM receiver 400 according to the present exemplary embodiment performs one detection operation on an OFDM signal input in an arbitrary FFT mode by using delay circuits DLY11 to DLY14 connected in series of the first mode detector 420. This makes it easy to detect the FFT mode. In other words, it is not necessary to repeatedly perform the detection operation for each FFT mode. In principle, the OFDM signal belonging to a specific FFT mode is accumulated in only one of the adders. Accordingly, if the maximum accumulation value is found, the corresponding FFT mode can be detected.

When all of the FFTs are detected through the first mode detector 420, detection of the second mode, that is, the guard mode, is performed by the second mode detector 440, which is a more detailed configuration of the second mode detector 440. And operations are described in FIGS. 8 and 9.

4 is a structural diagram illustrating a general addition logic circuit that may be used in the adders RCA1 to RCA3 of the first mode detector of FIG. 3.

Referring to FIG. 4, the addition logic circuit ADD adds an input value IN and an output value OUT and outputs the accumulated value A1. In order to calculate the cumulative value A1, the addition logic circuit ADD must have a storage space, that is, a memory having a size corresponding to the size of the input value IN and the cumulative value A1. Accordingly, when the addition logic circuit ADD is used in the adders of the first mode detector, there is a problem that the size of the memory must be increased in order to accumulate a correlation number of a predetermined number or more.

FIG. 5 is a structural diagram illustrating an adder having a configuration different from that of FIG. 4, which may be used in the adders RCA1 to RCA3 of the first mode detector of FIG. 3.

Referring to FIG. 5, adders RCA1 to RCA3 according to an embodiment of the present invention include add logic circuits +1 to +3 and controllers RCA CTL1 to RCA CTL3. That is, the first adder RCA1 is composed of a first adding logic circuit +1 and a first controller RCA CTL1, and the second adder RCA2 is a second adding logic circuit +2 and a second controller. The third adder RCA3 includes a first adding logic circuit +2 and a third controller RCA CTL3. The adders RCA1 to RCA3 according to the present exemplary embodiment consist of three adders having each correlation value as an input value corresponding to each of the three correlation values. However, when the number of correlation values is different, the number of adders is changed correspondingly. Of course it can.

Here, the functions of the addition logic circuits +1 to +3 are the same as the addition logic circuit ADD described with reference to FIG. 4. On the other hand, the controllers RCA CTL1 to RCA CTL3 actively control the memory of each of the addition logic circuits +1 to +3 to control the use of the memory to a minimum. The specific operation of the adder of this embodiment will be described together with the memory of FIG.

FIG. 6 is a diagram illustrating a memory included in the addition logic circuit of FIG. 5. For convenience of understanding, the present invention will be described with reference to FIG. 5.

Referring to FIG. 6, the addition logic circuits +1 to +3 include memories A1 to A3 to perform a cumulative operation. That is, the first addition logic circuit (+1) has a first memory (│A1│), the second addition logic circuit (+2) has a second memory (│A2│), and the third addition logic The circuit +3 may include a third memory | A3 |. Here, MSB means Most Significant Bit and LSB means Least Significant Bit. Such memories (+1 ~ +3) are preferably all configured in the same size, but of course it can be configured in a different size. However, in the case of different sizes, the cumulative calculation should not exceed the size of the smallest memory. On the other hand, while the above has been described that each of the addition logic circuit has a memory, it can be configured that the memory is disposed outside the addition logic circuit to use the memory when the addition logic circuit performs the addition operation.

Referring to the operation of the adders RCA1 to RCA3 of FIG. 5 again with these memories,

The addition logic circuits +1 to +3 add the input values IN1 to IN3 and the corresponding storage values OUT1 to OUT3 for the corresponding correlation values to add the accumulated values A1 to A3. Will output At this time, the stored values OUT1 to OUT3 and the accumulated values A1 to A3 are merely distinguished for convenience of description and have the same value. That is, the cumulative values A1 to A3 when the cumulative values A1 to A3 are inputted to the corresponding addition logic circuits +1 to +3 again are only referred to as the stored values OUT1 to OUT3. .

The memories │ A1 │ ˜ A3 │ store cumulative values A1 ˜ A3 of corresponding addition logic circuits + 1 ˜ + 3. That is, the first memory │ A1 │ stores the cumulative value A1 of the first adding logic circuit +1, and the second memory │ A2│ stores the cumulative value of the second adding logic circuit +2. Save the value A2. Similarly, the third memory | A3 | stores the accumulated value A3 of the third addition logic circuit +3.

The controllers RCA CTL1 to RCA CTL3 accumulate the cumulative values A1 to A3 of all the memories A1 to A3 when the cumulative value stored in any memory becomes more than a predetermined value. The shifted direction is reduced, and the input values IN1 to IN3 are also shifted by shifting the accumulated value. In addition, the controllers RCA CTL1 to RCA CTL3 transfer the shifted accumulated values A1 to A3 and the input values IN1 to IN3 to corresponding addition logic circuits +1 to +3.

At this time, the controllers RCA CTL1 to RCA CTL3 may be provided in each of the addition logic circuits +1 to +3. Thus, as shown in FIG. 5, three adders RCA1, RCA2, RCA3 are applied to the three adding logic circuits +1 to +3 and the respective adding logic circuits +1 to +3. Three controllers RCA CTL1 to RCA CTL3 may be provided. However, each of the controllers RCA CTL1 to RCA CTL3 should be able to know information about accumulated values A1 to A3 of all memories A1 to A3.

On the other hand, while the above has been described that each of the addition logic circuit has a memory, the memory may be configured such that the memory is disposed outside the addition logic circuit to use the memory when the addition logic circuit performs the addition operation.

Hereinafter, the operation of the adder according to an embodiment of the present invention will be described in more detail with reference to specific examples.

FIG. 7 is a diagram illustrating a process of shifting a cumulative value in a memory to explain the operation of the adder of FIG. 5, (a) shows cumulative values stored in each memory before the shift, and (b) after a shift. The cumulative values stored in each memory are shown. For convenience of understanding, the present invention will be described with reference to FIG. 5.

Referring to FIG. 7, each of the illustrated memories A1 to A3 has a size of 16 bits. As described above, the addition logic circuits +1 to +3 add the input values IN1 to IN3 and the stored values OUT1 to OUT3 and output the accumulated values A1 to A3.

When the controllers RCA CTL1 to RCA CTL3 have a value k (k is a natural number) of the most significant i bits of the cumulative value stored in any one of the memories │ A1 │ │ A3 │, Compare the cumulative values of the remaining memories except for. When the position of the most significant bit having a logic "high", that is, '1', of each bit of the memory having the largest accumulated value among the remaining memories is N (N is a natural number), the controllers RCA CTL1 to RCA CTL3 Next, the current accumulation values A1 to A3 are shifted by N corresponding to the direction in which the accumulation values decrease in each of the memories A1 to A3.

For example, the controller RCA CTL1 to RCA CTL3 according to an embodiment of the present invention performs a shifting operation when i is 2 and k is '1', that is, when the most significant two bits have a value of "01". Let's do it. Then, it is assumed that the cumulative values A1 to A3 stored in each of the memories A1 to A3 at a predetermined time point are as shown in (a). That is, the cumulative value A1 of the first memory │ A1 │ is “01xxxxxxxxxxxxx”, the cumulative value A2 of the second memory │ A2│ is “00000001xxxxxxx”, and the third memory │ A3│. Let cumulative value A3 be " 0000000001xxxxx ". At this time, "x" may represent a value of "0" or "1".

The controllers RCA CTL1 to RCA CTL3 detect that the most significant two bits of the cumulative value A1 stored in the first memory | A1 | have a value of "01". Thereafter, the controllers RCA CTL1 to RCA CTL3 compare the cumulative values of the second memory │ A2 │ and the third memory │ A3 │ except for the first memory │ A1 │. In this case, the comparison of the cumulative values may be performed by receiving cumulative value information from other controllers in all controllers, or may be performed integrally by receiving cumulative value information from another controller in one controller.

In the example of (a), the cumulative value A2 of the second memory | A2 | is larger than the cumulative value A3 of the third memory | Accordingly, the controllers RCA CTL1 to RCA CTL3 find the position "N" of the most significant bit having a value of "1" of each bit of the cumulative value A2 of the second memory |

As a result, the position "N" of the most significant bit having the value of "1" of each bit of the cumulative value A2 of the second memory | A2 | is "9". However, since the least significant bit LSB of the memory is counted from " 0 ", it is shown as if the value of the most significant " 1 "

When the controllers RCA CTL1 to RCA CTL3 obtain a value of "N" by the above operation, the controllers RCA CTL1 to RCA CTL3 store all accumulated values A1 to R1 in the memories A1 to R3. Shift A3) in the least significant bit direction by " N-1 ". In addition, the input values IN1 to IN3 are also shifted in the least significant bit direction by "N-1". In this case, "N-1" is exemplary and is not limited thereto. However, when N or more, the cumulative values of the second memory (│A2│) and the third memory (│A3│) become “0”. It is preferable to set the shift amount to "N-1" or less.

As a result, it can be seen that the cumulative values A1 to A3 shown in (a) are shifted by "8" in the least significant bit LSB direction as shown in (b). Although not shown, the shifting results for the input values IN1 to IN3 are similar to the shifting results of the cumulative values. That is, each input value is also shifted by "8" in the least significant bit (LSB) direction.

The controllers RCA CTL1 to RCA CTL3 repeat the above shifting operation M (M is a natural number) at the time of calculating the cumulative correlation value, and then stores the cumulative value of the memory having k values of the most significant i bits of the cumulative value. Output as maximum cumulative value. At this time, M may be set in advance by the user or the system designer before the adding operation.

As described above, the adder according to the embodiment of the present invention may further perform the addition operation through the shifting operation even if the capacity of one memory is full, and thus the input value and the accumulated value smaller than the actual correlation value may be applied. The maximum cumulative value can be obtained, and the addition speed can be increased. Furthermore, the adder according to the embodiment of the present invention can prevent a change in the operating speed of the system according to the magnitude of the correlation value.

As described above, when the FFT mode is detected through the first mode detector, the symbol size of the received OFDM signal can be known. Next, the start point of the valid symbol should be found by detecting the GI mode to obtain the length of the guard interval. The GI mode detection may be performed by the second mode detector 440 in FIG. 3. Hereinafter, the second mode detector 400 will be described with reference to FIG. 8.

8 is a block diagram illustrating in detail the second mode detector of FIG. 3.

Referring to FIG. 8, the second mode detector 440 may delay the selection correlation value SCORR corresponding to the detected FFT mode MOD1 among the first correlation values CORR1, CORR2, and CORR3. The second mode MOD2 of the received signal InSIG is detected using the signals DSIG21 to DSIG26 and the selection correlation value SCORR corresponding to the FFT mode MOD1. In this case, the second mode MOD2 may be a GI mode. Hereinafter, the case where the second mode is the GI mode will be described.

In order to detect the GI mode MOD2, the second mode detector 440 may include the first selection circuit MUX1, the second delay circuits DLY21 to DLY26, the second selection circuits MUX21 to MUX24, and the accumulated value. A calculator ACC and a second mode detector MOD2 DETC may be provided.

The first selection circuit MUX1 selects and outputs one selection correlation value SCORR among the first correlation values CORR1, CORR2, and CORR3 in response to the FFT mode MOD1.

The second delay circuits DLY21 to DLY26 delay the selection correlation value SCORR to generate second delay signals DSIG21 to DSIG26. Preferably, the second delay circuits DLY21 to DLY26 may be provided in a number corresponding to the type of the FFT mode MOD1.

The second selection circuits MUX21 to MUX24 output one delay signal among the input second delay signals DSIG21 to DSIG26 in response to the detected FFT mode MOD1 and the corresponding GI mode. As described above, the GI mode may have one of 1/4, 1/8, 1/16 and 1/32.

For example, the twenty-first delay circuit DLY21 and the twenty-second delay circuit DLY22 delay the input signal by 64 samples, and the twenty-third delay circuit DLY23 delays the 128 signals by 24 samples. DLY24) delays by 256 samples. Similarly, it is assumed that the 25 th delay circuit DLY25 delays 512 samples and the 26 th delay circuit DLY26 delays 1024 samples.

As a result, the twenty-first delay signal DSIG21, which is the output of the twenty-first delay circuit DLY21, is delayed by 64 samples from the first correlation value SCORR, and the twenty-second delay signal DLY22, which is the output of the twenty-second delay circuit DLY22, is delayed. The DSIG22 may be delayed by 128 samples, and the 23rd delay signal DSIG23 which is an output of the 23rd delay circuit DLY23 may be delayed by 256 samples. Similarly, the 24 th delay signal DSIG24, which is the output of the 24 th delay circuit DLY24, is delayed by 512 samples from the first correlation value SCORR, and the 25 th delay signal DSIG25, which is the output of the 25 th delay circuit DLY25. ) May be delayed by 1024 samples, and the 26th delay signal DSIG26, which is an output of the 26th delay circuit DLY26, may be delayed by 2048 samples.

As described above, the second selection circuits MUX21 to MUX24 may output one of the second delayed signals as described above by the type of the corresponding GI mode and the detected FFT mode, respectively.

For example, it is assumed that the twenty-first selection circuit MUX21 of FIG. 8 corresponds to 1/32 GI mode, and the twenty-second selection circuit MUX22 corresponds to 1/16 GI mode. Similarly, it is assumed that the twenty-third selection circuit MUX23 corresponds to the 1/8 GI mode, and the twenty-fourth selection circuit MUX24 corresponds to the 1/4 GI mode.

At this time, the twenty-first selection circuit MUX21, which receives the twenty-first delay signals DSIG21 to 23rd delay signals DSIG23, receives a delay signal of 64 (= 2K / 32) samples when the FFT mode is 2K. Outputs (DSIG21), outputs the 22nd delayed signal DSIG22, which is 128 (= 4K / 32) sample delayed when the FFT mode is 4K, and delays 256 (= 8K / 32) samples, when the FFT mode is 8K. The twenty-third delay signal DSIG23 may be output.

Similarly, the twenty-second selection circuit MUX22 that inputs the twenty-second delay signals DSIG22 to 24 th delay signals DSIG24 has a 22nd delay signal delayed by 128 (= 2K / 16) samples when the FFT mode is 2K. Outputs (DSIG22) and outputs the 23rd delayed signal (DSIG23) which is 256 (= 4K / 16) samples delayed if the FFT mode is 4K, and 512 (= 8K / 16) samples that are delayed if the FFT mode is 8K. The 24 th delay signal DSIG24 may be output.

The cumulative value calculator ACC performs a subtraction and iterative addition operation on the output of the selection correlation value SCORR and the second selection circuits, and calculates a correlation value for each GI mode as a cumulative value. The cumulative value calculator (ACC) is a device for performing a moving sum, and is related to matters that can be easily performed by those skilled in the art of the present invention, and a detailed description thereof will be omitted. do.

The second mode detector MOD2 DETC detects the GI mode MOD2 from the accumulated value for the first correlation value SCORR.

9 is a flowchart illustrating an operation of the second mode detector of FIG. 8. For convenience of understanding, the following description will be made with reference to FIG. 8.

Referring to FIG. 9, the second mode detector MOD2 DETC first initializes each variable, that is, count, first to third maximum values, and the like (S901), and then, in the second mode, that is, the GI mode. In order to detect the received value, the accumulated value output from the accumulated value calculator (ACC) is received (S902), and the received accumulated value is indicated as "Input_data". When the cumulative value Input_data is received, first, a count of the cumulative value Input_data is compared with a preset estimated range value t (S910). Here, the count is initially set to "0", and is a variable that continues to increase by "1" until the estimated range value t, and corresponds to the sample index of the accumulated value.

Next, when the count is less than or equal to the estimated range value t, the cumulative value is classified into the magnitude order by comparing the cumulative value with the maximum value according to the magnitude order (S920, S930, and S940). That is, first, the cumulative value is compared with the first maximum value (S920), and when the value is larger than the first maximum value, the cumulative value is input to the first maximum value to set the first maximum value (S922). In the first maximum value setting step S922, a process of setting a first maximum value index by inputting a count to the first maximum value index Max_index is also performed.

On the other hand, when the cumulative value is less than or equal to the first maximum value, the cumulative value is compared with the second maximum value (S930), and when the cumulative value is larger than the second maximum value, the cumulative value is input to the second maximum value. The second maximum value is set (S932). In the second maximum value setting step S932, a process of setting a second maximum value index by inputting a count to the second maximum value index Second_Max_index is also performed.

When the cumulative value is less than or equal to the second maximum value, the cumulative value is compared with the third maximum value (S940), and when the cumulative value is larger than the third maximum value, the cumulative value is input to the third maximum value. The third maximum value is set (S942). In the third maximum value setting step S942, a process of setting a third maximum value index is also performed by inputting a count to the third maximum value index Third_index.

Here, the first to third maximum values and the first to third maximum value indices are already set when starting the second mode detection as described above. These first to third maximum values and the first to third maximum value indices may be set to any value at first with continuously changing values. However, it is obvious that the first to third maximum values should be set in order of magnitude.

In the present embodiment, the first maximum value Max to the third maximum value Third_Max are exemplified, but the maximum value classification may be more than that.

After the maximum value and maximum value index setting step (S922, S932, S942), the count value is increased to "1" (S950), and the above process is repeated. Here, the cumulative value is compared with the third maximum value, and even when the cumulative value is smaller than or equal to the third maximum value, the process proceeds to the count value increasing step S950. This comparison and setting step is continued until the count exceeds the estimated range value t. Here, the estimated range value t may be set to an appropriate value, but in order to detect an effective GI mode, the estimated range value t may be set to about the number of samples included in four symbols.

Through the above process, the maximum values dominant in the GI mode portion are input to the first to third maximum values, and indices corresponding to the indexes of the GI mode portion are also input to the first to third maximum value indexes. Will be. This result is a necessary result of the moving island in the cumulative value calculator (ACC) through the signal delay.

If the count is greater than the estimated range value t, a new variable corresponding to the difference between the indices is set (S960). That is, the absolute value of the value obtained by subtracting the first maximum value index from the second maximum value index is input to the 21st order index (Index2_Index1). In other words, the absolute value of the value obtained by subtracting the second maximum value index from the third maximum value index is input to the 32nd order index (Index3_Index2).

Next, the 21 st order and the 32 nd order index are compared with the lengths (F = 2K, 4K, ...) of the FFT mode detected by the first mode detector 420 (S970). In general, as mentioned above, the first to third maximum indexes appear in the GI mode, and thus, the 21st or 32nd order indices, which are the differences between the maximum value indices, are longer than the length of the FFT mode. Therefore, in the comparison with the FFT mode (S970), when both the 21st index and the 32nd index are longer than the length of the FFT mode (Yes), it is assumed that the GI mode is normally detected, and the GI mode is calculated. The process proceeds to S990. If not (No), that is, if either the 21st index or the 32nd index is smaller than the FFT mode length, the GI mode detection is regarded as failed, and the count is reset to “0” to estimate the estimated range. Returning to the value t and comparing step S910, the GI mode detection process is started again.

On the other hand, if it is determined that the normal GI mode is detected, the GI mode is calculated by summing the value obtained by subtracting the FFT mode length from the 21st index and the value obtained by subtracting the FFT mode length from the 32nd index, and dividing by 2 to calculate the GI mode. do. Here, the value obtained by subtracting the length of the FFT mode from the 21st index or the length obtained by subtracting the length of the FFT mode from the 32nd index may be set to the GI mode. It is preferable.

In the present embodiment, a case where the above operation is repeated t times in particular is illustrated. In this case, since the accumulated value calculator ACC of FIG. 8 transmits the outputs for the four GI mode types to the second mode detector MOD2 DETC, the operation as described above in the second mode detector according to the embodiment of the present invention. Reliability can be secured by comparing four cumulative values for each of the four GI mode types.

When the OFDM receiver of the present embodiment detects the FFT mode and the GI mode through the above operation, the start points of the valid symbols may be calculated by adding the length of the guard interval according to the GI mode determined from the maximum value index. Symbol units can be distinguished. In addition, by performing FFT transform on each symbol from the start point of the valid symbol, input data such as Equation 2 may be estimated.

As described above, the OFDM receiver and the mode detection method thereof according to the present invention can perform accurate and fast mode detection by first detecting the FFT mode for the same signal and then detecting the GI mode using the result. Chip size can be reduced.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to more fully understand the drawings recited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a transmitter and a receiver of an OFDM communication system.

2 is a diagram briefly illustrating a method for setting a guard interval in an OFDM system.

3 is a block diagram illustrating an OFDM receiver according to an embodiment of the present invention.

4 is a structural diagram illustrating a general addition logic circuit that may be used in the adders RCA1 to RCA3 of the first mode detector of FIG. 3.

FIG. 5 is a structural diagram illustrating an adder having a configuration different from that of FIG. 4, which may be used in the adders RCA1 to RCA3 of the first mode detector of FIG. 3.

FIG. 6 is a diagram illustrating a memory included in the addition logic circuit of FIG. 5.

FIG. 7 is a diagram illustrating a process of shifting a cumulative value in a memory to explain an operation of the adder of FIG. 5.

8 is a block diagram illustrating in detail the second mode detector of FIG. 3.

9 is a flowchart illustrating an operation of the second mode detector of FIG. 8.

Claims (20)

Detecting a first mode of the received signal using first delayed signals that delay the received signal a predetermined delay and first correlation values for the received signal; And A second mode of the received signal by using second delay signals having a predetermined delay of a first correlation value corresponding to the first mode among the first correlation values and a first correlation value corresponding to the first mode Detecting a mode; mode detection method in an OFDM receiver. The method of claim 1, Detecting the first mode of the received signal, Obtaining cumulative values for the first correlation values; Calculating a maximum cumulative value among the accumulated values; And And detecting the first mode from the maximum cumulative value. The method of claim 1, The first delay signals, And a mode corresponding to the type of the first mode. The method of claim 1, The detecting of the second mode may include: Selecting a corresponding second delay signal among the second delay signals according to the detected first correlation value corresponding to the first mode; Calculating a cumulative value for the second mode by subtracting and adding the selected second delay signal and the first correlation value; And And detecting the second mode from the calculated cumulative value. The method of claim 4, wherein The detecting of the second mode from the calculated cumulative value may include: Receiving the cumulative value; Obtaining a maximum value of a first maximum value to i (i is a natural number of two or more) in the order of magnitude among the cumulative values; And Obtaining a first maximum value index to an ith maximum value index for the first maximum value to the ith maximum value; And a mode detection method in an OFDM receiver. The method of claim 5, wherein The detecting of the second mode from the calculated cumulative value may include: And increasing the count value by one after the step of obtaining the first to i-th maximum value indices. The method of claim 5, wherein The detecting of the second mode from the calculated cumulative value may include: Comparing a count corresponding to the index of the accumulated value with a preset estimated range value t; And And comparing an absolute value of a difference between two indices of the first maximum value index to the ith maximum value index and a size of the first mode. If the count is less than the estimated range value t, the process proceeds to obtaining a maximum value, and if the count is greater than the estimated range value t, the process proceeds to comparing the magnitude with the first mode. A mode detection method in an OFDM receiver. The method of claim 7, wherein The detecting of the second mode from the calculated cumulative value may include: If the absolute value of the difference between any two indexes among the first maximum value index and the i maximum value index is smaller than the first mode, the second mode detection is regarded as failed, the count value is initialized, and the accumulation is performed. To receive the value, And if it is larger than the first mode, shifting to a second mode calculating step. The method of claim 8, In the second mode calculating step, And calculating the first mode as an average value of values obtained by subtracting the first mode from an absolute value of a difference between any two indices of the first to i-th indexes. The method of claim 5, wherein The detecting of the second mode from the calculated cumulative value may include: And the first to i th maximum values are reset whenever the cumulative value is received. The method of claim 1, The first mode is an FFT mode, And the second mode is a GI mode. The method of claim 1, The second delay circuits, And a number corresponding to the type of the first mode and the second mode. The method of claim 1, The first mode has a value of one of 2K, 4K, and 8K, And the second mode has one of 1/4, 1/8, 1/16, and 1/32. A first mode detector configured to detect a first mode of the received signal by using first delayed signals delaying a received signal and first correlation values of the received signal; And A second mode of the received signal by using second delay signals having a predetermined delay of a first correlation value corresponding to the first mode among the first correlation values and a first correlation value corresponding to the first mode And a second mode detector for detecting a signal. The method of claim 14, The first mode detector, First delay circuits for delaying the received signal to generate the first delay signals; A conjugator for obtaining a conjugate signal of the received signal; Multipliers for multiplying a corresponding first delayed signal among the first delayed signals and the conjugate signal to output the first correlation values;  Adders for obtaining a cumulative value for a corresponding first correlation value among the first correlation values; And And a first mode detector for calculating a maximum cumulative value among the cumulative values and detecting the first mode from the maximum cumulative value. The method of claim 14, The first delay circuits, OFDM receiving apparatus, characterized in that provided in the number corresponding to the type of the first mode. The method of claim 14, The second mode detector, A first selection circuit outputting a first correlation value of one of the first correlation values in response to the first mode; Second delay circuits for delaying the selected first correlation value to generate the second delay signals; Second selection circuits for outputting a delay signal of one of the second delay signals in response to the first mode; A cumulative value calculating unit configured to subtract and add a second delay signal selected by the second selection circuits and the selected first correlation value to calculate a cumulative value for the first correlation value; And And a second mode detector for detecting the second mode from the calculated cumulative value. The method of claim 16, The second mode detector, The cumulative values are received from the cumulative value calculating unit, and the cumulative values are calculated according to a first order to i (a natural number of i 2 or more) maximum values and the first to i maximum values according to the order of magnitude. After obtaining the first maximum value index to the ith maximum value index, And the second mode is detected by comparing the absolute value of the difference between any two indexes among the first maximum value index and the ith maximum value index with the first mode. The method of claim 18, The second mode detector, And an average value of values obtained by subtracting the first mode from the absolute value of the difference between any two indexes among the first maximum value index and the i maximum value index is calculated as the second mode. The method of claim 14, The first mode is an FFT mode, And the second mode is a GI mode.

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