KR20090110040A - Liquid Crystal Display - Google Patents

Abstract

PURPOSE: A liquid crystal display for improving the characteristic of a capacitor is provided to form a charge on an active layer and a gate insulating layer of a full-up transistor. CONSTITUTION: A liquid crystal display includes a sub pixel, data driver, and a scan driver. The sub pixel is located on a substrate(110). The data driver supplies data signal to data line of the sub pixel. The scan driver supplies the scan signal to the scan wiring of the sub pixel. The output terminal of the scan driver includes the pull-up transistor and upper electrode. The pull-up transistor includes the gate, the first insulating layers, the active layer, a drain and source, and the second insulating layers. The gate is located on surface of the substrate. The first insulating layer is located on surface the gate. The active layer is located on surface the first insulating layers.

Description

Liquid Crystal Display

The present invention relates to a liquid crystal display device.

Liquid crystal display devices are widely used in display devices of office equipment, monitors of computers, and even large-screen televisions with the development of recent process and driving technologies.

In the liquid crystal display panel of the liquid crystal display device, subpixels are arranged in a matrix type, and data wires to which a data signal is supplied and scan wires to which a scan signal are supplied cross.

The scan driver of the liquid crystal display includes a level shifter for shifting the swing width of the scan signal to a level suitable for driving the subpixels, and a shift register for sequentially outputting the scan signal. Here, the output stage of the shift register includes an output buffer using a pull-up transistor to supply a scan signal to each sub-pixel.

The scan driver formed on the basis of the conventional a-Si forms a capacitor between the gate and the source or drain terminal for the purpose of stably driving the pull-up transistor. The capacitor connected to the structure of the conventional pull-up transistor is formed into a structure including a gate of the pull-up transistor, a gate insulating film, an active layer of a-Si, a source and a drain.

The problem with such a structure is that when the circuit operates for a long time, the capacitance of the capacitor decreases as the threshold voltage of the capacitor increases. In other words, even if the scan signal of the pull-up transistor is always constant, since the active layer of a-Si is positioned in the capacitor, the capacity of the capacitor decreases when deterioration continues.

Therefore, if such a problem continues to occur, the conventional a-Si-based liquid crystal display has a charge trapped or a defect in the gate insulating film and the active layer of the pull-up transistor included in the output terminal of the shift register. Since the characteristics of the capacitor are degraded due to the deterioration of the built-in circuit, the life of the scan driver is reduced.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems of the background art is that a charge is trapped or defects in a gate insulating film and an active layer of a pull-up transistor included in a scan driver of an a-Si-based liquid crystal display. ) Is formed and the characteristics of the capacitor deteriorate, thereby reducing the reliability of the embedded circuit.

The present invention as a means for solving the above problems, the sub-pixel located on the substrate; A data driver supplying a data signal to a data line of a sub pixel; And a scan driver configured to supply a scan signal to the scan wiring of the subpixel, wherein an output terminal of the scan driver includes a gate positioned on the substrate, a first insulating layer positioned on the gate, and an active layer positioned on the first insulating layer. A pull-up transistor comprising a layer, a drain and source positioned on the active layer, and a second insulating layer positioned on the drain and source, a gate, a first insulating layer, and a second insulating layer; The present invention provides a liquid crystal display including a capacitor including an upper electrode connected to a drain or a source.

The capacitor may be located apart from the pull-up transistor.

The capacitor may further include a second insulating layer positioned between the first insulating layer and the upper electrode.

The upper electrode may be formed by the same process as the pixel electrode included in the subpixel.

The second insulating layer includes a first contact hole exposing a drain or source included in the pull-up transistor, and a second contact hole exposing the first insulating layer, and the upper electrode is connected to the drain or source through the first contact hole. Contact the gate and the first insulating layer corresponding to the gate through the second contact hole.

The second insulating layer includes a first contact hole exposing a drain or source included in the pull-up transistor, and the upper electrode contacts the drain or source through the first contact hole and contacts the gate and the second insulating layer corresponding to the gate. can do.

The pull-up transistor may be included in the shift register of the scan driver.

The pull-up transistor may include an ohmic contact layer positioned between the active layer and the drain and the source.

The active layer may be a-Si.

According to the present invention, charges are trapped or defects in the gate insulating layer and the active layer of the pull-up transistor by changing the structures of the pull-up transistor and the capacitor located at the output terminal of the scan driver of the a-Si-based liquid crystal display. Is formed and the characteristics of the capacitor are deteriorated, thereby reducing the reliability of the embedded circuit and improving the life and reliability of the circuit.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

First Embodiment

1 is a schematic plan view of a liquid crystal display according to the present invention.

As illustrated in FIG. 1, the liquid crystal display may include a display unit AA on which a plurality of sub pixels P are positioned on the substrate 110. The subpixel P may be driven by the driving units DRV1 and DRV2 to represent an image.

The driving units DRV1 and DRV2 are connected to the scan line of the subpixel P to supply a scan signal, and the data driver DRV2 is connected to the data line of the subpixel P to supply a data signal. ) May be included. Here, the data driver DRV1 and the scan driver DRV2 are only schematically illustrated and are not limited to the illustrated positions.

The scan driver DRV1 may include a level shifter for shifting the swing width of the scan signal to a level suitable for driving the subpixel P, and a shift register for sequentially outputting the scan signal.

In the present invention, the level shifter included in the scan driver DRV1 is located outside the substrate 110 and the shift register is a GIP (Gate in Panel) method located on the substrate 110.

The data driver DRV2 may be connected to the subpixel P positioned on the substrate 110 using a tape carrier package (TCP) or a flexible printed circuit (FPC).

Hereinafter, a schematic structure of the sub pixel P shown in FIG. 1 will be described.

2 is a schematic plan view of a subpixel, and FIG. 3 is a cross-sectional view of an area A1-A2 of FIG. 2. Here, the exemplary diagram of the subpixel of FIG. 2 is only for explaining an example of an embodiment, and the present invention is not limited thereto. However, the liquid crystal cell is omitted due to the characteristics of the drawings.

As illustrated in FIG. 2, the subpixel P may be positioned in an intersection area of the scan line 170, the data line 180, and the common voltage line 190 that cross each other.

In the region where the scan line 170 and the data line 180 cross each other, the transistor T is positioned and the pixel electrode 160 connected to the drain or source of the transistor T may be positioned.

The common electrode 140 connected to the common voltage line 190 may be positioned on one surface of the pixel electrode 160 that faces the pixel electrode 160. The common electrode 140 connected to the common voltage wire 190 may be connected through the via hole VH, but is not limited thereto. Here, the common voltage line 190 and the common electrode 140 may form a capacitor by sandwiching an insulating layer therebetween.

Hereinafter, the transistor T shown in FIG. 2 will be described with reference to FIG. 3.

The transistor T may include a gate 106 positioned on the buffer layer 105 formed on the substrate 110. In addition, the first insulating layer 115 may be disposed on the gate 106. In addition, the active layer 120a may be disposed on the first insulating layer 112. In addition, an ohmic contact layer 120b may be included in each of the source and drain regions defined on the active layer 120a. In addition, a drain 121 and a source 122 contacting the active layer 120a and the ohmic contact layer 120b may be included. In addition, the second insulating layer 130 may be disposed on the drain 121 and the source 122. The pixel electrode 160 may be disposed on the second insulating layer 130 exposing one of the drain 121 and the source 122 and connected to the drain 121 and the source 122.

Here, the gate 106 may be connected to the scan line 170, and the drain 121 or the source 122 may be connected to the data line 180.

Hereinafter, the scan driver described above will be described in more detail with reference to FIGS. 4 and 5.

4 is a schematic diagram illustrating an example of a scan driver, and FIG. 5 is a diagram illustrating a circuit configuration of an output terminal of the shift register illustrated in FIG. 4.

Referring to FIG. 4, the scan driver may include a level shifter LS for moving the swing width of the scan signal to a level suitable for driving the subpixel P. Referring to FIG. In addition, a shift register SR for sequentially outputting scan signals in association with the level shifter LS may be included.

The output terminals S1..Sn of the shift register SR are connected to the scan wirings of the subpixels, and the scan signals output from the output terminals S1..Sn of the shift register SR are sequentially scanned line by line.

The output terminal of the shift register includes an output buffer using a pull-up transistor to supply a scan signal to each sub-pixel P.

Referring to FIG. 5, a circuit configuration of a part of the output terminal S1 shown in the Z region of FIG. The output terminal S1 is electrically connected to the pull-up transistor T1, the capacitor C connected to the gate and one end of the pull-up transistor T1, and the pull-down transistor T2.

Here, the other end of the pull-up transistor T1 is connected to the clock voltage Vc1, and one end of the pull-down transistor T2 is connected to the reference voltage Vss. Due to such a circuit configuration, the output terminal S1 of the shift register has a voltage applied to the clock voltage Vc1 or the reference voltage Vss while the pull-up transistor T1 or the pull-down transistor T2 is turned on every time a clock signal is supplied. Outputs the voltage applied to).

Hereinafter, the cross-sectional structure of the pull-up transistor and the capacitor shown in FIG. 5 will be described in more detail.

6 is a cross-sectional structural view of the pull-up transistor and the capacitor illustrated in FIG. 5, and FIG. 7 is a schematic structural diagram of the capacitor of FIG. 6.

The pull-up transistor and the capacitor illustrated in FIG. 6 may be formed through the same process as the transistor included in the subpixel. Therefore, the cross-sectional structure of the pull-up transistor and the capacitor illustrated in FIG. 6 will be described with reference to the drawings of FIG.

Referring to FIG. 6, the pull-up transistor includes a gate 108, a first insulating layer 115 positioned on the gate 108, and an a-Si active layer 120a positioned on the first insulating layer 115. And a drain 121 and a source 122 disposed on the active layer 120a and a second insulating layer 130 located on the drain 121 and the source 122.

The process of forming the pull-up transistor may use a four mask process using four masks, but is not limited thereto.

The gate 108 may be located on the buffer layer 105 positioned on the substrate 110. The gate 108 is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be made of one or an alloy thereof. In addition, the gate 108 is formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer made of any one or alloys thereof. In addition, the gate 108 may be a bilayer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating film 115 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

The drain 121 and the source 122 may be formed of a single layer or multiple layers. When the drain 121 and the source 122 are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and gold may be used. (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof. In addition, when the drain 121 and the source 122 are multiple layers, the double layer of molybdenum / aluminum-neodymium and the triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The second insulating layer 130 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating layer 130 may be a passivation layer.

The capacitor may include a gate 108, a first insulating layer 115, and an upper electrode 160 positioned on the second insulating layer 130 and connected to the drain 121 or the source 122.

The upper electrode 160 may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

Although the gate 108 positioned on the buffer layer 105 is an example in which some portions are formed at different heights in different layers, they may be formed at the same height. However, in forming the gate 108, the shape of the gate 108 is not limited so long as the width of the gate 108 is wide enough to allow the pull-up transistor and the capacitor to be spaced apart from each other.

The active layer 120a on the first insulating layer 115 may be a-Si: H, which is hydrogenated amorphous silicon, such as an active layer of a transistor included in a subpixel. The ohmic contact layer 120b may be positioned on the active layer 120a to reduce contact resistance between the active layer 120a, the drain 121, and the source 122.

Meanwhile, the second insulating layer 130 may include a first contact hole H1 exposing the drain 121 or the source 122 included in the pull-up transistor, and a second contact hole exposing a portion of the first insulating layer 115. (H2) may be included.

Accordingly, the upper electrode 160 is in contact with the drain 121 or the source 122 through the first contact hole H1 and in contact with the first insulating layer 115 through the second contact hole H2. It may be positioned on the second insulating layer 130.

In this case, as shown in FIG. 7, the capacitor is positioned in a form including a gate 108, a first insulating layer 115, and an upper electrode 160. That is, the capacitor thus formed uses the first insulating film 115 as a dielectric and the gate 108 and the upper electrode 160 as electrodes.

The upper electrode 160 may be formed by the same process as the pixel electrode included in the subpixel. In such a structure, when forming a transistor included in a sub-pixel, it is possible to simultaneously form a pull-up transistor and a capacitor without additional processing.

On the other hand, according to the structure of the pull-up transistor as described above, the gate of the pull-up transistor may be subjected to a voltage (VQ) as shown in Equation 1 below by clock coupling.

Where Cgs is the capacitance between the gate 108 and the source 122 of the transistor, Cgd is the capacitance between the gate 108 and the drain 121 of the transistor, and V _clk is supplied from the outside to the gate 108 of the transistor. It may be a voltage of a clock signal.

Here, even if the pull-up transistor included in the shift register is operated for a long time and deterioration is continued, the capacitor can maintain a constant capacitance.

According to Equation 1 above, since Cgd decreases and Cgs have the same value, Cgd (Cgd + Cgs) decreases, thereby reducing the VQ voltage due to clock coupling.

Hereinafter, the cross-sectional structure according to the second embodiment of the pull-up transistor and the capacitor shown in FIG. 5 will be described in more detail.

Second Embodiment

8 is another cross-sectional structural view of a pull-up transistor and a capacitor, and FIG. 9 is a schematic structural diagram of the capacitor of FIG. 8.

Referring to FIG. 8, the pull-up transistor includes a gate 208, a first insulating layer 215 disposed on the gate 208, and an a-Si active layer 220a disposed on the first insulating layer 215. And a drain 221 and a source 222 on the active layer 220a and a second insulating layer 230 on the drain 221 and the source 222.

The gate 208 may be located on the buffer layer 205 positioned on the substrate 210. The gate 208 is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It may be made of one or an alloy thereof. In addition, the gate 208 is formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer made of any one or alloys thereof. In addition, the gate 208 may be a bilayer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating layer 215 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto.

The drain 221 and the source 222 may be formed of a single layer or multiple layers. When the drain 221 and the source 222 are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and gold may be used. (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof. In addition, when the drain 221 and the source 222 are multiple layers, the double layer of molybdenum / aluminum-neodymium and the triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The second insulating layer 230 may be a silicon oxide film SiOx, a silicon nitride film SiNx, or a multilayer thereof, but is not limited thereto. The second insulating layer 230 may be a passivation layer.

The capacitor may include a gate 208, a first insulating layer 215, and an upper electrode 260 positioned on the second insulating layer 230 and connected to the drain 221 or the source 222. The upper electrode 260 may be one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

The gate 208 positioned on the buffer layer 105 is an example in which a part of the gate 208 is formed at different heights in different layers, but it may be formed at the same height. However, when the gate 208 is formed, the shape of the gate 208 is widened so that the pull-up transistor and the capacitor can be spaced apart from each other.

Here, the active layer 220a positioned on the first insulating layer 215 may be a-Si: H, which is oxidized amorphous silicon, such as an active layer of a transistor included in a subpixel, and is active on the active layer 220a. The ohmic contact layer 220b may be positioned to reduce contact resistance between the layer 220a and the drain 221 and the source 222.

The second insulating layer 230 may include a first contact hole H1 exposing the drain 221 or the source 222 included in the pull-up transistor.

Accordingly, the upper electrode 260 may be positioned on the second insulating layer 230 corresponding to the gate 208 in the form of contacting the drain 221 or the source 222 through the first contact hole H1. have.

In this case, as shown in FIG. 9, the capacitor is positioned to include a gate 208, a first insulating layer 215, a second insulating layer 230, and an upper electrode 260. That is, the capacitor formed as described above uses the first insulating layer 215 and the second insulating layer 230 as a dielectric, and the gate 208 and the upper electrode 260 as electrodes.

On the other hand, the upper electrode 260 may be formed by the same process as the pixel electrode included in the sub-pixel. In such a structure, when forming a transistor included in a sub-pixel, it is possible to simultaneously form a pull-up transistor and a capacitor without additional processing.

As described above, the first and second embodiments of the present invention can maintain a constant capacitance even when the pull-up transistor is deteriorated by changing the structure of the capacitor located at the output terminal of the scan driver of the a-Si-based liquid crystal display.

Accordingly, in the pull-up transistor positioned at the output terminal of the shift register included in the scan driver, charge trapped or defects are formed in the gate insulating layer and the active layer, and the characteristics of the capacitor are deteriorated. It has the effect of solving the problem of dropping and improving the life and reliability of the circuit.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a schematic plan view of a liquid crystal display according to the present invention;

2 is a schematic plan view of a subpixel;

3 is a cross-sectional view of region A1-A2 of FIG. 2;

4 is an exemplary schematic configuration of a scan driver;

5 is an exemplary circuit configuration of an output terminal of the shift register shown in FIG. 4;

6 is a cross-sectional structural view of the pull-up transistor and capacitor shown in FIG.

7 is a schematic structural diagram of the capacitor of FIG.

8 is another cross-sectional structural view of a pull-up transistor and a capacitor.

9 is a schematic structural diagram of the capacitor of FIG. 8;

<Explanation of symbols on main parts of the drawings>

110: substrate 106,108: gate

115: first insulating film 121: drain

122: source 130: second insulating film

140: planarization layer 160: upper electrode

170: scan wiring 180: data wiring

190: common voltage wiring

Claims (9)

A subpixel located on the substrate; A data driver supplying a data signal to the data line of the subpixel; And Including a scan driver for supplying a scan signal to the scan line of the sub-pixel, The output terminal of the scan driver, A gate on the substrate, a first insulating layer on the gate, an active layer on the first insulating layer, a drain and a source on the active layer, and a drain and a source on the A pull-up transistor comprising a second insulating film positioned thereon; And a capacitor including the gate, the first insulating layer, and an upper electrode on the second insulating layer and connected to the drain or the source. The method of claim 1, And the capacitor is spaced apart from the pull-up transistor. The method of claim 1, The capacitor, And a second insulating layer disposed between the first insulating layer and the upper electrode. The method of claim 1, The upper electrode, And a pixel electrode included in the sub-pixel. The method of claim 1, The second insulating film, A first contact hole exposing the drain or the source included in the pull-up transistor and a second contact hole exposing the first insulating layer; The upper electrode, And contacting the drain or the source through the first contact hole and contacting the first insulating layer corresponding to the gate through the second contact hole. The method of claim 3, The second insulating film, A first contact hole exposing the drain or the source included in the pull-up transistor; The upper electrode, And contacting the drain or the source through the first contact hole and on the second insulating layer corresponding to the gate. The method of claim 1, The pull-up transistor, And a shift register of the scan driver. The method of claim 1, The pull-up transistor, And an ohmic contact layer disposed between the active layer, the drain, and the source. The method of claim 1, The active layer, A liquid crystal display, characterized in that a-Si.

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