KR20090108468A - Memory apparatus and the driving method of the same - Google Patents

Abstract

PURPOSE: A memory apparatus and the driving method of the same are provided to minimize the area of the memory device by sharing a plurality of memory cell. CONSTITUTION: The memory device and driving method includes the memory device, the first transistor, and the first switching transistor and the first coupling capacitors. The memory device includes a substrate and a floating gate. The first transistor reads out data. The first switching transistor is connected to a dataline. The coupling capacitor is serially connected with the memory device. The first coupling capacitors include the second electrode electrically connected to the first electrode, and the word line.

Description

Memory apparatus and its driving method {Memory apparatus and the driving method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a method of driving the same, and more particularly, to a memory device and a method of driving the same, which prevents deterioration of internal elements of a memory and lowers a voltage required for writing and erasing operations.

The semiconductor memory device may be divided into a volatile memory which loses its recorded contents when the power supply is interrupted and a nonvolatile memory which does not lose its recorded contents even when the power supply is interrupted. The dual nonvolatile memory has been developed from Mask Read Only Memory (PROM) to Programmable ROM (PROM), EPROM, and EEPROM. In particular, unlike the semiconductor memory device developed in the early days, the number of times that can be written, modified or deleted has increased. Accordingly, reduction of power consumed to perform functions such as data writing, modification, or deletion in the semiconductor memory device, and reduction of time required to perform the above functions are increasingly considered as important factors.

Meanwhile, in the case of flash memory, which has recently developed into the largest market, both NAND and NOR types still have high voltages of about 20V despite the development of technology and a decrease in external power supply voltage and miniaturization of minimum line width. The internal voltage is used for writing and erasing data. It is known that a voltage of about 10 V must be applied across the insulating film to cause a tunneling effect on the insulating film and to maintain the tunneled charge for more than 10 years. However, as mentioned above, in the case of a flash memory, a high voltage of about 20 V, which is twice that, is required. This is a problem originating from the structure of the flash memory. Unlike conventional MOS capacitors or MOS transistors that have a vertical structure such as a 'gate-insulation-substrate', a flash memory has a 'control gate-coupling oxide-floating gate-tunneling oxide ( tunneling oxide)-consists of a substrate 'structure. In order to generate a current due to the tunneling effect from the substrate to the floating gate or vice versa, a voltage of about 10 V must be applied to both ends of the tunneling oxide film formed between the two layers. However, the voltage applied to the substrate and the control gate is distributed by the capacitance of the coupling capacitor formed by the control gate and the floating gate, and the tunneling capacitor formed by the floating gate and the substrate, and the capacitances of the two types of capacitors are almost similar. Has a value. Thus, for example, when the substrate is grounded, a voltage of about 20V, which is twice the voltage required for the tunneling effect, should be applied to the control gate.

This excessive operating voltage is generated by boosting an externally supplied voltage in a circuit called a charge pump provided inside the chip. However, the greater the ratio between the externally supplied voltage and the boosted internal voltage, the lower the energy efficiency of the charge pump. In addition, as the size of the transistor decreases with the development of technology, the maximum withstand voltage of the transistor decreases, so a transistor having a large channel length and channel width must be used to withstand a large internal voltage. In addition, transistors with large channel lengths and channel widths not only increase chip area, but also increase power consumption proportionally as devices increase.

As mentioned above, much research has been made to reduce excessive operating voltage. 1 shows a circuit of a cell of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a cell C100 of a memory device includes first and second programming transistors M106 and M104 and a storage transistor M102. The first programming transistor M106 and the second programming transistor M104 share a floating gate as a gate electrode. In addition, an area of the first programming transistor M106 is larger than that of the second programming transistor M104.

Referring to the operation of the memory cell according to the related art, a low level voltage (about 0V) is applied to the source, drain, and n-well terminals of the first programming transistor M106 during an erase operation. A high level voltage (about 10V) is applied to the source, drain and n-well terminals of the second programming transistor M104. Due to the area difference between the two programming transistors, a voltage of about 9 V is formed in the second programming transistor M104, and electrons are removed from the shared floating gate.

On the other hand, during a program operation, a voltage between a high level and a low level is applied to the first programming transistor M106 and a current flows through the storage transistor M102 to a floating gate where hot carriers generated at this time are shared. Is injected.

In this manner, the operating voltage required for the data write or erase operation was reduced to about 10V. However, the 10V operating voltage is high enough to cause the tunneling effect. Therefore, even in a general transistor that is not the target of tunneling, tunneling occurs due to the high voltage, and as a result, the transistor deteriorates. That is, in the case of FIG. 1, transistors included in circuits for supplying a high voltage to the first programming transistor M106 and the second programming transistor M104 may be deteriorated by a voltage of 10V.

Therefore, there is a need to develop a cell structure capable of minimizing deterioration of many elements included in an internal cell of a semiconductor memory device and reducing an operating voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a memory device which prevents deterioration of elements other than those in which tunneling occurs and lowers operating voltages required for write and erase operations.

In order to solve the above technical problem, a first aspect of the present invention provides a memory device including at least one memory cell, wherein the memory cell includes a substrate and a floating gate, and a memory device to which data is written, and reads the data. The shipping device includes a first transistor and a first boosting circuit, and the first boosting circuit includes a coupling capacitor and a first switching transistor connected in series with the memory device.

The first transistor may include a gate electrode connected to a floating gate of a memory device, a first electrode connected to a bit line, and a second electrode to which a first voltage is applied. A first electrode connected to the data line, a second electrode connected to the substrate of the memory device, and a gate electrode to which the second voltage is applied, wherein the coupling capacitor comprises: a first electrode connected to the floating gate of the memory device; A first coupling capacitor including a second electrode electrically connected to a word line, and a second coupling capacitor including a first electrode connected to a substrate of the memory device and a second electrode connected to a program line. Can be.

In the present invention, a second switching transistor includes a first electrode connected to the word line, a second electrode connected to a second electrode of the first coupling capacitor, and a gate electrode to which the second voltage is applied. And a second boosting circuit including a first electrode connected to the second electrode of the first coupling capacitor and a third coupling capacitor including a second electrode connected to the erase line.

The present invention may further include a decoder provided outside the memory cell, and the second boosting circuit may be provided in the decoder.

In the present invention, the third coupling capacitor can be shared by a plurality of memory cells.

The present invention may further include a third switching transistor including a first electrode connected to the second electrode of the first transistor, a second electrode to which the first voltage is applied, and a gate electrode.

In the present invention, the memory device may be a nonvolatile memory device.

In order to solve the above technical problem, a second aspect of the present invention is a memory device including a substrate and a floating gate, a first electrode connected to the floating gate of the memory device, a first coupling capacitor comprising a second electrode, And at least one memory cell including a first electrode connected to a substrate of the memory device and a second coupling capacitor including a second electrode, the method comprising: a) the first coupling Applying a first voltage to a second electrode of the capacitor; b) applying a second voltage to the second electrode of the memory element; and c) generating a tunneling current to a voltage applied to the second electrode of the memory element. It provides a method of driving a memory device comprising the step of boosting to a third voltage.

In the present invention, step c) may be a step of changing the voltage applied to the second electrode of the second coupling capacitor from the first voltage to the second voltage.

In an embodiment of the present invention, the method may further include d) repeating the boost and the depressurization so that the third voltage and the second voltage are alternately applied to the second electrode of the memory device.

As such, the memory device includes a boosting circuit including a coupling capacitor and a switching transistor, thereby reducing the possibility of deterioration due to the application of high voltage to all devices except the memory device, and also improving the energy efficiency of the charge pump. Will be.

In addition, the additional switching transistor prevents deterioration of the transistor connected to the floating gate.

In addition, after the third coupling capacitor having a large area is installed in the decoder region, the plurality of memory cells are shared so that the area of the memory device can be minimized.

In addition, the first and second voltages are alternately applied to the signals applied to the program line and the erase line, thereby reducing the tunneling efficiency.

Hereinafter, a preferred embodiment of the present invention will be described in more detail with reference to FIGS. 2 to 6.

2 is a diagram illustrating a cell circuit of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a cell 200a of a memory device includes a memory device Cst, a first transistor M1, and a first boosting circuit.

The memory device Cst includes a substrate and a floating gate FG, and writes data by using tunneling generated due to a voltage difference applied across the substrate and the floating gate FG. It is also possible to delete data using the tunneling. The memory device Cst may be a MOS capacitor or a MOSFET.

The first transistor M1 reads data written to the floating gate FG by the tunneling. The reading of data may be, for example, "1" for a state in which charge is applied (electron removed) from floating gate FG by the tunneling, and "0" for a state in which charge is removed (electron applied). You will be able to

The first transistor M1 is connected to the floating gate FG of the memory device Cst and the gate electrode, and the first electrode is connected to the bit line BL. The first voltage is applied to the second electrode. The bit line signal is applied to the bit line BL from the outside of the cell 200a. The first electrode and the second electrode may be a source electrode and a drain electrode, respectively. In addition, the ground voltage may be used as the first voltage.

The first boosting circuit includes a coupling capacitor and a first switching transistor M2 connected in series with the memory device. In addition, the coupling capacitor may include a first coupling capacitor C1 and a second coupling capacitor C2.

In the first switching transistor M2, a first electrode is connected to the data line DL, and a second electrode is connected to the substrate of the memory device Cst. In addition, a second voltage is applied to the gate electrode. The first electrode and the second electrode may be a source electrode and a drain electrode, respectively. A data line signal may be applied to the data line DL. On the other hand, when a voltage sufficient to generate the tunneling effect is called Vtn, the second voltage may be a value slightly smaller than half or half of the Vtn value. For convenience of description, the second voltage is referred to as 'VPP'. When the VPP value is applied to the data line DL, the first switching transistor M2 is turned off, and the second electrode receives VPP-Vth (Vth: threshold voltage). On the other hand, when a ground voltage, which is a first voltage, is applied to the data line DL, the first switching transistor is turned on so that a ground voltage is also applied to the second electrode. In this case, the first switching transistor M2 may be an NMOS transistor. However, the present invention is not limited thereto, and a PMOS transistor may be used. In this case, it will be apparent to those skilled in the art that the above operation may be performed by changing a combination of applied voltages.

In the first coupling capacitor C1, a first electrode is connected to the floating gate FG of the memory device Cst, and a second electrode is electrically connected to the word line WL. A word line signal may be applied to the word line WL.

In the second coupling capacitor C2, a first electrode is connected to the substrate of the memory device Cst, and a second electrode is connected to the program line PGM. A program line signal may be applied to the program line PGM.

The first and second coupling capacitors C1 and C2 may perform a function of distributing a voltage applied to both ends of the memory device Cst. In this case, the first and second coupling capacitors C1 and C2 may be formed to have an electric capacity about 10 times larger than the electric capacity of the memory element Cst.

Meanwhile, the memory cell 200a according to the present invention may further include a second boosting circuit 200b. The second boosting circuit 200b includes a second switching transistor M3 and a third coupling transistor C3.

In the second switching transistor M3, a first electrode is connected to the word line WL, and a second electrode is connected to the second electrode of the first coupling capacitor C1. On the other hand, the second voltage VPP is applied to the gate electrode.

In the third coupling capacitor C3, a first electrode is connected to the second electrode of the first coupling capacitor C1, and the second electrode is connected to the erase line ERS. An erase line signal may be applied to the erase line ERS. It may be possible to form a switch (not shown) between the erase line ERS and the second electrode of the third coupling capacitor C3 so as to connect both devices by turning the switch ON only when necessary. This will be described again with reference to FIG. 5. In addition, the capacitance of the third coupling capacitor (C3) is preferably at least 10 times larger than the capacitance of the first, second coupling capacitor (C1, C2).

The write and erase operations of data in the memory cells of the memory device as described above are as follows.

First, the operation of storing charge, ie, removing electrons, in a floating gate path is described. In order to store electric charges, a ground voltage, which is a first voltage, is applied to the second electrode of the first coupling capacitor C1. When the ground voltage is applied as the word line signal, the second switching transistor M3 may be turned on to apply the ground voltage to the second electrode of the first coupling capacitor C1. In addition, a ground voltage is applied as a program signal to the program line PGM as a preliminary step of voltage boosting. The VPP value is applied to the data line DL as a data line signal. Under the above conditions, since the first switching transistor M2 is in an OFF state, the potential of the second electrode of the first switching transistor M2 becomes VPP-Vth. At this time, if the signal of the program line PGM to which the ground voltage is applied is increased to VPP, the voltage of the node B is increased to 2VPP-Vth. Then, the potential difference between node B and node A is 2VPP-Vth, and as mentioned above, since the capacitance of the first coupling capacitor C1 is much larger than that of the memory element Cst, the voltage 2VPP-Vth Most of the time is caught in the memory element Cst. The value of 2VPP-Vth is a voltage such that tunneling can occur, and a tunneling current is generated in the memory device Cst to store charge (remove electrons) in the floating gate FG. In this case, no voltage other than the second voltage VPP is applied to any device except the memory device Cst. Therefore, all devices except the memory device Cst are less likely to deteriorate due to high voltage application, and tunneling occurs only in devices requiring write and erase operations. In addition, the voltage of about 10V required for cell tunneling and the conventional technology is not directly applied from the outside, but a much smaller voltage of about 5V can be applied as an operating voltage to boost the tunneling to generate a tunneling energy efficiency. Can be improved.

Next, the data erasing operation will be described. The erasing of data can be accomplished by removing the charge (injecting electrons) stored in the floating gate FG, which is the reverse operation of writing the data.

First, a ground voltage, which is a first voltage, is applied to the data line DL, thereby applying a ground voltage to the substrate of the node B, that is, the memory device Cst. The VPP value is applied to the word line WL so that the potential of the second electrode of the node A, that is, the first coupling capacitor C1, is set to VPP-Vth. Then, when VPP is applied to the erase line ERS, the potential of the node A is boosted to 2VPP-Vth. The potential difference between node A and node B is then 2VPP-Vth, and as mentioned above, the capacitance of the second coupling capacitor C2 is much larger than that of the memory element Cst, so the voltage 2VPP-Vth Most of the time is caught in the memory element Cst. The value of 2VPP-Vth is a voltage such that tunneling can occur, and a tunneling current is generated in the memory device Cst to remove charges (inject electrons) from the floating gate FG. In this case, as in the data writing operation, no voltage other than the second voltage VPP is applied to any element except the memory element Cst. Therefore, all devices except the memory device Cst are less likely to deteriorate due to high voltage application, and the energy efficiency of the charge pump may be improved.

Meanwhile, the second boosting circuit 200b including the second switching transistor M3 and the third coupling capacitor C3 may be formed to be included in a cell of the memory device. Alternatively, the second boosting circuit 200b may be formed outside the plurality of cell arrays. It is also possible to form the provided decoder. In addition, it may be possible to form only one third coupling capacitor C3 for the entire region without having to provide as many cells as the memory device. In this case, the third coupling capacitor C3 may be formed to have a large capacitance of several tens to hundreds of times larger than the capacitance of the memory element Cst, and erase the data in each selected cell. A switch can be formed to perform.

Since the third coupling capacitor C3 should be 10 times or more than the first and second coupling capacitors C1 and C2, the second coupling circuit may be made too large when formed inside the cell. By forming 200b in the decoder part, the size of the entire memory device can be reduced.

FIG. 3 is a diagram illustrating a cell circuit of a nonvolatile memory device according to another exemplary embodiment of the present invention. Referring to FIG. 3, a third switching transistor M11 is further included as compared with the cell circuit of FIG. 2.

In the third switching transistor M11, a first electrode is connected to the second electrode of the first transistor M1. In addition, a first voltage is applied to the second electrode, and a redundant line (RWL) signal is applied to the gate electrode.

In the data erasing operation of FIG. 2, when the high voltage is applied to the floating gate FG, degradation may occur in the first transistor M1. Therefore, the third switching transistor M11 may be further included to prevent the first transistor M1 from being deteriorated by floating the first electrode and the second electrode of the first transistor M1.

In addition, since the area of the cell is determined by the sizes of the first and second capacitors C1 and C2, further inclusion of the third switching transistor M11 as shown in FIG. 3 has little effect on the area of the cell. .

4 is a waveform diagram illustrating a driving signal of a cell circuit of the nonvolatile memory device of FIG. 2. 2 and 4, the write and erase operations of data will be described. Data is written at T1 to T4, and data is erased at T5 to T8.

First, the operation in T1 to T4 will be described. Since the ground voltage is applied to the word line WL from before T1, the node A also takes the ground voltage. The signal applied to the data line DL at T1 is changed from the ground voltage to the second voltage VPP. As a result, the node B receives the voltage of VPP-Vth. In addition, after the signal applied to the data line DL is changed, the signal applied to the program line PGM at T2 is changed from the ground voltage to VPP. The node B is stepped up to 2VPP-Vth to maintain a constant voltage across the second coupling capacitor C2. Due to the capacitance of each capacitor, the voltage of 2VPP-Vth is mostly applied to the memory device Cst. Since the voltage 2VPP-Vth is a voltage at which a tunneling current can occur, the tunneling current is generated to the floating gate FG to record data. It can be confirmed that data has been written in that the potential of the floating gate FG is maintained at T4 to T5.

Next, the operation of T5 to T8 will be described. The ground voltage is applied to the data line DL before T5, and the ground voltage is also applied to the node B because the first switching transistor M2 is turned on. On the other hand, when the second voltage VPP is applied to the word line WL at T5, the second switching transistor M3 is turned off and the voltage of the node A becomes VPP-Vth. When the voltage of the node A becomes the VPP-Vth, the voltage of the erase line ERS is changed from the ground voltage to VPP at T6. In order to maintain a constant voltage across the first coupling capacitor C1, the voltage of the node A is stepped up to 2VPP-Vth. Most of the voltage of 2VPP-Vth is applied to the memory device Cst by the ratio of the capacitance between the capacitors. As a result, a tunneling current is generated and data is erased.

On the other hand, looking at the node B in T2 to T3 it can be seen that the voltage gradually decreases. This causes the generation of leakage currents from junctions connected to Node B. As a result, if a large amount of time passes after the voltage of the node B is boosted to 2VPP-Vth, the voltage of the node B gradually decreases and the tunneling effect decreases drastically.

Therefore, instead of maintaining the voltage of the program line PGM at VPP for a long time, VPP and the ground voltage are alternately applied at regular time intervals, thereby replenishing the lost charge due to leakage current through the first switching transistor M2. As shown in Fig. 4, the voltage of the node B can be maintained above a certain voltage to allow sufficient tunneling to occur.

Likewise, in T6 to T7, instead of maintaining the voltage applied to the erase line ERS at VPP to prevent the tunneling efficiency from being lowered due to leakage current, the VPP and the ground voltage are alternately applied at regular time intervals. Can be.

5 is a diagram illustrating a cell circuit array according to the embodiment of FIG. 2.

Referring to FIG. 5, the memory device includes a plurality of data lines DL, a plurality of bit lines BL, a plurality of program lines PGM, and a plurality of word lines WL. The memory cell may be formed in an area surrounded by the data line DL, the bit line BL, the program line PGM, and the word line WL. The cell may include a memory device Cst, a first transistor M1, first and second coupling capacitors C1 and C2, and a first switching transistor M2. The connection relationship of each device is described in Figure 2 will be omitted.

In addition, a decoder may be formed outside the cell array, and the decoder region may include a third coupling capacitor C3 and a second switching transistor M3 as a second boosting circuit. As mentioned in the description of FIG. 2, the third coupling capacitor C3 may be formed to share a plurality of cells, and switches may be used to perform an erase operation with the memory device Cst of a cell selected from the plurality of cells. Can be formed. The switches may be turned on by a word line signal connected to the selected cell.

As described above, all cells share the third coupling capacitor C3, which occupies a larger area than other devices, thereby minimizing an area required for manufacturing a memory device.

6 is a top view of a cell structure of the nonvolatile memory device of FIG. 3.

It can be seen that the areas of the first and second coupling capacitors C1 and C2 are formed to be several times the area of the memory element Cst. In addition, as mentioned in the description of FIG. 3, it can be seen that the addition of the third switching transistor M11 does not significantly affect the total area. The top view of FIG. 6 is merely an embodiment for implementing a circuit of a cell according to the present invention, and is not limited to the structure as shown in FIG. 6, and may be formed in another structure.

Although the nonvolatile memory device has been described with reference to FIGS. 2 to 6, the present invention is not limited thereto, and a person skilled in the art will be able to apply it to other semiconductor memory devices without departing from the spirit of the present invention. The first to third coupling capacitors C1, C2, and C3 may be NMOS capacitors or PMOS transistors. However, the present invention is not limited thereto, and a general capacitor may be used. In addition, the ratio of the capacitance between the first to third coupling capacitors C1, C2, and C3 is not limited to the numerical values mentioned in the above description and may be variously changed. In addition, although the transistors used in the present invention may use an NMOS transistor, it will be possible to use a PMOS transistor.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a diagram illustrating a cell circuit of a memory device according to the prior art.

2 is a diagram illustrating a cell circuit of a nonvolatile memory device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a cell circuit of a nonvolatile memory device according to another exemplary embodiment of the present invention.

4 is a waveform diagram illustrating a driving signal of a cell circuit of the nonvolatile memory device of FIG. 2.

5 is a diagram illustrating a cell circuit array according to the embodiment of FIG. 2.

FIG. 6 is a top view illustrating an exemplary embodiment of a cell structure of the nonvolatile memory device of FIG. 3.

Claims (10)

A memory device having at least one memory cell, the memory device comprising: The memory cell is A memory device including a substrate and a floating gate, to which data is written; A first transistor reading the data; And A first boosting circuit, The first boosting circuit And a coupling capacitor and a first switching transistor connected in series with the memory device. The method of claim 1, The first transistor includes a gate electrode connected to a floating gate of a memory device, a first electrode connected to a bit line, and a second electrode to which a first voltage is applied. The first switching transistor includes a first electrode connected to the data line, a second electrode connected to a substrate of a memory device, and a gate electrode to which a second voltage is applied. The coupling capacitor A first coupling capacitor including a first electrode electrically connected to the floating gate of the memory device and a second electrode electrically connected to a word line; And And a second coupling capacitor including a first electrode connected to a substrate of the memory device and a second electrode connected to a program line. The method of claim 2, A second switching transistor including a first electrode connected to the word line, a second electrode connected to a second electrode of the first coupling capacitor, and a gate electrode to which the second voltage is applied; And A third coupling capacitor including a first electrode connected to a second electrode of the first coupling capacitor and a second electrode connected to an erase line; The memory device further comprises a second boosting circuit having a. The method of claim 3, Further comprising a decoder provided outside the memory cell, And the second boosting circuit is provided in the decoder. The method of claim 4, wherein And the third coupling capacitor is shared by a plurality of memory cells. The method according to any one of claims 1 to 5, And a third switching transistor including a first electrode connected to the second electrode of the first transistor, a second electrode to which a first voltage is applied, and a gate electrode. The method of claim 1, And the memory device is a nonvolatile memory device. A memory device including a substrate and a floating gate, a first electrode connected to the floating gate of the memory device, a first coupling capacitor including a second electrode, a first electrode connected to a substrate of the memory device, and a second A method of driving a memory device including at least one memory cell having a second coupling capacitor including an electrode, the method comprising: a) applying a first voltage to a second electrode of said first coupling capacitor; b) applying a second voltage to a second electrode of said memory element; And c) boosting the voltage applied to the second electrode of the memory device to a third voltage at which a tunneling current is generated. The method of claim 8, wherein step c) And changing the voltage applied to the second electrode of the second coupling capacitor from the first voltage to the second voltage. The method of claim 8, and d) repeating the boosting and the depressurizing such that the third voltage and the second voltage are alternately applied to the second electrode of the memory device.

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