KR20090107963A - Circuit arrangement for operating a capacitive load and usage of such a circuit arrangement - Google Patents

Abstract

PURPOSE: A circuit device for operating a capacitive load is provided to prevent generation of a high current or a high voltage in an output part in case an error is generated. CONSTITUTION: A circuit device(10) for operating a capacitive load(P) includes a first power supply terminal(E1), a second power supply terminal(E2), a first output terminal(A1), a second output terminal(A2), a capacitor(C), a first inductor(L1), a first switch(Q1), a second inductor(L2), a diode(D1), a second switch(Q3), and a control device(ST). The first output terminal for connecting the load is connected to the first power supply terminal. The capacitor is arranged between a first circuit node and a second circuit node. The first inductor is arranged between the second power supply terminal and the first circuit node. The first switch is arranged between the first circuit node and the firs power supply terminal. The second inductor is arranged between the second circuit node and the first power supply terminal. The diode is arranged between the second circuit node and the second output terminal. The second switch is arranged between the second output terminal and the first output terminal.

Description

CIRCUIT ARRANGEMENT FOR OPERATING A CAPACITIVE LOAD AND USAGE OF SUCH A CIRCUIT ARRANGEMENT}

The present invention relates to circuit arrangements for operating capacitive loads, for example piezoelectric actuators.

Such circuit arrangements are known in various embodiments, especially in the field of automotive electronics, and are especially used for operating piezoelectric actuators in fuel injectors. However, the known circuit arrangements are quite complex due to the high requirements posed by such applications in connection with the fast, accurate and renewable opening and closing of fuel injection valves.

As such, less complex and less economical circuit devices would be desirable for applications where the requirements for power characteristics of the circuit device are low.

An object of the present invention is to provide a simply configured circuit arrangement for operating a capacitive load.

The problem is solved by the circuit arrangement according to claim 1 or 2 of the present invention. The dependent claims relate to preferred refinements of the invention.

The circuit arrangements 10 and 10a according to the present invention, because they are simply configured respectively, produce an output stage which is advantageously advantageous for triggering a piezoelectric actuator. The circuit arrangement consists of only one stage and does not require a linear regulator connected later. Basically any output voltage and input voltage can be set. Capacitive or inductive decoupling between the power supply side and the output side may not generate high current or high voltage at the output even in the event of an error. In addition, energy stored in the load may be recovered at least partially again at the time of load discharge.

The circuit arrangement according to the first aspect of the present invention is

A first power supply terminal and a second power supply terminal for applying a first supply potential or a second supply potential,

A first output terminal and a second output terminal for connecting the load, in which case the first output terminal is connected to the first power supply terminal,

A capacitor disposed between the first circuit node and the second circuit node,

A first inductor disposed between the second power supply terminal and the first circuit node,

A first triggerable switch disposed between the first circuit node and the first power supply terminal,

A second inductor disposed between the second circuit node and the first power supply terminal,

A diode disposed between the second circuit node and the second output terminal,

A triggerable second switch disposed between the second output terminal and the first output terminal,

A control device for providing a control signal for triggering two switches.

In one refinement of the first aspect of the invention, two inductors are inductively coupled, that is to say formed as coils wound on one common core, for example.

The circuit arrangement according to the second aspect of the present invention

A first power supply terminal and a second power supply terminal for applying a first supply potential or a second supply potential,

A first output terminal and a second output terminal for connecting the load, in which case the first output terminal is connected to the first power supply terminal,

A series circuit disposed between the first power supply terminal and the second power supply terminal and comprising a first inductor and a triggerable first switch,

A second inductor coupled inductively to the first inductor, the second inductor being connected to the first power supply terminal on the one hand and to the second output terminal via the diode on the other hand,

A triggerable second switch disposed between the second output terminal and the first output terminal,

A control device for providing a control signal for triggering two switches.

In one refinement the circuit arrangement according to the second aspect of the invention also comprises a capacitor arranged between the first power supply terminal and the second power supply terminal.

The circuit arrangement according to the invention can be implemented very simply with a relatively small number of components and charges the capacitive load with a corresponding load current which basically has an arbitrary time waveform by correspondingly triggering two switches. And discharge.

Furthermore, the circuit design has a series of additional advantages, particularly when used for the purpose of triggering a piezoelectric actuator (eg in a proportional valve).

The present invention is well suited for triggering "relatively slow" (as compared to fuel injectors), for example, actuators in adjustable fluid valves (such as proportional valves), for example in gas valves provided with pressure reducers. The piezoelectrically actuated and adjustable gas valve can be inserted, for example, as a pressure reducer between the combustion gas storage region and the combustion gas inlet region of an internal combustion engine (gas motor) operated by gas. With the circuit arrangement according to the invention, the rate of change over time of the output voltage (load voltage) which is fully sufficient to trigger such a pressure reducing valve can be achieved (typically within the ms-range).

In addition, the circuit arrangement according to the invention can generate the higher voltages necessary to deflect the piezoelectric actuator from a relatively low supply voltage (= difference between two supply potentials). Correspondingly, the output side voltage is also very large (because the output voltage can also be reduced to 0 V).

In addition, the circuit arrangement allows a constant output voltage to be maintained over a longer time in a simple manner (e.g., adjusted to a set point), and this situation is practical in the application of the above-described pressure reducer operated in a piezoelectric manner. Occurs frequently.

Although the structure of the circuit arrangement is extremely simple, the power loss during operation can be kept relatively low. In addition, recovery of electrical energy stored in the capacitive load is possible at the time of load discharge, thereby enabling operation with low loss even in the dynamic stop-start-operation state.

In one embodiment two supply potentials are provided by one battery, for example by a battery provided for powering an automotive electrical system. The circuit arrangement can in this case be provided in the area of the motor vehicle drive device (for example for operating the proportional valve) for operating the piezo actuator.

In one embodiment, the circuit components are designed to reach an output voltage that exceeds the supply voltage. This upward movement from the supply voltage to the output voltage is typically relatively high (eg 50 V) for complete deflection from an electrical system having a relatively low voltage (in the range of 12 V to 16 V), for example in automotive applications. This is particularly important when triggering piezoelectric actuators requiring voltages (especially above 100 V) are problematic.

The first triggerable switch and / or the second triggerable switch can be formed in a simple manner as a transistor, in particular as a field effect transistor (FET). If bipolar transistors are used, bipolar transistors with insulated gate-electrodes (“IGBTs”) are preferred in connection with low electrical losses.

With regard to adjusting the output voltage as accurately as possible, it is advantageous if means are provided for measuring the current flowing through the first switch and / or for measuring the current flowing through the load. Such current measuring means may comprise, for example, a shunt resistor, the shunt resistor being arranged in a corresponding current path, the voltage drop of the shunt resistance being recorded as a measurement value representing the flow current by the evaluation unit. do. The evaluation unit may in particular be part of a control device provided in any case for providing control signals for two switches.

The invention is described in detail below with reference to embodiments associated with the accompanying drawings.

FIG. 1 shows a circuit arrangement 10 (output stage) for operating a capacitive load in the form of a piezoelectric actuator P. FIG. The circuit arrangement 10 comprises in this case, for example, power supply terminals E1 and E2 for applying supply potentials GND and VBAT provided from an automobile battery.

The supply voltage (difference between VBAT and GND) is eg 12V. On the output side, between the output terminals A1 and A2, an output voltage (load voltage) for the piezoelectric actuator P can be set during operation, which output voltage can be changed in the range of 0 V to 200 V, for example. have.

Piezoelectric actuators P are used to operate pressure reducers, for example, in the inlet region of an automobile gas motor.

Circuit device 10 also

A capacitor C disposed between the first circuit node K1 and the second circuit node K2,

A first inductor L1 disposed between the second power supply terminal E2 and the first circuit node K1,

A first switching transistor Q1 disposed between the first circuit node K1 and the first power supply terminal E1,

A second inductor L2 disposed between the second circuit node K2 and the first power supply terminal E1,

A diode D1 disposed between the second circuit node K2 and the second output terminal A2,

A second switching transistor Q3 disposed between the second output terminal A2 and the first output terminal A1,

A control device ST for providing control signals q1 and q3 for triggering two transistors Q1 and Q3. The control device ST causes such a triggering operation on the basis of the preset signal S provided (the preset signal is generated by, for example, a program controlled computer device (eg a microcontroller)).

In the illustrated embodiment, the current measuring resistor Rs1 is connected in series to the first transistor Q1, and the voltage drop Us1 of the current measuring resistor represents a current flowing through the first transistor Q1. The measured value Us1 is provided to improve the control accuracy of the control device ST.

In another exemplary embodiment, the voltage drop Us2 falling from the second current measuring resistor Rs2 is considered in the control, and the second current measuring resistor includes the first power supply terminal E1 and the first output terminal. It is arranged in the connection path between A1). Therefore, the voltage drop Us2 represents the current flowing through the piezoelectric actuator P. FIG.

According to one simple functional scheme of the circuit arrangement 10, the charging of the piezoelectric actuator P is made by the clocked operation of the first transistor Q1, whereas the discharge of the load P is Made by the second transistor Q3, the second transistor can be operated, for example clock-controlled or permanently, in particular in a linearly set state.

It should be noted that with respect to the charging process, the circuit arrangement 10 actually works the same as the so-called "Single Ended Primary Inductance Converter" (SEPIC) -converter. Charging in a clock-controlled manner can be described as follows:

At the beginning of the circuit operation, transistors Q1 and Q3 are cut off, and a charging voltage corresponding to the supply voltage is set in capacitor C. The potential VBAT prevails at the first circuit node K1, and the potential GND prevails at the second circuit node K2.

When the first transistor Q1 is switched on, the potential at the first circuit node K1 suddenly decreases to GND. As a result of this phenomenon, the gradually increasing current of the second power supply terminal E2 is passed through the first inductor L1 (first choking coil) and further through the first transistor Q1. Flowing to one power supply terminal E1, the potential at the second circuit node K2 suddenly drops to the value of VBAT, that is to say below the potential GND. As a result of this phenomenon, a gradually increasing current also flows from the first power supply terminal E1 to the second circuit node K2 through the second inductor L2 (second choking coil). In the illustrated embodiment, the inductors L1 and L2 are designed to be the same size.

After a predetermined time, the potential at the second circuit node K2 will again rise to a value of approximately GND, at which moment a relatively large current will flow through the two inductors L1 and L2.

If the first transistor Q1 is switched off again at about the moment, then the current flowing through the first inductor L1 increases the prevailing potential at the first circuit node K1. In addition, the predominant potential at the second circuit node K2 (up to a degree far exceeding the value of VBAT) also increases, so that the load current of the second circuit node K2 eventually leads to the diode D1 and the second output terminal A2. Flows through the piezoelectric actuator (P). In this state, the piezoelectric actuator P is charged by increasing the output voltage.

By repeating the switch-on operation and the switch-off operation of the first transistor Q1, the piezoelectric actuator P can be charged by a desired amount or a desired output voltage (load voltage) can be set.

In order to keep the output voltage between the output terminals A1 and A2 constant and thereby keep the charge stored in the piezoelectric actuator P constant, the two switches Q1 and Q3 are simply switched off (open). do). For example, the output voltage can be monitored to compensate for the undesirable gradual discharge caused by the leakage current, and the output voltage can be reset based on the monitoring result.

In order to reduce the output voltage again and thereby discharge the piezoelectric actuator P, the second transistor Q3 is switched on permanently or in a clock controlled state. In this way a desired temporal discharge waveform can be achieved.

One feature of the illustrated embodiment is that the triggering of the second transistor Q3 is not performed by directly applying the control signal q3 to the control input (in this case the gate) of the second transistor Q3 but rather arithmetic. The adjustment of the discharge current is performed by the amplifier OPAMP. In such a discharge current adjustment, the voltage value of the control signal q3 becomes the setting contents for the discharge current to be set. For this purpose, the signal q3 is applied to the non-inverting input of the operational amplifier OPAMP, by which the inverting input is connected to the source terminal of the second transistor Q3 and outputs. The terminal is connected to the gate terminal of the second transistor Q3. In addition, the source-terminal of the second transistor Q3 is connected directly to the connection path from the first power supply terminal E1 to the first output terminal A1 through the additional shunt resistor Rs3. By this measure, the discharge current flowing through the second transistor Q3 and the additional shunt resistor Rs3 is set in accordance with the control signal q3.

With regard to the triggering of the two switches Q1 and Q3 as precisely as possible for the purpose of setting the output voltage as precisely as possible, in the case of determining the switching point using the control device ST, the above-mentioned current measurement signal Us1 And Us2) can be used.

To monitor the temporal discharge current waveform, monitor the voltage dropping in the shunt resistor Rs3 as an alternative or as an additional measure (redundant measure) as an alternative to evaluating the voltage dropping in the shunt resistor Rs2. The way of doing this is considered.

Alternatively or additionally, a way of detecting other measurement signals in the area of the circuit shown in the figure to determine the optimized switching timing is contemplated. In this approach, for example, detecting the output voltage is desirable in many cases to implement a servo loop that adjusts the output voltage to a set value.

In the following description of the additional embodiment, the same reference numerals are used for the circuit components having the same function. In the present description, only the differences from the above-described embodiment are actually described, with the rest of which may be referred to the description of the above-described embodiment.

FIG. 2 shows a circuit arrangement 10a (output stage) for operating the piezoelectric actuator P. FIG.

The circuit device 10a

A first power supply terminal E1 and a second power supply terminal E2 for applying a first supply potential GND or a second supply potential VBAT,

A first output terminal A1 and a second output terminal A2 for connecting the load P, in which case the first output terminal A1 is connected to the first power supply terminal E1 and ,

A series circuit disposed between the first power supply terminal E1 and the second power supply terminal E2 and consisting of a first inductor L1 and a first switching transistor Q1,

A second inductor L2 inductively coupled to the first inductor L1, said second inductor on one hand to the first power supply terminal E1 and on the other hand to a diode D1; It is connected to the second output terminal (A2) through the two inductors form a transformer,

A second switching transistor Q3 disposed between the second output terminal A2 and the first output terminal A1,

A control device ST for providing control signals q1, q3 for triggering the two switches Q1, Q3. The control device ST causes the triggering operation on the basis of the preset signal S (as already described above for the embodiment according to FIG. 1).

Current measuring resistors Rs1 and Rs2 are provided to measure the current flowing through the first transistor Q1 or piezoelectric actuator P. FIG.

According to one simple functional scheme of the circuit arrangement 10a, the charging of the piezoelectric actuator P is performed by clock controlled operation of the first transistor Q1 while the discharge of the load P is performed by the second transistor Q3. By linear operation (discharge current regulation).

It should be noted that with respect to the charging process, the circuit arrangement 10a actually works the same as the so-called cut-off converter.

In the illustrated embodiment for buffering the supply voltage VBAT-GND, a capacitor C is provided disposed between two power supply terminals E1 and E2.

Charging made in a clock-controlled manner of the piezoelectric actuator P can be described as follows:

When transistor Q1 is shut off at the beginning of circuit operation, a charge voltage corresponding to the supply voltage is set at capacitor C. In this case, the capacitor C is designed such that the charging voltage of the capacitor is kept substantially constant during circuit operation.

When the first transistor Q1 is switched on, the gradually increasing current of the second power supply terminal E2 is increased by the first inductor L1 (primary side of the transformer) and further by the first transistor Q1. To the first power supply terminal E1. The inductively coupled second inductor L2 (secondary side of the transformer) is arranged so that the voltage induced therein does not cause any current flow on the secondary side due to the polarity of the diode D1.

After a predetermined time, a relatively large current flows through the inductor L1.

At that time, when the first transistor Q1 is again switched off and the primary current is cut off, a relatively large voltage is induced in the second inductor L2 so that the load current is transferred from the second inductor L2 to the diode D1 and It flows to the piezoelectric actuator P via the output terminal A2. In this state, the piezoelectric actuator P is charged by increasing the output voltage.

By repeating the switch-on operation and the switch-off operation of the first transistor Q1, the piezoelectric actuator P can be charged by a desired amount or a desired output voltage (load voltage) can be set.

In order to keep the output voltage between the output terminals A1 and A2 constant and thereby keep the charge stored in the piezoelectric actuator P constant, the two switches Q1 and Q3 are simply switched off (open). do). For example, the output voltage can be monitored to compensate for the undesirable gradual discharge caused by the leakage current, and the output voltage can be reset based on the monitoring result.

In order to reduce the output voltage again and thereby discharge the piezoelectric actuator P, the second transistor Q3 is switched on permanently or in a clock controlled state. In this way a desired temporal discharge waveform can be achieved.

In the case of triggering the two switches Q1 and Q3, the above-mentioned current measuring signals Us1 and Us2 are used to determine the switching point advantageous for operation using the control device ST.

In addition, the above-described embodiment described with reference to FIG. 1 contemplates a way to consider other measurement signals such as voltage dropping in the shunt resistor Rs3 or in particular the output voltage when triggering.

1 is a circuit diagram of a circuit arrangement for operating a piezoelectric actuator according to a first embodiment.

2 is a circuit diagram of a circuit arrangement for operating a piezoelectric actuator according to a further embodiment.

Claims (9)

As a circuit arrangement 10 for operating a capacitive load P, The circuit device A first power supply terminal E1 and a second power supply terminal E2 for applying a first supply potential GND or a second supply potential VBAT, A first output terminal A1 and a second output terminal A2 for connecting the load P, in which case the first output terminal A1 is connected to the first power supply terminal E1 and , A capacitor C disposed between the first circuit node K1 and the second circuit node K2, A first inductor L1 disposed between the second power supply terminal E2 and the first circuit node K1, A triggerable first switch Q1 disposed between the first circuit node K1 and the first power supply terminal E1, A second inductor L2 disposed between the second circuit node K2 and the first power supply terminal E1, A diode D1 disposed between the second circuit node K2 and the second output terminal A2, A triggerable second switch Q3 disposed between the second output terminal A2 and the first output terminal A1, A control device ST for providing control signals q1 and q3 for triggering two switches Q1 and Q3, Circuit device. As a circuit device 10a for operating a capacitive load P, The circuit device A first power supply terminal E1 and a second power supply terminal E2 for applying a first supply potential GND or a second supply potential VBAT, A first output terminal A1 and a second output terminal A2 for connecting the load P, in which case the first output terminal A1 is connected to the first power supply terminal E1 and , A series circuit disposed between the first power supply terminal E1 and the second power supply terminal E2 and consisting of a first inductor L1 and a triggerable first switch Q1, A second inductor L2 inductively coupled to the first inductor L1, said second inductor on one hand to the first power supply terminal E1 and on the other hand to a diode D1; Is connected to the second output terminal (A2) through A triggerable second switch Q3 disposed between the second output terminal A2 and the first output terminal A1, A control device ST for providing control signals q1, q3 for triggering two switches Q1, Q3, Circuit device. The method of claim 2, The circuit arrangement also comprises a capacitor C disposed between the first power supply terminal E1 and the second power supply terminal E2, Circuit device. The method according to any one of claims 1 to 3, The two supply potentials GND, VBAT are provided by one battery, Circuit device. The method according to any one of claims 1 to 4, The circuit components are designed to reach an output voltage exceeding the supply voltage (VBAT-GND), Circuit device. The method according to any one of claims 1 to 5, The triggerable first switch Q1 and / or the triggerable second switch Q3 are formed as a transistor, in particular as a field effect transistor FET, Circuit device. The method according to any one of claims 1 to 6, Means Rs1 for measuring the current flowing through the first switch Q1 and / or means Rs2 for measuring the current flowing through the load P are provided, Circuit device. The method according to any one of claims 1 to 7, Means OPAMP, Rs3 are provided for setting the current flowing through the second switch Q3 in a regulated manner in accordance with the associated control signal q3, Circuit device. Use of the circuit arrangement 10, 10a according to any one of claims 1 to 8, Used to trigger piezo actuators, Use of circuit devices.

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