KR20090107630A - Semiconductor Integrated Circuit for Supporting a Test Mode and Control Method Thereof - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit supporting a test mode and a control method thereof are provided to improve efficiency of a layout by decreasing the number of the global line wirings. CONSTITUTION: An address driver(120) outputs an address drive signal by driving the latched input address in a test mode. An address decoder(130) decodes the address drive signal and provides the decoded signal to a target circuit(140). A global line is interposed between the address driver and the address decoder. The address drive signal is transmitted to the same number of the global lines as the number of the latched input addresses. An output signal of the address decoder is transmitted to the local line.

Description

Semiconductor Integrated Circuit for Supporting a Test Mode and Control Method Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a semiconductor integrated circuit supporting a test mode and a control method thereof.

In general, the semiconductor memory device may monitor characteristics and signals of various operation modes through the test mode. Accordingly, in the semiconductor memory device, various test modes may be performed after a signal is applied using an NC connection pin or an address pin.

In order to perform such a test, the semiconductor memory device is set to a test mode instead of a normal operation mode, and a plurality of test mode items are separately set according to the type of test to be performed. By decoding ⁿ input signals (n is a natural number of two or more) to distinguish various test mode items, 2 ⁿ decoded signals may be used as test signals for each test mode. Since a circuit portion for performing the test mode, that is, a target circuit, may exist in each bank, such a decoding signal is once transmitted to a global line. Therefore, as the input signal increases, the number of decoded signals increases accordingly, so that the number of global lines increases, and the wiring thereof is complicated and the area of the wiring layout also increases. Thus, if one wants to reduce the line width, the resistance of the global line may increase. In addition, when the spacing between the lines becomes smaller, coupling noise between the lines may occur.

An object of the present invention is to provide a semiconductor integrated circuit that supports a test mode that reduces the number of global line wirings by wiring the decoded signals to local lines.

An object of the present invention is to provide a control method of a semiconductor integrated circuit which supports a test mode which reduces the number of global line wirings by wiring the decoded signals to local lines.

In order to achieve the technical object of the present invention, the semiconductor integrated circuit according to an embodiment of the present invention, the address driver for driving the latched input address to output the address drive signal in the test mode, by decoding the address drive signal An address decoding section provided to a target circuit section, which is a circuit under test, and a global line interposed between the address driving section and the address decoding section, wherein the address driving signal is equal to the number of latched input addresses. The signal is transmitted on a global line, and the output signal of the address decoding unit is transmitted on a local line.

According to another aspect of the present invention, a semiconductor integrated circuit may include an address latch unit including n latch units that receive and latch n input address signals when a test mode signal is activated. An address address driver including n drive units corresponding to the n latch units to provide n address drive signals, and a target circuit unit configured to decode the n address drive signals to decode the 2 ⁿ decoded signals to be a circuit under test; And a global line interposed between the address driver and the address decoder, wherein the address drive signal is transmitted to the n global lines, and the 2 ⁿ decoded signals are local lines. line).

In accordance with another aspect of the present invention, a method of controlling a semiconductor integrated circuit may include transmitting an address driving signal to a global line by the number of latched input addresses, and decoding the address driving signal. The decoded signal includes transmitting on a local line and connecting the decoded signal transmitted on the local line to a target circuit, which is a circuit under test.

According to an embodiment of the present invention, the number of global line wirings can be reduced by wiring the decoded signal to local lines. In short, by decoding the address, wiring the buffered signal to the global line, and arranging the address decoding section adjacent to the target circuit section, the decoded signal from the address decoding section to the target circuit section can be routed to the local line. Thereby, the number of global line wirings can be reduced by wiring the number of global line wirings in the same number as the number of input addresses. As a result, the number of global line wirings can be reduced, thereby increasing the efficiency of the layout area.

Hereinafter, a semiconductor integrated circuit according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a conceptual block diagram of a semiconductor integrated circuit 100 according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor integrated circuit 100 may include an address latch unit 110, an address driver 120, an address decoding unit 130, and a target circuit unit 140.

First, the address latch unit 110 may respond to a series of addresses, for example, the first to seventh addresses ADDR <0: 6>, the test mode signal TMRS, and the reset signal RESET. The seventh latch address ILA <0: 7> is provided. When the test mode signal TMRS is activated, the address latch unit 110 latches with respect to the first to seventh addresses ADDR <0: 6>, which are input to the first to seventh latch addresses ILA <0: 7>. ) Can be provided. Here, the test mode signal TMRS may be provided as a combination of clock commands such as CAS, RAS, WE, and the like, such as a mode register set (MRS) or a special mode register set (SMRS). Meanwhile, when the reset signal RESET is activated, the address latch unit 110 may be initialized regardless of the first to seventh addresses ADDR <0: 6>. In an embodiment of the present invention, seven address signals are illustrated as input address signals for the test mode, but the present invention is not limited thereto.

The address driver 120 buffers the first to seventh latch addresses ILA <0: 7> to provide the first to seventh drive address signals LA <0: 6> with improved driving capability. The first to seventh driving address signals LA <0: 6> are wired on a global line.

Conventionally, the latched address is decoded and buffered to improve driving capability, and then wired to a global line corresponding to the number of decoded addresses. Therefore, since a large number of decoded signals are wired to the global lines, it may be difficult to arrange the lines in the layout. That is, the pitch between lines or the width of lines for many global lines has become a limiting factor in arranging lines.

However, according to one embodiment of the present invention, the buffered drive address signal is wired to the global line so as to reduce the number of wires of the global line. In this way, a global line wiring number equal to the number of input addresses can be obtained.

Subsequently, the address decoding unit 130 decodes the first to seventh driving address signals LA <0: 6> to provide the first to 128th decoding signals TM <0: 127>. Although not shown, the address decoding unit 130 is illustrated as including a conventional decoder. Since the address decoding unit 130 can provide a decoding signal that is a test signal only before being provided to the circuit unit to be tested, that is, the target circuit unit 140 (target ciruit), it is possible to use a signal after being wired to a global line. Do. In addition, the first to 128th decoding signals TM <0: 127> are wired to local lines.

Preferably, the address decoding unit 130 may be disposed adjacent to the target circuit unit 140. In addition, according to the number and type of the target circuit unit 140, it is not excluded that a plurality is provided.

The target circuit unit 140 is a circuit under test, and a plurality of target circuit units 140 may be provided according to each test purpose. For example, the target circuit unit 140 may include an input / output terminal (DQ) related circuit unit, a read mode circuit unit, a write mode circuit unit, and an operation verification circuit unit for each bank. Accordingly, a plurality of address decoding units 130 may also be provided according to the number and type of the target circuit units 140, and are arranged to be adjacent to each target circuit unit 140, so that the wiring is easily performed when wiring with local wiring. can do.

FIG. 2 is a conceptual diagram conceptually illustrating positions of the address decoding unit 130 and the target circuit unit 140 according to the floor plan of the semiconductor integrated circuit.

Referring to FIG. 2, an address decoding unit 130 is disposed adjacent to each target circuit unit 140. Therefore, the local line may be wired between the address decoding unit 130 and the target circuit unit 140. In addition, since only the first to seventh driving addresses LA <0: 6> serving as input signals of the address decoding unit 130 are wired as global lines, it is understood that the number of wires of the global lines can be reduced. Can be.

Here, the target circuit unit 140 is illustrated as being disposed at different positions for each bank, but is not limited thereto. In addition, it is illustrated that necessary decoding addresses can be distinguished according to each target circuit unit 140. In other words, each address decoding unit 130 may connect only the necessary address signals from the first to seventh driving addresses LA <0: 6> wired to the global line to the local line according to the target circuit unit 140. Exemplarily illustrated that the present invention is not limited thereto. Each address decoding unit 130 may use the same first to seventh driving addresses LA <0: 6>.

3 is a conceptual block diagram of the address latch unit 110 according to FIG. 1.

Referring to FIG. 3, the address latch unit 110 includes first to seventh latch units 110a to 110g.

Each of the first to seventh latch units 110a to 110g corresponds to each input address, the first to seventh addresses ADDR <0: 6>, and includes a test mode signal TMRS and a reset signal RESET. Is commonly received. Thus, the first to seventh latch units 110a-110g receive the first to seventh addresses ADDR <0: 6> and provide the first to seventh latch addresses ILA <0: 6>. . As described above, when the test mode signal TMRS is activated, the latch address may be provided by the latch unit corresponding to the input address.

This will be described in more detail with reference to FIG. 4.

4 is a detailed circuit diagram of the first latch unit 110a according to FIG. 3.

The configuration and operation principle of each of the first to seventh latch units 110a-110g are similar, but only the input addresses received are different. Therefore, the first latch unit 110a will be described in detail, and the description of the remaining second to seventh latch units 110b to 110g will be replaced.

Referring to FIG. 4, the first latch unit 110a includes a transmission unit 111, an initialization unit 112, and a latch unit 113.

First, the transmission unit 111 includes a transmission gate TR. The transmission gate TR may be turned on when the test mode signal TMRS is activated, that is, when the test mode signal TMRS is at a high level to transmit the first address ADDR <0>.

The initialization unit 112 includes an NMOS transistor NM. The NMOS transistor NM includes a gate receiving the reset signal RESET, a drain connected to the node a, and a source connected to the ground power supply VSS. Thus, when receiving the activated reset signal RESET, the NMOS transistor NM lowers the level of the node a to the ground power supply VSS level, thereby providing a low level first latch address ILA <0>. .

The latch unit 113 includes second and third inverters INV2 and INV3. The second and third inverters INV2 and INV3 are connected in a latch type to reverse latch the level of the node a.

Subsequently, when the operation of the first latch unit 110a is described, when the activated high level test mode signal TMRS is received, the transmission gate TR is turned on to transmit the first address ADDR <0>. Let's do it. This then provides the first latch address ILA <0> via the latch 113 and the fourth inverter INV4.

5 is a block diagram of the address driver 120 of FIG. 1.

Referring to FIG. 5, the address driver 120 buffers the first to seventh latch addresses ILA <0: 6> and provides the first to seventh drive addresses LA <0: 6>. The address driver 120 includes first to seventh drive units 120a to 120g. This indicates that each driving unit is provided to correspond to the first to seventh latch addresses ILA <0: 6>. It can be seen that the first to seventh driving units 120a-120g are also provided to correspond to the respective latch units of the address latch unit (see 110 in FIG. 1).

6 is a detailed circuit diagram of the first driving unit 120a according to FIG. 5.

The configuration and operation principle of each of the first to seventh driving units 120a to 120g are similar, except that only the latch addresses received are different. Therefore, the overlapping description will be avoided, and only the first driving unit 120a will be described.

Referring to FIG. 6, the first driving unit 120a includes first and second inverters IN1 and IN2. That is, as a driving unit like a normal buffer unit, the first driving address LA <0 having improved driving capability by passing the first latch address ILA <0> through the first and second inverters IN1 and IN2. >) Can be provided.

7 is a timing diagram illustrating an operating characteristic of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.

1 to 7, the first to seventh addresses ADDR <0: 6> are provided as the first to seventh latch addresses ILA <0: 6> when the test mode signal TMRS is activated. Can be. Subsequently, the first to seventh driving addresses LA <0: 6> are provided via the address driver 120. In this case, the first to seventh driving addresses LA <0: 6> according to the exemplary embodiment of the present invention are signals wired to global lines. That is, it can be seen that the number of wires connected to the global line is reduced than before. Thereafter, the first to 128th decoding signals TM <0: 127> may be provided through the address decoding unit 130. In FIG. 7, the decoding signals of any one of the first to 128th decoding signals TM <0: 127> are illustrated.

As described above, according to an embodiment of the present invention, it is possible to prevent the wiring to the global line equal to the number of decoding signals for the test mode. Unlike the prior art, from the address decoding unit 130 to the target circuit unit 140 by latching an address, wiring the buffered signal to a global line, and arranging the address decoding unit 130 adjacent to the target circuit unit. The decoded signal may be wired to a local line.

8 is a block diagram of a semiconductor integrated circuit diagram according to another embodiment of the present invention.

Referring to FIG. 8, a description overlapping with an embodiment of FIG. 1 will be omitted and will be described in detail with reference to FIG. 1.

Referring to FIG. 8, between the address driver 120 and the address decoder 130, a buffer unit 125 is provided between two divided lines of a global line.

The buffer unit 125 is a kind of repeater or driver. When the wiring of the global line is long, the buffer unit 125 may divide the loading of the global line wiring by first dividing it. Thus, cross coupling noise between global lines can be reduced. However, although the wiring length of the global line was divided, the signal was driven through the buffer unit 125 so that the signal can be safely transmitted to the address decoding unit 130 (see 130).

This is merely an embodiment showing the spirit of the present invention, but is not limited thereto. However, if the signal before decoding is wired to the global line, and the decoded signal as the test signal is wired to the local line, this satisfies the object scope of the present invention, which can exclude the wiring of many decoded signals to the global line. .

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention;

2 is a conceptual diagram conceptually illustrating positions of an address decoding unit and a target circuit unit according to FIG. 1;

3 is a block diagram of an address latch unit according to FIG. 1;

4 is a circuit diagram of a first latch unit according to FIG. 3;

5 is a block diagram of an address driver according to FIG. 1;

6 is a circuit diagram of a first driving signal according to FIG. 5;

7 is a timing diagram illustrating characteristics of a semiconductor integrated circuit according to FIG. 1;

8 is a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: address latch unit 120: address driver

130: address decoding unit 140: target circuit unit

Claims (11)

An address driver for driving a latched input address to output an address driving signal in a test mode; An address decoding unit which decodes the address driving signal and provides it to a target circuit unit which is a circuit under test; And A global line interposed between the address driver and the address decoder, And the address driving signal is transmitted to the global line equal to the number of latched input addresses, and the output signal of the address decoding unit is transmitted to a local line. The method of claim 1, And the address decoding unit is provided in plurality according to the target circuit unit. The method of claim 1, And dividing each of the global lines, and further comprising a buffer unit interposed between the divided global lines. An address latch unit including n latch units for receiving and latching n (n is a natural number of two or more) input address signals when the test mode signal is activated; An address driver including n drive units corresponding to the n latch units to provide n address drive signals; An address decoding unit for decoding the n address driving signals and providing 2 ⁿ decoding signals to a target circuit unit which is a circuit under test; And A global line interposed between the address driver and the address decoder, And the address driving signal is transmitted on the n global lines, and the 2 ⁿ decoding signals are transmitted on a local line. The method of claim 4, wherein And the address decoding unit is provided in plurality according to the target circuit unit. The method of claim 5, And the plurality of address decoding units supports a test mode disposed adjacent to the target circuit unit. The method of claim 4, wherein Each latch unit of the address latch unit is And a test mode initialized regardless of the input address by a reset signal. The method of claim 4, wherein Each of the drive units of the address driver, And a test mode for buffering each output signal of the address latch unit. The method of claim 4, wherein And dividing each of the global lines, and further comprising a buffer unit interposed between the divided global lines. Transmitting address driving signals to the global line by the number of latched input addresses; Transmitting the decoded signal obtained by decoding the address driving signal to a local line; And And connecting and providing the decoded signal transmitted to the local line to a target circuit, which is a circuit under test. The method of claim 10, And a control mode in which the decoded signal and the target circuit unit are adjacently connected.

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