KR20090105152A - Semiconductor memory devices having capacitors and methods of forming the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device including a capacitor and a method for forming the same are provided to minimize power consumption by supplying a voltage to a plate electrode in only part of cells. CONSTITUTION: A semiconductor memory device includes a pair of insulation line patterns(120), a plurality of storage nodes(114a), a plate line pattern(124a), and a capacitor dielectric layer(122). The insulation line patterns are extended on the substrate along one direction. The storage nodes are arranged on the substrate between the insulation line patterns. The storage nodes form a first row and a second row in one direction. The plate line pattern is arranged between the insulation line patterns and is extended along one direction. The plate line pattern covers the surface of the storage nodes. The capacitor dielectric layer is interposed between the plate line pattern and the storage nodes.

Description

A semiconductor memory device including a capacitor and a method of forming the same {SEMICONDUCTOR MEMORY DEVICES HAVING CAPACITORS AND METHODS OF FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element and a method of forming the same, and more particularly, to a semiconductor memory element including a capacitor and a method of forming the same.

Semiconductor memory devices may include various kinds of data storage elements. For example, there are semiconductor memory devices that store logic data in electrically isolated floating gates. Depending on the amount of charge stored in the floating gate, the threshold voltage of the unit cell of the floating gate type semiconductor memory device may vary. The floating gate type semiconductor memory device may store and / or read logic data by using the threshold voltage difference of the unit cell.

As another example, one semiconductor memory device may store logical data in a capacitor. The voltage of the bit line may change depending on the amount of charge stored in the capacitor. In general, the capacitor may include a storage node, a dielectric layer, and a plate electrode. Typically, the cells in a block unit of the DRAM device share one plate electrode.

As the semiconductor industry is highly developed, demands for high integration, low power consumption, and high speed of semiconductor memory devices are increasing. However, various problems may arise in the case of simply scaling down the semiconductor memory device. For example, as the operating voltage is decreased, the sensing margin of the semiconductor memory device may be reduced. As a result, problems such as lowering the reliability of the semiconductor device and lowering the operation speed may occur. In addition, in the case of DRAM devices, the unit cells of the block share one plate electrode, thereby increasing power consumption, interference of other semiconductor elements (eg, bit lines, etc.), and signal delay by an operating voltage supplied to the plate electrode. Problems such as (signal delay) may occur.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned general problems, and a technical object of the present invention is to provide a semiconductor memory device including a capacitor optimized for high integration and a method of forming the same.

Another object of the present invention is to provide a semiconductor memory device including a capacitor capable of increasing a sensing margin and a method of forming the same.

Another object of the present invention is to provide a semiconductor memory device including a capacitor capable of reducing power consumption, and a method of forming the same.

A semiconductor memory device for solving the above technical problems is provided. This element includes a pair of insulated line patterns extending side by side along one direction on a substrate; A plurality of storage nodes disposed on a substrate between the pair of insulating line patterns and forming a first row and a second row in the one direction; A plate line pattern disposed between the pair of insulating line patterns and extending in the one direction and covering surfaces of the plurality of storage nodes; And a capacitor dielectric interposed between the plate line pattern and the plurality of storage nodes.

In example embodiments, the storage node may include a portion lower than an upper surface of the insulating line pattern. The storage node may include a portion in contact with the insulation line pattern and a portion in non-contact with the insulation line pattern. In this case, a portion lower than an upper surface of the insulating line pattern of the storage node may include the non-contact portion. The upper surface of the contacted portion may be higher than the upper surface of the non-contacted portion and the upper surface of the contacted portion may be coplanar with the upper surface of the insulation line pattern. The storage node may include a first surface covered by the plate line pattern and a second surface not covered by the plate line pattern. The second surface may include a contact surface of the contacted portion and the insulation line pattern and an upper surface of the contacted portion.

A method of forming a semiconductor memory device for solving the above technical problems is provided. The method comprises a pair of insulated line patterns extending side by side along one direction on a substrate, and a plurality of storage nodes disposed on the substrate between the insulated line patterns and forming a first row and a second row in the one direction. Forming; Forming a capacitor dielectric layer on the substrate having the storage nodes and the insulating line patterns; And forming a plate line pattern on the capacitor dielectric layer and between the pair of insulating line patterns.

In example embodiments, the forming of the insulating line patterns and the storage nodes may include forming a mold insulating layer on a substrate; Patterning the mold insulating layer to form a plurality of holes forming the first row and the second row in one direction; Respectively forming a plurality of spare storage nodes in the plurality of holes; Recessing at least portions of the preliminary storage nodes lower than an upper surface of the mold insulating layer to form storage nodes; And patterning the mold insulating layer to form a pair of insulating line patterns arranged side by side in the one direction, wherein the storage nodes of the first and second rows are disposed between the pair of insulating line patterns. have.

In example embodiments, the recessing of the at least portions of the preliminary storage node and the patterning of the mold insulating layer may include forming a pair of mask patterns arranged side by side in the one direction on the mold insulating layer. Forming one of the pair of mask patterns covering portions of the spare storage nodes in the first column and the other covering portions of the spare storage nodes in the second column; Recessing exposed portions of the storage nodes using the mask patterns as an etch mask to form the storage nodes; And anisotropically etching the mold insulating layer using the mask patterns as an etching mask to form the insulating line pattern.

According to an embodiment, the forming of the preliminary storage node may include: conformally forming a storage conductive layer on the substrate having the holes; Forming a sacrificial layer filling the holes on the storage conductive layer; And planarizing the sacrificial layer and the storage conductive layer until the top surface of the insulating line pattern is exposed to form a preliminary storage node and a sacrificial pattern sequentially stacked in the hole. The sacrificial layer may be etched by the anisotropic etching of the mold insulating layer.

In an embodiment, the forming of the plate line pattern may include forming a plate conductive film on a substrate having the capacitor dielectric film; And planarizing the plate conductive layer to remove the plate conductive layer on the insulating line pattern. The planarizing of the plate conductive layer may include planarizing the plate conductive layer and the capacitor dielectric layer until the insulating line pattern is exposed.

As described above, the plate line pattern covers the storage nodes of the first and second columns between the pair of insulated line patterns. That is, the plate line pattern covers only the storage nodes forming two columns. Accordingly, in operation of the semiconductor memory device, the voltage may be supplied to the plate electrode only to some cells, not to cells in a block unit. As a result, power consumption of the semiconductor memory device can be minimized and optimized for high integration. In addition, the plate line pattern covers only the storage nodes that make up two columns, thereby utilizing the second charges stored in the plate line pattern and of opposite types to the first charges together with the first charges stored in the storage node. Data can be read. In this case, the voltage of the bit line may be changed by the first charges, and the sensing margin of the semiconductor memory device may be increased by changing the voltage of the bit bar line by the second charges.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

1 is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, a lower insulating film 102 is disposed on a substrate 100, and a plurality of buried plugs 104 are formed in the lower insulating film 102. The investment plugs 104 are two-dimensionally arranged on the substrate 100. Each of the investment plugs 104 may be electrically connected to one end of a switching element (eg, a diode or a MOS transistor, etc.) formed in the substrate 100 under the lower insulating layer 102. The lower insulating layer 102 may be a single layer or a multilayer. For example, the lower insulating film 102 may include at least one selected from an oxide film, a nitride film, and an oxynitride film. The investment plugs 104 are formed of a conductive material. For example, the investment plugs 104 may include a doped semiconductor, a metal (ex, tungsten, titanium, tantalum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) and a metal silicide (ex, titanium silicide, Tungsten silicide, cobalt silicide, or the like).

A plurality of insulating line patterns 120 extend along the first direction on the lower insulating layer 102. The insulating line patterns 120 are spaced apart from each other in a second direction perpendicular to the first direction. The first direction corresponds to the y-axis direction of the drawing and the second direction corresponds to the x-axis direction of the drawing. The first and second directions are parallel to the top surface of the substrate 100. The insulating line patterns 120 may be arranged at equal intervals in the second direction.

A plurality of storage nodes 114a are disposed between a pair of adjacent insulating line patterns 120. The storage nodes 114a between the pair of insulating line patterns 120 form a first column R1 and a second column R2 in the first direction. The first row R1 and the second row R2 are spaced apart from each other in the second direction. The storage nodes 114a of the first row R1 are adjacent to any one of the pair of insulating line patterns 120, and the storage nodes 114a of the second row R2 are of the pair. Adjacent one of the insulating line patterns 120. The first row R1, the second row R2, and the insulating line pattern 120 may be repeatedly arranged on the lower insulating layer 102 along the second direction. Storage nodes 114a of the first row R1 and storage nodes 114a of the second row R2 are adjacent to both sides of one insulating line pattern 120, respectively.

The storage nodes 114a of the first row R1 and the storage nodes 114a of the second row R2 may be arranged in a zigzag form along the first direction. For example, the storage nodes 114a of the first row R1 may be arranged at a specific pitch in the first direction. In this case, the storage nodes 114a of the second row R2 are moved to the first direction by 1/2 of the specific pitch based on the storage nodes 114a of the first row R1. May be arranged in each of the two fields.

The storage nodes 114a are connected to the investment plugs 104 respectively. An etch stop layer 106 may be disposed on the lower insulating layer 102. In this case, the lower portions of the storage nodes 114a are respectively disposed in the holes 112 ′ penetrating the etch stop layer 106. Upper portions of the storage nodes 114a protrude higher than an upper surface of the etch stop layer 106. The insulating line pattern 120 is disposed on the etch stop layer 106. The etch stop layer 106 may include an insulating material having an etch selectivity with respect to the lower insulating layer 102. For example, when the lower insulating film 102 is formed of an oxide film, the etch stop layer 106 may include at least one selected from a nitride film and an oxynitride film.

When at least a lower portion of the insulating line pattern 120 has an etch selectivity with respect to at least an upper portion of the lower insulating layer 106, the etch stop layer 106 may be omitted. In example embodiments, the insulating line pattern 120 may include an interlayer insulating pattern 108a and a hard mask pattern 110a that are sequentially stacked. In this case, when at least an upper portion of the lower insulating layer 106 is formed of an insulating material having an etching selectivity with respect to the interlayer insulating pattern 108a, the etch stop layer 106 may be omitted.

At least some of the storage nodes 114a may have an upper surface lower than an upper surface of the insulating line pattern 120. For example, each of the storage nodes 114a may include a portion 113a in contact with the insulation line pattern 120 and a portion 113b in contact with the insulation line pattern 120. In this case, the upper surface of the non-contact portion 113b may be lower than the upper surface of the insulating line pattern 120. The upper surface of the contacted portion 113a forms a coplanar with the upper surface of the insulating line pattern 120. That is, the contacted portion 113a may have an upper surface that is substantially the same height as the upper surface of the insulating line pattern 120. Of course, the upper surface of the contacted portion 113a is higher than the upper surface of the non-contacted portion 113b.

Meanwhile, according to an exemplary embodiment, the entire upper surface of each of the storage nodes 114a may be lower than the upper surface of the insulating line pattern 120. According to an embodiment of the present invention, the insulating line pattern 120 and the storage nodes 114a may be spaced apart from each other. That is, the storage nodes 114a and the pair of insulating line patterns 120 in the first and second columns may be spaced apart from each other.

The storage node 114a may be in the form of a cylinder as shown. That is, the storage node 114a may include a plate portion and a wall portion extending upward from an edge of the plate portion. The flat plate portion is disposed on the lower insulating film 102 and connected to the investment plug 104. A portion of the wall portion may contact the insulating line pattern 120 and another portion of the wall portion may be spaced apart from the insulating line pattern 120. Alternatively, the storage node 114a may have a shape other than a cylinder shape. The storage node 114a is formed of a conductive material. For example, the storage node 114a may be a doped semiconductor, a conductive metal nitride (ex, titanium nitride, tantalum nitride or tungsten nitride, etc.), a metal (ex, precious metals such as ruthenium, iridium, etc., titanium, tantalum, etc.). And at least one selected from a conductive metal oxide (ex, iridium oxide, etc.).

As described above, the insulation line pattern 120 may include an interlayer insulation pattern 108a and a hard mask pattern 110a that are sequentially stacked. In this case, the hard mask pattern 110a may be formed of an insulating material having an etching selectivity with respect to the interlayer insulating pattern 108a. For example, the interlayer insulating pattern 108a may be formed of an oxide, and the hard mask pattern 110a may be formed of at least one selected from nitride and oxynitride. According to one embodiment of the present invention, the entirety of the insulating line pattern 120 may be formed of one insulating material.

A capacitor dielectric layer 122 is conformally disposed on the surfaces of the storage nodes 114a. The capacitor dielectric layer 122 may partially cover the entire surface of each of the storage nodes 114a. That is, each of the storage nodes 114a may be divided into a first surface and a second surface. The capacitor dielectric layer 122 is disposed on the first surface. In contrast, the capacitor dielectric layer 122 does not exist on the second surface. The second surface of each of the storage nodes 114a may include an upper surface of the contacted portion 113a and a contact surface between the contacted portion 113a and the insulating line pattern 120.

The capacitor dielectric layer 122 may extend on side surfaces of the insulating line pattern 120. The capacitor dielectric layer 122 may be disposed on an inner surface of the storage node 114a having a cylindrical shape. The capacitor dielectric layer 122 disposed on a side of the contact portion 113a other than the contact surface may have an upper surface coplanar with an upper surface of the contact portion 113a. In this case, the capacitor dielectric layer 122 may not exist on the top surface of the insulating line pattern 120.

The capacitor dielectric layer 122 may include at least one selected from oxides, nitrides, oxynitrides, and high dielectric materials. The high dielectric material may be an insulating material having a higher dielectric constant than that of nitride. For example, the high dielectric material may be at least one selected from an insulating metal oxide such as hafnium oxide or aluminum oxide.

The plate line pattern 124a is disposed on the capacitor dielectric layer 122 between the pair of insulating line patterns 120 adjacent to each other. The plate line pattern 124a covers the storage nodes 114a in the first and second columns R1 and R2 between the pair of insulating line patterns 120. The plate line pattern 124a covers surfaces of the storage nodes 114a between the pair of insulating line patterns 120. The plate line pattern 124a covers the top surfaces of portions of the storage nodes 114a that are lower than the top surface of the insulating line pattern 120. The plate line pattern 124a does not cover the top surface coplanar with the top surface of the insulating line pattern 120 of the storage node 114a. That is, the upper surface of the plate line pattern 124a may be coplanar with the upper surface of the insulating line pattern 120.

The plate line patterns 124a extend side by side along the first direction on the substrate 100. That is, the insulating line patterns 120 and the plate line patterns 124a may be alternately arranged along the second direction. The plate line pattern 124a is formed of a conductive material. For example, the plate line pattern 124a may include at least one selected from doped semiconductors, metals, conductive metal nitrides, and metal silicides. The plate line pattern 124a corresponds to plate electrodes of capacitors arranged along the adjacent first and second columns R1 and R2.

According to the semiconductor memory device described above, one plate line pattern 124a covers the storage nodes 114a between the pair of insulating line patterns 120 adjacent to each other. That is, a plurality of plate line patterns 124a separated from each other are disposed on the substrate 100. Accordingly, the operation voltage can be supplied to the plate line pattern 124a of the cells arranged in the two columns during the operation of the semiconductor memory element. As a result, in the operation of the semiconductor memory element, the operating voltage is applied only to the plate electrodes of the capacitors of some cells in the block unit cells. As a result, power consumption of the semiconductor memory device can be minimized and reliability deterioration can be minimized.

Meanwhile, word lines 170 arranged side by side on the substrate 100 and bit lines 150 crossing the word lines 170 may be disposed. The bit lines 150 may extend in the first direction, and the word lines 170 may extend in the second direction. The word lines 170 and the bit lines 150 may be disposed at lower positions than the storage nodes 114a. The bit lines 150 may be parallel to the plate line pattern 124a. The bit lines 150 may be disposed under the insulating line pattern 120.

A semiconductor memory device according to the present invention will be described in more detail with reference to the circuit diagram of FIG. 3.

3 is a circuit diagram illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention.

1, 2, and 3, the bit line BL and the bit bar line BLB are connected to both terminals of a sense amplifier SA. In FIG. 1, one of the pair of bit lines 150 adjacent to each other corresponds to the bit line BL of FIG. 3, and the other corresponds to the bit bar line BLB of FIG. 3. A plurality of word lines WL0, WL1,..., WLn−1, WLn cross the bit line BL and the bit bar line BLB side by side. The plate line PL is disposed between the bit line BL and the bit bar line BLB. The plate line PL corresponds to the plate line pattern 124a of FIG. 1.

A plurality of first unit cells includes odd-numbered word lines WL0, WL2,..., WLn-1 and the bit line BL among the plurality of word lines WL0, WL1,..., WLn-1, WLn. Are arranged at intersections of. A plurality of second unit cells of the word lines WL1, WL3,..., WLn and the bit bar line BLB of the plurality of word lines WL0, WL1,..., WLn-1, WLn. It is arranged at intersections respectively. Each of the first unit cells includes a first switching element and a first capacitor. The first switching element may be a MOS transistor having three terminals. The first capacitor includes a first electrode and a second electrode separated from each other by a capacitor dielectric layer. The first terminal (gate) of the first switching element is connected to one of the odd word lines WL0, WL2,..., WLn-1, and the second terminal is connected to the bit line BL. The three terminals may be connected in series with the first electrode of the first capacitor. The second electrode of the first capacitor is connected to the plate line PL. Similarly, each second unit cell includes a second switching element and a second capacitor. The second switching element may be a MOS transistor having three terminals. The second capacitor includes a first electrode and a second electrode separated from each other by a capacitor dielectric layer. The first terminal (gate) of the second switching element is connected to one of the even-numbered word lines WL0, WL3,..., WLn, and the second terminal is connected to the bit bar line BLB. The three terminals may be connected in series with the first electrode of the second capacitor. The second electrode of the second capacitor is connected to the plate line PL. The first electrodes of the first and second capacitors correspond to the storage nodes of FIGS. 1 and 2. The second electrodes and the plate line PL of the first and second capacitors correspond to the plate line pattern 124a of FIGS. 1 and 2.

The first dummy word line DWL1 and the second dummy word line DWL2 are arranged side by side on one side of the plurality of word lines WL0, WL1,..., WLn-1, WLn. The first and second dummy word lines DWL1 and DWL2 cross the bit line BL and the bit bar line BLB. A first selection transistor TR1 is disposed at an intersection point of the first dummy word line DWL1 and the bit line BL, and crosses the second dummy word line DWL2 and the bit bar line BLB. The second selection transistor TR2 is disposed at the point. The gate of the first select transistor TR1 is connected to the first dummy word line DWL1, and the first source / drain and the second source / drain of the first select transistor TR1 are the bit line BL. ) And the plate line PL, respectively. Similarly, a gate of the second select transistor TR2 is connected to the second dummy word line DWL2, and a first source / drain and a second source / drain of the second select transistor TR2 are connected to each other. It is connected to the bit bar line BLB and the plate line PL, respectively.

A reading method will be described among the data driving methods of the above-described semiconductor memory element. First, the bit line BL, the plate line PL, and the bit bar line BLB are precharged. The precharging may be a half value of the power supply voltage Vcc. The switching element of the selected unit cell 200 is turned on by applying a sensing voltage to the word line WL0 connected to the selected unit cell 200 among the plurality of first and second unit cells. Accordingly, the first electrode E1 (hereinafter, referred to as the selected first electrode) of the capacitor C of the selected cell 200 is connected to the bit line BL. The second select transistor TR2 connected to the bit bar line BLB is turned on through the second dummy word line DWL2. Accordingly, the bit bar line BLB and the plate line PL are electrically connected to each other. That is, the second electrode E2 (hereinafter referred to as the selected second electrode) of the capacitor C of the selected cell 200 is electrically connected to the bit bar line BLB. Preferably, the word line WL0 and the second dummy word line DWL2 of the selected cell 200 are simultaneously selected.

As a result, the voltage of the bit line BL precharged by the first charges stored in the selected first electrode E1 is changed. In this case, second charges opposite to the first charges are stored in the selected second electrode E2. The bit bar line BLB and the selected second electrode E2 are connected to each other by turning on the second selection transistor TR2. Thus, the voltage of the bit bar line BLB is changed by the second charges of the selected second electrode E2. Since the first charges and the second charges are opposite types, the voltage change direction of the bit line BL and the voltage change direction of the bit bar line BL are opposite to each other. For example, when positive charges are stored in the selected first electrode E1, negative charges are stored in the selected second electrode E2. Accordingly, in the read operation, the voltage of the bit line BL is increased by the positive charges, and the voltage of the bit bar line BLB is reduced by the negative charges. As a result, the voltage difference between the bit line BL and the bit variance BLB is increased to increase the sensing margin by the semiconductor memory device.

Meanwhile, according to an exemplary embodiment, the word lines 170 may extend along the first direction, and the bit lines 150 may extend along the second direction. That is, the word lines 170 may be parallel to the plate line pattern 124a, and the bit lines 150 may be perpendicular to the plate line pattern 124a.

Preferably, the semiconductor memory device according to the present invention described above is a DRAM device including a capacitor.

Next, a method of forming a semiconductor memory device according to the present invention will be described with reference to the drawings.

4A to 8A are plan views illustrating a method of forming a semiconductor memory device according to an embodiment of the present invention, and FIGS. 4B to 8B are cross-sectional views taken along line II-II 'of FIGS. 5A to 9A, respectively.

4A and 4B, a lower insulating film 102 is formed on the substrate 100, and a plurality of buried plugs 104 penetrating the lower insulating film 102 are formed. An etch stop layer 106 and a buried insulating film 111 are sequentially formed on the substrate 100 having the buried plugs 104. In example embodiments, the etch stop layer 106 may be omitted. The investment insulating layer 111 may be formed as a single layer. Alternatively, the investment insulating layer 111 may include an interlayer insulating layer 108 and a hard mask layer 110 that are sequentially stacked. The hard mask layer 110 may include an insulating material having an etch selectivity with respect to the interlayer insulating layer 108. The etch stop layer 106 may include an insulating material having an etch selectivity with respect to the interlayer insulating layer 108.

The buried insulating layer 111 and the etch stop layer 106 are successively patterned to form a plurality of holes 112 forming a first row R1 and a second row R2 in a first direction. The second row R2 is disposed next to the first row R1. Holes 112 may be formed on the substrate 100 to form the plurality of first columns R1 and the plurality of second columns R2. In this case, the first columns R1 and the second columns R2 may be alternately arranged in a second direction perpendicular to the first direction. The first direction and the second direction may correspond to the y-axis direction and the x-axis direction of FIG. 1, respectively.

5A and 5B, a storage conductive film is conformally formed on the substrate 100 having the holes 112, and a sacrificial layer filling the holes 112 is formed on the storage conductive layer. The sacrificial layer and the storage conductive layer are planarized until the buried insulating layer 111 is exposed to form the preliminary storage node 114 and the sacrificial pattern 116 that are sequentially stacked in the holes 112. The sacrificial pattern 116 may be formed of a material that is equal to or higher than an etching rate of the interlayer insulating layer 108. For example, the sacrificial pattern 116 may be formed of SOG oxide or the like.

Mask patterns 118 parallel to each other are formed on the buried insulating layer 111. The mask patterns 118 extend side by side in the first direction. The mask patterns 118 are spaced apart from each other in the second direction. Spare storage nodes 114 of the first and second columns R1 and R2 are disposed between the pair of adjacent mask patterns 118. Each mask pattern 118 may cover portions of the spare storage nodes 114 adjacent thereto. In detail, any one of the pair of mask patterns 118 may be configured as one of the preliminary storage nodes 114 among the first and second columns R1 and R2 between the pair of mask patterns 118. The other one of the pair of mask patterns 118, the other one of the first and second columns R1 and R2 between the pair of mask patterns 118, and the other spare storage nodes 113. To cover parts of the. The portions of the preliminary storage nodes 114 of the first and second columns R1 and R2 adjacent to both sides of the mask pattern 118 are covered.

6A and 6B, the preliminary storage nodes 114 are recessed to form the storage nodes 114a using the mask patterns 118 as an etch mask. Each storage node 114a may include a first portion 113a and a second portion 113b. The first portion 113a is an unrecessed portion, and the second portion 113b is Recessed part. In other words, the first portion 113a is a portion covered by the mask pattern 118, and the second portion 113b is a portion not covered by the mask pattern 118.

The hard mask layer 110 may be etched using the mask patterns 118 as an etch mask until the interlayer insulating layer 108 is exposed. As a result, a hard mask pattern 110a is formed under the mask pattern 118. The process of etching the hard mask layer 110 may be performed before or after the process of recessing the preliminary storage nodes 114.

An upper portion of the sacrificial pattern 116 may be etched by a process of recessing the preliminary storage node 114 and / or a process of etching the hard mask layer 110.

Meanwhile, according to an embodiment of the present invention, the mask pattern 118 may not cover portions of the spare storage nodes 114. In this case, the entire top surfaces of the storage nodes 114a may be recessed lower than the top surfaces of the hard mask patterns 110a.

7A and 7B, the interlayer insulating layer 108 is anisotropically etched using the mask patterns 118 and / or the hard mask pattern 110a as an etch mask. As a result, the insulating line pattern 120 is formed. The insulating line pattern 120 includes an interlayer insulating pattern 108a and a hard mask pattern 110a that are sequentially stacked. After etching the interlayer insulating layer 108, the etch stop layer 106 may be exposed. In this case, a lower portion of each storage node 114a may be disposed in the remaining hole 112 'formed in the etch stop layer 106. The remaining hole 112 ′ corresponds to a portion surrounded by the etch stop layer 106 of the hole 112. During the anisotropic etching of the interlayer insulating film 108, the sacrificial pattern 116 is also etched.

The first portion 113a of the storage nodes 114a may correspond to a portion in contact with the insulating line pattern 120, and the second portion 113b may be in contact with the insulating line pattern 120. It may correspond to a part. The storage nodes 114a may be supported by the insulating line pattern 120. Accordingly, even if the height of the storage nodes 114a is increased, it is possible to prevent the inclination phenomenon. In addition, the storage nodes 114a may be further supported by the etch stop layer 106 having the residual hole 112 '. In contrast, when the etch stop layer 106 is omitted, the lower insulating layer 102 may be exposed after etching the interlayer insulating layer 108.

8A and 8B, the mask patterns 118 are removed. The mask patterns 118 may be removed after the interlayer insulating pattern 108a is formed. Alternatively, the mask patterns 118 may be removed after the hard mask pattern 110a and before the formation of the interlayer insulating pattern 108a.

A capacitor dielectric layer 122 is conformally formed on the substrate 100 having the insulating line pattern 120 and the storage nodes 114a. The plate conductive layer 124 is formed on the capacitor dielectric layer 122. The plate conductive layer 124 fills the spaces between the insulating line patterns 120.

The plate conductive layer 124 is planarized until the capacitor dielectric layer 122 on the top surface of the insulating line pattern 120 is exposed to form the plate line pattern 124a of FIGS. 1 and 2. That is, the plate lines 124a are separated from each other by removing the plate conductive layer 124 on the insulating line pattern 120 by the planarization process. The exposed capacitor dielectric layer 122 may be planarized until the top surface of the insulating line pattern 120 is exposed. That is, the plate conductive layer 124 and the capacitor dielectric layer 122 may be continuously planarized until the upper surface of the insulating line pattern 120 is exposed. In this case, the planarization process may be performed by a chemical mechanical polishing process.

The method of forming the semiconductor memory device according to the present invention described above is preferably a method of forming a DRAM element including a capacitor.

1 is a plan view showing a semiconductor memory device according to an embodiment of the present invention.

2 is a cross-sectional view taken along the line II ′ of FIG. 1;

3 is a circuit diagram illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention.

4A through 8A are plan views illustrating a method of forming a semiconductor memory device according to an embodiment of the present invention.

4B-8B are cross sectional views taken along II-II ′ of FIGS. 5A-9A, respectively.

Claims (14)

A pair of insulated line patterns extending side by side along one direction on the substrate; A plurality of storage nodes disposed on a substrate between the pair of insulating line patterns and forming a first row and a second row in the one direction; A plate line pattern disposed between the pair of insulated line patterns and extending in the one direction and covering surfaces of the plurality of storage nodes; And And a capacitor dielectric layer interposed between the plate line pattern and the plurality of storage nodes. The method according to claim 1, And the storage node includes a portion lower than an upper surface of the insulating line pattern. The method according to claim 2, The storage node may include a portion in contact with the insulated line pattern and a portion in non-contact with the insulated line pattern, and a portion lower than an upper surface of the insulated line pattern of the storage node may represent the non-contact portion. A semiconductor memory device comprising. The method according to claim 3, And an upper surface of the contacted portion is higher than an upper surface of the non-contacted portion and the upper surface of the contacted portion is coplanar with an upper surface of the insulating line pattern. The method according to claim 3, The storage node includes a first surface covered by the plate line pattern and a second surface not covered by the plate line pattern, wherein the second surface is in contact with the contact surface of the contacted portion and the insulation line pattern. A semiconductor memory device comprising an upper surface of a portion thereof. The method according to claim 1, And the capacitor dielectric film is interposed between the insulating line pattern and the plate line pattern. The method according to claim 1, The insulating line pattern may include a mold insulating pattern and a hard mask pattern that are sequentially stacked, and the hard mask pattern may include an insulating material having an etch selectivity with respect to the mold insulating pattern. Forming a pair of insulating line patterns extending side by side along one direction on the substrate, and a plurality of storage nodes disposed on the substrate between the insulating line patterns and forming first and second rows in the one direction; ; Forming a capacitor dielectric layer on the substrate having the storage nodes and the insulating line patterns; And Forming a plate line pattern on the capacitor dielectric layer and between the pair of insulated line patterns. The method of claim 8, Forming the insulating line patterns and the storage nodes, Forming a mold insulating film on the substrate; Patterning the mold insulating layer to form a plurality of holes forming the first row and the second row in one direction; Respectively forming a plurality of spare storage nodes in the plurality of holes; Recessing at least portions of the preliminary storage nodes lower than an upper surface of the mold insulating layer to form storage nodes; And Patterning the mold insulating layer to form a pair of insulating line patterns arranged side by side in the one direction, wherein the storage nodes of the first and second columns are disposed between the pair of insulating line patterns. Formation method of the device. The method of claim 9, Recessing at least portions of the spare storage node and patterning the mold insulating film, Forming a pair of mask patterns arranged side by side along the one direction on the mold insulating layer, one of the pair of mask patterns covering portions of the preliminary storage nodes in the first column and the other preliminary storage in the second column Forming to cover portions of the nodes; Recessing exposed portions of the storage nodes using the mask patterns as an etch mask to form the storage nodes; And And anisotropically etching the mold insulating layer using the mask patterns as an etching mask to form the insulating line pattern. The method of claim 10, The mold insulating layer may include an interlayer insulating layer and a hard mask layer that are sequentially stacked, and the anisotropic etching of the mold insulating layer may include a first anisotropic etching of the hard mask layer and a second anisotropic etching of the interlayer insulating layer. Method of forming a memory element. The method of claim 10, Forming the spare storage node, Conformally forming a storage conductive film on the substrate having the holes; Forming a sacrificial layer filling the holes on the storage conductive layer; And Planarizing the sacrificial layer and the storage conductive layer until the top surface of the insulating line pattern is exposed to form a preliminary storage node and a sacrificial pattern sequentially stacked in the hole, wherein the sacrificial layer is formed by etching the mold insulating layer. A method of forming a semiconductor memory device etched by the anisotropic etching. The method of claim 8, Forming the plate line pattern, Forming a plate conductive film on the substrate having the capacitor dielectric film; And And planarizing the plate conductive film so that the plate conductive film on the insulating line pattern is removed. The method of claim 13, And planarizing the plate conductive film includes planarizing the plate conductive film and the capacitor dielectric film until the insulating line pattern is exposed.

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