KR20090104971A - Method for fabricating pillar pattern - Google Patents

Method for fabricating pillar pattern Download PDF

Info

Publication number
KR20090104971A
KR20090104971A KR1020080030165A KR20080030165A KR20090104971A KR 20090104971 A KR20090104971 A KR 20090104971A KR 1020080030165 A KR1020080030165 A KR 1020080030165A KR 20080030165 A KR20080030165 A KR 20080030165A KR 20090104971 A KR20090104971 A KR 20090104971A
Authority
KR
South Korea
Prior art keywords
pillar
substrate
forming
film
pattern
Prior art date
Application number
KR1020080030165A
Other languages
Korean (ko)
Inventor
김광옥
강혜란
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080030165A priority Critical patent/KR20090104971A/en
Publication of KR20090104971A publication Critical patent/KR20090104971A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

PURPOSE: A method for fabricating a pillar pattern is provided to solve a problem of falling of a pillar pattern in forming a pillar neck with a support film. CONSTITUTION: A method for fabricating a pillar pattern is comprised of the steps: forming a plurality of trenches by etching the substrate(21B) as a partly grid format; burying the support film(25) on a trench; etching the substrate partly and forming a plurality of pillar head contacting the supporting film; forming a plurality of pillar necks by etching the substrate isotropically; removing the support film; and forming the support film and the pillar head by the same height.

Description

필라패턴 제조 방법{METHOD FOR FABRICATING PILLAR PATTERN}Pillar pattern manufacturing method {METHOD FOR FABRICATING PILLAR PATTERN}

본 발명은 반도체 소자의 제조 기술에 관한 것으로, 특히 상/하 방향의 채널을 형성하기 위한 필라패턴의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a pillar pattern for forming a channel in an up / down direction.

반도체 소자는 채널의 면적 또는 길이를 증가시키기 위해, 리세스(recess)형, 벌브(bulb)형 및 핀(fin)형의 형태로 진보해 왔다. 그러나, 위와 같은 반도체 소자들은 채널의 길이 또는 면적은 확보할 수 있겠으나, 복잡한 형태의 패턴을 형성해야 하고, 셀 효율(cell efficiency)까지 고려해야 하는 어려움이 있다.Semiconductor devices have evolved into recessed, bulbous and fin shapes to increase the area or length of the channel. However, the semiconductor devices as described above can secure the length or area of the channel, but have a complex pattern and have difficulty in considering cell efficiency.

특히, 소스 및 드레인(source and drain)을 필라패턴(pillar pattern) 내에 상/하로 배치시켜서 상/하 방향의 채널을 유도하는 반도체 소자의 경우, 종횡비가 높은 필라패턴의 특성으로 인해 도 1과 같이 필라패턴이 쓰러지고(11, collapse), 인접하는 필라패턴간 붙어버리는(12, leaning) 현상이 발생된다. 특히, 필라넥(13)을 형성하기 위한 비등방성 식각 공정에서 위와 같은 쓰러짐 및 붙는 현상이 다수 발생한다.In particular, in the case of a semiconductor device in which a source and a drain are arranged up and down in a pillar pattern to induce an up and down channel, the characteristics of the pillar pattern having a high aspect ratio are shown in FIG. 1. The pillar pattern collapses (11) and collapses between adjacent pillar patterns (12). In particular, in the anisotropic etching process for forming the pillar neck 13, the fall and sticking phenomenon as described above occurs a lot.

이는 반도체 소자의 특성을 저하시키는 요인으로 작용하는바, 필라넥(13) 형 성을 위한 비등방성 식각 공정에서 필라패턴의 쓰러짐 및 붙는 현상을 방지할 수 있는 기술이 필요하게 되었다.This acts as a factor to deteriorate the characteristics of the semiconductor device, a technique that can prevent the fall and sticking of the pillar pattern in the anisotropic etching process for forming the pillar neck (13).

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 필라넥 형성 중에, 필라패턴이 쓰러지고 붙어버리는 현상을 방지하는 필라패턴 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a pillar pattern which prevents a phenomenon that the pillar pattern falls and sticks during the formation of the pillar neck.

상기의 목적을 달성하기 위한 본 발명의 필라패턴 제조 방법은 부분 격자형태로 기판을 식각하여 복수의 트렌치를 형성하는 단계, 상기 트렌치에 지지막을 매립하는 단계, 상기 기판을 선택적으로 식각하여 상기 지지막과 접촉하는 복수의 필라헤드를 형성하는 단계, 상기 기판을 등방성 식각하여 복수의 필라넥을 형성하는 단계 및 상기 지지막을 제거하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a pillar pattern includes forming a plurality of trenches by etching a substrate in the form of a partial lattice, embedding a support layer in the trench, selectively etching the substrate, and supporting the support layer Forming a plurality of pillar heads in contact with the substrate, isotropically etching the substrate to form the plurality of pillar heads, and removing the support layer.

상술한 바와 같은 과제 해결 수단을 바탕으로 하는 본 발명은 지지막으로 필라넥 형성 중에 발생하는 필라패턴의 쓰러짐 문제를 해결한다.The present invention based on the problem solving means described above solves the problem of the fall of the pillar pattern generated during the formation of the pillar neck as a supporting film.

따라서, 필라패턴을 안정적으로 형성할 수 있으며, 나아가 반도체 소자의 신뢰성 및 안정서을 향상시킬 수 있다.Therefore, a pillar pattern can be formed stably, and also the reliability and stability of a semiconductor element can be improved.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위해 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 나타낸 공정단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 실리콘 기판(21) 상에 부분 격자형태(partial mesh profile)의 개방영역을 갖는 마스크패턴(22)을 형성한다. As shown in FIG. 2A, a mask pattern 22 having an open area of a partial mesh profile is formed on the silicon substrate 21.

부분 격자형태이란, 가로와 세로를 일정한 간격으로 배치한 격자구조에서, 가로와 세로가 만나는 부분이 제외된 형상을 의미한다. 따라서, 마스크패턴(22)은 가로와 세로가 만나는 부분 - 본 실시예에서는 필라헤드 예정지역(23)을 의미한다. - 을 덮고, 가로와 세로 방향으로 복수의 개방영역을 갖는다. 그리고, 마스크패턴(22)은 더블 노광(double exposure)으로 격자구조의 포토레지스트 패턴을 형성하고, 이후 필라헤드 예정지역(23)을 덮도록 추가적인 포토레지스트의 증착, 노광 및 현상 공정을 진행하여 형성된다.The partial lattice shape means a shape in which a part where the horizontal and vertical meets is excluded from the lattice structure in which the horizontal and the vertical are arranged at regular intervals. Therefore, the mask pattern 22 means a portion where the width and the vertical meet-in the present embodiment, the pillar head predetermined area 23. -Covers a plurality of open areas in the horizontal and vertical directions. The mask pattern 22 is formed by forming a photoresist pattern of a lattice structure by double exposure, and then further depositing, exposing and developing a photoresist to cover the predetermined region of the pillar head 23. do.

이어서, 마스크패턴(22)을 식각장벽으로 기판(21)을 식각하여 복수의 트렌치(24)를 형성한다. 여기서, 트렌치(24)의 깊이(D1)는 후속 필라헤드의 높이와 동일한 것이 바람직하다.Subsequently, the plurality of trenches 24 are formed by etching the substrate 21 using the mask pattern 22 as an etch barrier. Here, the depth D1 of the trench 24 is preferably equal to the height of the subsequent pillarhead.

이어서, 마스크패턴(22)을 제거한다.Next, the mask pattern 22 is removed.

도 2b에 도시된 바와 같이, 트렌치(24)에 지지막(25)을 매립한다.As shown in FIG. 2B, the support layer 25 is embedded in the trench 24.

지지막(25)은 산화막 또는 질화막으로 형성하며, 증착 및 평탄화 공정을 진 행하여 트렌치(24)에 매립한다.The support film 25 is formed of an oxide film or a nitride film, and is buried in the trench 24 by a deposition and planarization process.

도 2c에 도시된 바와 같이, 필라헤드 예정지역에 하드마스크막패턴(26)을 형성한다. As shown in FIG. 2C, a hard mask film pattern 26 is formed at a predetermined area of the pillar head.

이어서, 하드마스크막패턴(26)을 식각장벽으로 기판(21)을 식각하여 필라헤드(27)를 형성한다. 이때 지지막(25)의 측벽이 노출된다. 그리고, 필라헤드(27)는 비등방성 식각으로 형성하며, 지지막(25)과 동일한 높이를 갖는다. 이하, 필라헤드(27)가 형성된 기판(21)의 도면부호를 (21A)로 변경 표기한다.Subsequently, the pillar head 27 is formed by etching the substrate 21 using the hard mask layer pattern 26 as an etch barrier. At this time, the side wall of the support layer 25 is exposed. The pillar head 27 is formed by anisotropic etching and has the same height as the support layer 25. Hereinafter, the reference numerals of the substrates 21 on which the pillar heads 27 are formed are referred to as 21A.

도 2d에 도시된 바와 같이, 하드마스크막패턴(26) 및 필라헤드(27)의 측벽에 측벽보호막(28)을 형성한다.As shown in FIG. 2D, the sidewall protective layer 28 is formed on the sidewalls of the hard mask layer pattern 26 and the pillar head 27.

측벽보호막(28)은 후속 등방성 식각에서 필라헤드(27)의 측벽을 보호하기 위한 박막으로 작용한다. 그리고, 측벽보호막(28)은 지지막(25)과 동일한 박막으로 형성한다. 예를 들어, 지지막(25)을 산화막으로 형성할 경우, 측벽보호막(28)도 산화막으로 형성하며, 지지막(25)을 질화막으로 형성할 경우, 측벽보호막(28)도 질화막으로 형성한다.The sidewall protection layer 28 serves as a thin film for protecting the sidewall of the pillar head 27 in subsequent isotropic etching. The sidewall protective film 28 is formed of the same thin film as the support film 25. For example, when the support film 25 is formed of an oxide film, the sidewall protection film 28 is also formed of an oxide film, and when the support film 25 is formed of a nitride film, the sidewall protection film 28 is also formed of a nitride film.

도 2e에 도시된 바와 같이, 기판(21A)을 식각하여 필라넥(29)을 형성한다. 이하, 필라헤드(27)와 필라넥(29)을 통칭하여 필라패턴이라 표기한다.As shown in FIG. 2E, the substrate 21A is etched to form the pillar neck 29. Hereinafter, the pillar head 27 and the pillar neck 29 are collectively referred to as a pillar pattern.

필라넥(29)은 등방성 식각으로 형성하며, 직경이 필라헤드(27)보다 작다. 때문에 등방성 식각 도중에 필라패턴이 쓰러질 수 있다.The pillar neck 29 is formed by isotropic etching, and the diameter is smaller than the pillar head 27. Because of this, the pillar pattern may fall during the isotropic etching.

그러나, 본 발명의 실시예에서는 지지막(25)이 필라헤드(27)간을 지지하고 있어서, 필라넥(29) 형성 중 발생하는 필라패턴의 쓰러짐 현상을 방지하며, 나아가 붙음 현상도 방지한다.However, in the embodiment of the present invention, the support film 25 supports the pillar heads 27, thereby preventing the fall of the pillar pattern occurring during the formation of the pillar neck 29, and further preventing the sticking phenomenon.

도 3a는 도 2e와 같이 필라헤드(27)를 지지하고 있는 지지막(25)을 도시한 사시도로서, 이를 참조하면 필라넥(29) 형성을 위한 등방성 식각 이후에 지지막(25)이 필라헤드(27)간을 지지하고 있는 것을 확인할 수 있다. 따라서, 필라패턴의 쓰러짐은 방지된다.FIG. 3A is a perspective view of the support layer 25 supporting the pillar head 27 as shown in FIG. 2E. Referring to this, the support layer 25 is the pillar head after isotropic etching for forming the pillar neck 29. (27) We can confirm that we support liver. Therefore, the fall of the pillar pattern is prevented.

도 2f에 도시된 바와 같이, 지지막(25)과 측벽보호막(28)을 제거한다.As shown in FIG. 2F, the supporting film 25 and the sidewall protective film 28 are removed.

도 3b는 도 2f와 같이 지지막(25)과 측벽보호막(28)을 제거한 상태의 필라패턴을 도시한 사시도로서, 기판(21B) 상에 필라패턴이 안정적으로 형성된 것을 확인할 수 있으며, 이는 상술한 바와 같이 등방성 식각에서 지지막(25)이 필라패턴, 특히 필라헤드(27)를 지탱했기 때문이다.FIG. 3B is a perspective view illustrating the pillar pattern in a state in which the support layer 25 and the sidewall protection layer 28 are removed as shown in FIG. 2F, and the pillar pattern is stably formed on the substrate 21B. This is because the support layer 25 supported the pillar pattern, particularly the pillar head 27, in isotropic etching.

계속해서 도 2f에 도시된 바와 같이, 필라넥(29)을 감싸는 게이트절연막(30)과 게이트 전극(31)을 형성한다. 이때, 게이트 전극(31)은 폴리실리콘막 또는 금속막일 수 있다.Subsequently, as shown in FIG. 2F, the gate insulating film 30 and the gate electrode 31 surrounding the pillar neck 29 are formed. In this case, the gate electrode 31 may be a polysilicon film or a metal film.

이후, 필라패턴의 상부영역과 하부영역에 소스 및 드레인을 형성하여 채널이 필라패턴을 따라 상/하 방향으로 형성되는 반도체 소자를 제조한다.Subsequently, a source and a drain are formed in the upper region and the lower region of the pillar pattern to manufacture a semiconductor device in which channels are formed in the up and down directions along the pillar pattern.

전술한 바와 같은 본 발명의 실시예는, 필라넥(29)을 형성하기 위한 등방성 식각에서 필라패턴이 쓰러지는 문제점을 해결하고자, 필라헤드(27)를 지탱하는 지지막(25)을 형성후 상기 등방성 식각을 진행한다. 지지막(25)은 격자형태로 필라헤드(27)를 지탱하여 상술한 문제점을 해결한다.Embodiment of the present invention as described above, in order to solve the problem that the pillar pattern falls in the isotropic etching for forming the pillar neck 29, after forming the support layer 25 supporting the pillar head 27 isotropic Proceed with etching. The supporting film 25 supports the pillar head 27 in the form of a lattice to solve the above-mentioned problem.

이상에서 설명한 본 발명은 전술한 제1 및 제2실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described first and second embodiments and the accompanying drawings, and the present invention is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in the art.

도 1은 쓰러지고, 붙어버린 필라패턴을 촬영한 전자현미경 사진.1 is an electron microscope photograph of a fallen, stuck pillar pattern.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 나타낸 공정단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a는 도 2e와 같이 필라헤드를 지지하고 있는 지지막을 도시한 사시도.Figure 3a is a perspective view showing a support membrane for supporting the pillar head as shown in Figure 2e.

도 3b는 도 2f와 같이 지지막과 측벽보호막을 제거한 상태의 필라패턴을 도시한 사시도.3B is a perspective view illustrating a pillar pattern in a state in which a supporting film and a sidewall protective film are removed as in FIG. 2F.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21, 21A, 21B : 기판 22 : 마스크패턴21, 21A, 21B: substrate 22: mask pattern

23 : 필라헤드 예정영역 24 : 트렌치23: planned area of pillar head 24: trench

25 : 지지막 26 : 하드마스크막패턴25: support film 26: hard mask film pattern

27 : 필라헤드 28 : 측벽보호막27 pillar head 28 sidewall protective film

29 : 필라넥 30 : 게이트 절연막29: pillar neck 30: gate insulating film

31 : 게이트 전극31: gate electrode

Claims (5)

부분 격자형태로 기판을 식각하여 복수의 트렌치를 형성하는 단계;Etching the substrate in the form of a partial grating to form a plurality of trenches; 상기 트렌치에 지지막을 매립하는 단계;Embedding a support film in the trench; 상기 기판을 선택적으로 식각하여 상기 지지막과 접촉하는 복수의 필라헤드를 형성하는 단계;Selectively etching the substrate to form a plurality of pillar heads in contact with the support layer; 상기 기판을 등방성 식각하여 복수의 필라넥을 형성하는 단계; 및Isotropically etching the substrate to form a plurality of pillarnecks; And 상기 지지막을 제거하는 단계Removing the support membrane 를 포함하는 필라패턴 제조 방법.Pillar pattern manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 지지막과 상기 필라헤드는 동일 높이로 형성하는 필라패턴 제조 방법.The support layer and the pillar head is a pillar pattern manufacturing method of forming the same height. 제1항에 있어서,The method of claim 1, 상기 기판은 실리콘이며, 상기 지지막은 산화막으로 형성하거나, 질화막으로 형성하는 필라패턴 제조 방법.The substrate is silicon, and the supporting film is formed of an oxide film or a nitride pattern manufacturing method formed of a nitride film. 제1항에 있어서,The method of claim 1, 상기 필라넥을 형성하는 단계는, 상기 필라헤드의 측벽에 측벽보호막을 형성한 후에 진행하는 필라패턴 제조 방법.The forming of the pillar neck may be performed after forming a sidewall protective layer on the sidewall of the pillar head. 제1항에 있어서,The method of claim 1, 상기 필라헤드를 형성하는 단계는, 상기 지지막이 형성된 기판 상에 필라헤드를 정의하는 하드마스크막을 형성한 후, 이를 식각장벽으로 상기 기판을 비등방 식각하여 형성하며, 4개의 지지막과 접촉하는 필라헤드를 형성하는 것을 특징으로 하는 필라패턴 제조 방법.The pillar head may be formed by forming a hard mask layer defining a pillar head on the substrate on which the support layer is formed, and then anisotropically etching the substrate using an etch barrier to contact the four support layers. Pillar pattern manufacturing method characterized in that to form.
KR1020080030165A 2008-04-01 2008-04-01 Method for fabricating pillar pattern KR20090104971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080030165A KR20090104971A (en) 2008-04-01 2008-04-01 Method for fabricating pillar pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080030165A KR20090104971A (en) 2008-04-01 2008-04-01 Method for fabricating pillar pattern

Publications (1)

Publication Number Publication Date
KR20090104971A true KR20090104971A (en) 2009-10-07

Family

ID=41534736

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080030165A KR20090104971A (en) 2008-04-01 2008-04-01 Method for fabricating pillar pattern

Country Status (1)

Country Link
KR (1) KR20090104971A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11139197B2 (en) 2019-11-11 2021-10-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11139197B2 (en) 2019-11-11 2021-10-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

Similar Documents

Publication Publication Date Title
KR100971412B1 (en) Method for forming vertical channel transistor of semiconductor device
CN101952958B (en) Systems and devices including fin transistors and methods of using, making, and operating the same
US8101497B2 (en) Self-aligned trench formation
US9093534B2 (en) Dielectric filler fins for planar topography in gate level
CN102074481B (en) Method of fabricating vertical channel semiconductor device
JP2011216651A (en) Method of manufacturing semiconductor device
KR20090106017A (en) Method for fabricating semiconductor device
JP2007273950A (en) Semiconductor device with channel area increased and method for manufacturing same
TWI479608B (en) Semiconductor element and method for manufacturing semiconductor element
KR20090104971A (en) Method for fabricating pillar pattern
KR100849186B1 (en) Method for manufacturing semiconductor device using lsoi process
KR100720258B1 (en) Method for forming semiconductor device
KR101087918B1 (en) Semiconductor device and method for fabricating the same
KR100971422B1 (en) Method for fabricating semiconductor device
TWI490950B (en) Trench mos structure and method for forming the same
KR100981250B1 (en) Manufacturing method of gate electrode for vertical transistor
KR101172310B1 (en) Method for fabricating semiconductor device
KR100905463B1 (en) Semiconductor device and method of manufacturing semiconductor device
KR101019701B1 (en) Semiconductor device and method of manufacturing the same
KR100733190B1 (en) Method for manufacturing semiconductor device
KR100973718B1 (en) Method for forming pillar of semiconductor device and vertical channel transistor using the same
KR100879886B1 (en) Semiconductor device and method for manufacturing the same
KR101079287B1 (en) Transistor and method for fabricating the same
KR100838397B1 (en) Semiconductor device and method for manufacturing the same
KR20140123338A (en) Semiconductor Apparatus and Fabrication Method Thereof

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination