KR20090104364A - Level shifter - Google Patents

Abstract

PURPOSE: A level shifter is provided to allow facilitate driving by implanting stable and high speed operation while low power consumption. CONSTITUTION: A level shifter is connected with an input terminal of a gate electrode. A first transistor(N1) is connected between a ground power(GND) and an output terminal. A gate electrode is connected to a first node(A), and a second transistor(N2) is connected between an output terminal and a second electric power supply(VDDH). The gate electrode is connected to the input terminal. The input terminal is connected between the first node and the power(VDD), and a third transistor is connected with the first power.

Description

Level shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter, and more particularly, to a level shifter for a flat panel display device that can be implemented in a small area and that achieves high speed operation and low power consumption.

In general, the level shifter is a circuit that changes the magnitude of the signal voltage between two circuits when the circuits having different magnitudes of the signal voltage are connected. This is a case where the magnitude of the signal voltage is changed from a small voltage range to a large voltage range. Mainly used.

In particular, liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), organic light emitting displays (OLEDs), and the like. In the case of the driving circuit of a flat panel display device, a value corresponding to a digital signal is designed to have a low voltage for low power, but a material such as a liquid crystal (LC) or an organic lighting emitting diode (OLED) must be driven. Due to the characteristics of the panel, it is necessary to convert the digital signal to fit the driving voltage range of the panel. For this purpose, the level shifter is used.

A conventional cross coupled latch structure level shifter which is commonly used in a driving circuit of a flat panel display device is shown in FIG.

1 is a circuit diagram showing a conventional level shifter structure.

Referring to FIG. 1, the conventional level shifter is composed of two P-type transistors P1 and P2 and two N-type transistors N1 and N2.

An input signal Input is input to a gate of the N-type transistor N1, an inverting input signal Input_b is input to a gate of the N-type transistor N2, and a source of the N-type transistors N1 and N2 is input. Is connected to the ground voltage GND.

The drain of the N-type transistor N1 is connected to the drain of the P-type transistor P1, and the gate of the P-type transistor P1 is connected to the drain of the N-type transistor N2. The drain of the transistor N2 is connected to the drain of the P-type transistor P2, and the gate of the P-type transistor P2 is connected to the drain of the N-type transistor N1, and the P-type transistors P1 and P2 are connected. Source is connected to the second power supply voltage VDDH.

The level shift circuit of FIG. 1 configured as described above has a cross coupling latch structure.

In the conventional level shifter configured as described above, the input signal Input of FIG. 2A and the inverted input signal Input_b of FIG. 2B are respectively input to the gates of the N-type transistors N1 and N2. The output signal Output of the output terminal is level-converted as shown in FIG. 2 (c), and is connected to the connection node (ie, the gate terminal of the P-type transistor P2) of the N-type transistor N1 and the P-type transistor P1. As shown in (d) of FIG.

That is, level conversion is performed on the input signal Input having the operating range of GND to VDD to the output signal Output having the operating range of GND to VDDH.

Looking at the operation of the conventional cross-coupled latch structure level shifter in detail as follows.

When the input signal Input is changed from the ground voltage GND to the first power supply voltage VDD, the N-type transistor N1 is turned on to turn the inverted output signal Output_b to the ground voltage GND. To discharge). The inverted output signal Output_b terminal discharged to the ground voltage GND turns on the P-type transistor P2 to charge the output signal Output terminal to the second power supply voltage VDDH.

When the input signal In changes from the ground voltage GND to the first power supply voltage VDD, the N-type transistor N1 connected to the input terminal is turned on and the N-type transistor N2 connected to the inverting input terminal Input_b. ) Is turned off to discharge the inversion output signal output_b node to the positive second power supply voltage GND.

At this time, the P-type transistor P2 is weakly turned on by the inverted output signal Output_b, which does not quickly raise the GND voltage of the output terminal to VDDH. As a result, the P-type transistor P1 is weakly turned on. In addition to the N-type transistor N1 turned on by the input signal, the power consumption is increased by generating a through current from VDDH to GND.

Similarly, when the input signal Input is changed from the first power supply voltage VDD to the ground voltage GND, the N-type transistor N2 connected to the inverting input signal Input_b is turned on and connected to the input signal Input. The N-type transistor N1 is turned off to discharge the output signal node to the ground voltage GND.

At this time, the P-type transistor P1 is weakly turned on by the transitioned output signal Output, and thus the GND voltage of the inverted output terminal Output_b cannot be quickly increased to VDDH, and thus the P-type transistor P2 is weakly turned on. In addition to the N-type transistor N2 turned on by the inverting input signal Input_b, power consumption is increased by generating a through current from VDDH to GND.

In particular, such a large power consumption problem is due to the nature of the cross-coupled latch structure that the speed at which the change of the input signal (Input) and the inverted input signal (Input_b) affects the output signal (Output) and the inverted output signal (Output_b) It is associated with the structural disadvantage of being very slow and presents a big problem in terms of operating speed as well as power consumption.

In addition, assuming that the generated inverted input signal Input_b is used, the number of elements of the level shift circuit main body of the latch structure is very small, but the transistor connected to the input signal Input and the inverted input signal Input_b ( In the case of N1 and N2, the input signal and the inverted input signal Input_b are outputted in the form of converting the voltage of the input signal Input and the inverted input signal Input_b into current through mutual conductance characteristics. to (out). Therefore, the size of the transistors N1 and N2 is increased to increase the transfer capability.

However, in this case, there is a signal delay due to the increase of parasitic capacitor seen at the input signal stage, which increases the transition time of the input signal and increases the power consumption due to the longer signal transition period. The problem is antagonized.

In other words, the conventional cross-coupled latch structure level shifter operates regardless of the initial value of each node. However, the short-circuit current generated when the N-type transistor and the P-type transistor are turned on at the same time. Due to the large amount of through-current, the power consumption is large, and the area advantage due to the size of the transistors N1 and N2 is also increased to increase the capacity.

In particular, when designing a circuit using a TFT, an additional process such as an increase in a mask is required when manufacturing an N-type and a P-type transistor together in a manufacturing process. This is the main reason for the increase of the process cost and the decrease of the yield, and thus, a circuit using only a single transistor is required when implementing a circuit using a TFT.

The present invention provides a level shifter suitable for driving a flat panel display device by minimizing the mounting area while achieving stable and high-speed operation and low power using only P-type or N-type transistors, that is, transistors of the same type. There is a purpose.

According to an embodiment of the present invention, a level shifter includes: a first transistor (N1) having a gate electrode connected to an input terminal and connected between a ground power source (GND) and an output terminal (Output); A second transistor N2 connected to a gate electrode of the first node A and connected between an output terminal and a second power source VDDH; A gate electrode is connected to an input terminal and includes a third transistor N3 connected between the first node A and the first power source VDD or between the input terminal and the first power source VDD. It is characterized by.

In this case, a first capacitor C1 connected between the first node A and an output terminal may be further provided, and the first to third transistors are all implemented as an N-type transistor, and the first W (Width) / L (Length) value for the channel of the transistor (N1) is characterized in that it is designed to be larger than W (Width) / L (Length) for the channel of the second transistor (N2).

In addition, the level shifter according to another embodiment of the present invention, the gate electrode is connected to the input (Input), the first transistor (N1) connected between the first node (A) and the input (Input); A second transistor (N2) connected to a gate electrode of the first node (A) and connected between an output terminal (Output) and an inverting input terminal (Input_b); A first capacitor C1 connected to the first node A and an input terminal; A third transistor N3 connected to a gate electrode of the gate electrode and to a second node B and the input terminal; The gate electrode is connected to the second node (B), characterized in that it comprises a fourth transistor (N4) connected between the second power source (VDDH) and the output terminal (Output).

In addition, the level shifter according to another embodiment of the present invention, the gate electrode is connected to the inverting input terminal (Input_b), the first transistor (P1) connected between the first node (A) and the input terminal (Input); A second transistor (P2) connected to a gate electrode of the first node (A) and connected between an output terminal and an input terminal; A first capacitor C1 connected to the inverting input terminal Input_b and the second node B; A third transistor (P3) having a gate electrode connected to the second node (B) and connected to the second node (B) and the input terminal (Input); The gate electrode is connected to the second node (B), characterized in that it comprises a fourth transistor (P4) connected between the second power source (VDDH) and the output terminal (Output).

According to the present invention, by implementing a level shifter using only P-type or N-type transistors, that is, transistors of the same type, it is possible to achieve stable and high-speed operation and low power, and to minimize the mounting area. There is an advantage that the unit price is reduced and the yield is improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a level shifter according to a first embodiment of the present invention, and FIG. 4 is a driving timing diagram of the embodiment shown in FIG.

Referring to FIG. 3, the level shifter according to the first embodiment of the present invention includes a first transistor N1 having a gate electrode connected to an input terminal and connected between a ground power source GND and an output terminal. ; A second transistor N2 connected to a gate electrode of the first node A and connected between an output terminal and a second power source VDDH; A first capacitor C1 connected between the first node A and an output terminal; The gate electrode is connected to an input terminal, and includes a third transistor N3 connected between the first node A and the first power source VDD.

In this case, all of the first to third transistors are implemented as N-type transistors, and the second power source VDDH is provided as twice as large as the first power source VDD.

In addition, the value of W (Width) / L (Length) for the channel of the first transistor (N1) is designed to be larger than W (Width) / L (Length) for the channel of the second transistor (N2). It is done.

In addition, the third transistor N3 serves as a voltage controller for precisely controlling the voltage of the first node A so as to implement accurate operation switching of the first capacitor C1 and the second transistor N2. Characterized by performing.

3 and 4, the operation of the level shifter according to the first embodiment of the present invention configured as described above is as follows.

First, when the input signal (Input) is transitioned to the first power supply voltage (VDD), the threshold voltage (V _thN3 ) at the first power supply voltage (VDD) by the third transistor (N3) to the first node (A). As low as that is, VDD-V _thN3 is applied as the initial voltage.

First, when the first node A is set to the initial voltage, that is, when the input signal transitions from GND to VDD, both the first and second transistors N1 and N2 are turned on. In the present embodiment, as described above, in the present embodiment, a W (Width) / L (Length) value for the channel of the first transistor N1 is set to W (W) for the channel of the second transistor N2. Since it is designed to be larger than Width / L (Length), the first transistor N1 is strongly turned on than the second transistor N2 so that the output terminal is discharged to the ground voltage GND.

That is, as illustrated in FIG. 4, when the signal input to the input terminal transitions to the first power supply voltage VDD, the signal output to the output terminal transitions to the ground voltage GND.

Thereafter, when the input signal (Input) transitions from VDD to GND, the first transistor (N1) and the third transistor (N3) is turned off (Turn off), so the first node (A) is floating (Floating) It becomes a state.

However, the second transistor N2 is turned on by a bootstrapping effect according to the parasitic capacitor of the channel.

Accordingly, since the first node A is in a floating state, the gate electrode of the second transistor N2 in the first floating state is affected by the charging of the output terminal. The first node A in the floating state is charged to 3VDD-V _thN3 , and as a result, the output terminal is charged to a complete second power supply voltage VDDH by _turning on the second transistor N2. do.

In addition, since the first transistor N1 is turned off, the first transistor N1 prevents a through current from the second power supply voltage VDDH which is an output voltage to the ground voltage GND.

That is, as shown in FIG. 4, when the signal input to the input terminal transitions to GND, the signal output to the output terminal transitions to the second power supply voltage VDDH.

Through this structure, since the voltage value is correctly defined in the voltage range of 2VDD (VDDH), the first node A accurately turns on and turns off the second transistor N2. Intended and stable by charging the floating gate of the second transistor N2 to 3VDD-V _TH due to the fast operation and the bootstrapping effect of the channel parasitic capacitor Cgs of the second transistor N2. The power consumption also performs less operation.

That is, the conventional cross-coupled latch reduces the time transitions of the first and second transistors N1 and N2 by charging the output terminal through the second transistor N2 to the second power supply voltage VDDH completely. Through the input signal that defines the transition period of the signal generated in the level shift circuit of the structure, it is possible to greatly reduce the amount of through current caused by the short circuit due to the slowly changing output voltage at the time of signal transition. .

This has the advantage of showing a very stable operating characteristics, very small power consumption and peak current characteristics compared to the level shift circuit of the conventional cross-coupled latch structure.

That is, the present invention is relatively small in area by using the bootstrapping effect, it is possible to implement a high-speed operation, by reducing the amount of through current caused by the short circuit (Short Circuit) generated during the transition of the input signal It is possible to realize low power consumption.

In addition, by implementing a circuit with a single transistor, it is possible to realize a reduction in process cost and an improvement in process yield.

5A and 5B are circuit diagrams of the level shifter according to the second and third embodiments of the present invention.

5A and 5B have the same operation as the first embodiment described with reference to FIG. 3, and thus, a detailed description thereof will be omitted and only the differences in configuration will be briefly described.

First, the second embodiment shown in FIG. 5A includes: a first transistor N1 having a gate electrode connected to an input terminal and connected between a ground power source GND and an output terminal; A second transistor N2 connected to a gate electrode of the first node A and connected between an output terminal and a second power source VDDH; A first capacitor C1 connected between the first node A and an output terminal; The gate electrode and the drain electrode are connected to an input terminal, and the source electrode is composed of a third transistor N3 connected to the first node.

That is, there is a difference in that the drain electrode of the third transistor N3 is connected to an input terminal instead of the first power source VDD, and the rest of the configuration is the same as in the first embodiment.

In this case, when VDD power is applied to the input terminal, the same operation as in the first embodiment is performed, and even when GND is applied to the input terminal, the third transistor N3 is turned off, resulting in the first embodiment. It works the same as the example.

Next, the third embodiment shown in FIG. 5B includes: a first transistor N1 having a gate electrode connected to an input terminal and connected between a ground power source GND and an output terminal; A second transistor N2 connected to a gate electrode of the first node A and connected between an output terminal and a second power source VDDH; The gate electrode is connected to an input terminal, and includes a third transistor N3 connected between the first node A and the first power source VDD.

That is, there is a difference in that the first capacitor C1 is removed, and the rest of the configuration is the same as in the first embodiment. This replaces the parasitic capacitor of the second transistor instead of the first capacitor C1, and its operation is the same as that of the first embodiment described above.

6 is a circuit diagram of a level shifter according to a fourth embodiment of the present invention, and FIG. 7 is a driving timing diagram of the embodiment shown in FIG.

Unlike the first embodiment, the fourth embodiment additionally connects an inverted input terminal Input_b to which an inverted input signal is input in addition to an input terminal to which an input signal is input, and removes ground power GND. There is a difference.

Referring to FIG. 6, the fourth embodiment includes a first transistor N1 having a gate electrode connected to an input terminal and connected between a first node A and the input terminal; A second transistor (N2) connected to a gate electrode of the first node (A) and connected between an output terminal (Output) and an inverting input terminal (Input_b); A first capacitor C1 connected to the first node A and an input terminal; A third transistor N3 connected to a gate electrode of the gate electrode and to a second node B and the input terminal; A gate electrode is connected to the second node B and includes a fourth transistor N4 connected between the second power supply VDDH and the output terminal.

In this case, the first to fourth transistors are all implemented with an N-type transistor, and in particular, the first and third transistors are diode-connected as shown.

In addition, the value of W (Width) / L (Length) for the channel of the second transistor (N2) is designed to be larger than W (Width) / L (Length) for the channel of the fourth transistor (N4). As an example, the second power source VDDH is provided twice as large as the first power source VDD.

6 and 7, operation of the level shifter according to the fourth embodiment of the present invention configured as described above is as follows.

First, when the input signal transitions from GND to VDD and the inverted input signal Input_b transitions from VDD to GND, the first and third transistors N1 and N3 are turned on because they are diode-connected. Accordingly, VDD-V _thN1 and VDD-V _thN3 are applied to the first node A and the second node B, respectively.

In addition, as described above, in the present embodiment, the value of W (Width) / L (Length) for the channel of the second transistor N2 is W (Width) / L for the channel of the fourth transistor N4. Since the second transistor N2 is strongly turned on than the fourth transistor N4 and discharged to the ground voltage GND, which is an input signal Input_b in which the output terminal is inverted, since the second transistor N2 is designed to be larger than (Length). do.

That is, as illustrated in FIG. 7, when the signal input to the input terminal transitions to the first power supply voltage VDD, the signal output to the output terminal transitions to the ground voltage GND.

Thereafter, when the input signal Input transitions from VDD to GND and the inverted input signal Input_b transitions from GND to VDD, the first transistor N1 and the third transistor N3 are turned off. Turn off) so that the first node (A) and the second node (B) is in a floating state.

However, the first node (A) has a voltage value of VDD because one terminal of the first capacitor (C1) is inputted with GND, which is an input signal of one terminal of the first capacitor (C1) due to the bootstrapping effect according to the first capacitor (C1). The second transistor N2 is turned off by rapidly discharging from -V _thN1 to V _thN1 and inverting the input signal Input_b to VDD.

On the other hand, the gate electrode of the fourth transistor N4 which is in the first floating state due to the floating state of the second node B is affected by the charging of the output terminal. The second node B in the floating state is charged to 3VDD-V _thN3 , and as a result, the output terminal is charged to a complete second power supply voltage VDDH by _turning on the second transistor N2. do.

At this time, since the second transistor N2 is turned off, the second transistor N2 prevents a through current from the second power supply voltage VDDH which is an output voltage to the ground voltage GND.

That is, as shown in FIG. 7, when the signal input to the input terminal transitions to GND, the signal output to the output terminal transitions to the second power supply voltage VDDH.

FIG. 8 is a circuit diagram of a level shifter according to a fifth embodiment of the present invention, and FIG. 9 is a driving timing diagram of the embodiment shown in FIG.

Unlike the first embodiment, the fifth embodiment further includes an inverting input terminal Input_b to which an inverted input signal is input, in addition to an input terminal to which an input signal is input, and removes ground power GND. There is a difference in that the transistor is formed in a P type.

Referring to FIG. 8, the fifth embodiment includes a first transistor P1 having a gate electrode connected to an inverting input terminal Input_b and connected between a first node A and an input terminal; A second transistor (P2) connected to a gate electrode of the first node (A) and connected between an output terminal and an input terminal; A first capacitor C1 connected to the inverting input terminal Input_b and the second node B; A third transistor (P3) having a gate electrode connected to the second node (B) and connected to the second node (B) and the input terminal (Input); A gate electrode is connected to the second node B, and includes a fourth transistor P4 connected between the second power source VDDH and the output terminal.

At this time, all of the first to fourth transistors are implemented as P-type transistors, and in particular, the third transistor P3 is diode-connected as shown.

In addition, the value of W (Width) / L (Length) for the channel of the fourth transistor (P4) is designed to be larger than W (Width) / L (Length) for the channel of the second transistor (P4). As an example, the second power source VDDH is provided twice as large as the first power source VDD.

8 and 9, the operation of the level shifter according to the fifth embodiment of the present invention configured as described above is as follows.

First, when the input signal transitions from GND to VDD and the inverted input signal Input_b transitions from VDD to GND, the first transistor P1 is turned on so that VDD is applied to the first node A. In addition, since the third transistor P3 is diode-connected, the third transistor P3 is turned on, and VDD-V _thP3 is applied to the second node B.

In addition, as described above, in the present embodiment, the value of W (Width) / L (Length) for the channel of the fourth transistor P4 is W (Width) / L for the channel of the second transistor P2. Since the fourth transistor P4 is strongly turned on than the second transistor P2, the output terminal is charged to the first power supply voltage VDDH.

That is, as shown in FIG. 9, when the signal inputted to the input terminal transitions to the first power supply voltage VDD, the signal outputted to the output terminal transitions to the second power supply voltage VDDH.

Thereafter, when the input signal Input transitions from VDD to GND and the inverted input signal Input_b transitions from GND to VDD, the first transistor P1 and the third transistor P3 are turned off. Turn off) so that the first node (A) is in a floating state.

However, the second node B is inputted with VDD, an input signal in which one terminal of the first capacitor C1 is inverted by a bootstrapping effect according to the first capacitor C1, thereby providing a voltage value. The 2VDD-V _thP3 is quickly charged, so that the fourth transistor N4 is turned off.

On the other hand, as the first node A is in a floating state, the gate electrode of the second transistor P2 in the first floating state is affected by the charging of the output terminal. The first node A in the floating state is discharged to -VDD. As a result, the output terminal discharges to the input voltage GND by turning on the second transistor P2.

That is, as shown in FIG. 9, when the signal input to the input transitions to GND, the signal output to the output transitions to GND.

10 is a circuit diagram of a level shifter according to a sixth embodiment of the present invention.

Referring to FIG. 10, the sixth embodiment includes a first transistor N1 having a gate electrode connected to an input terminal and connected between a first node A and the input terminal; A second transistor N2 connected to a first electrode A of the gate electrode and connected between an output terminal and an input terminal; A first capacitor C1 connected to the first node A and an inverting input terminal Input_b; A third transistor N3 connected to a gate electrode connected to the inverting input terminal Input_b and connected to a second node B and the inverting input terminal Input_b; A gate electrode is connected to the second node B and includes a fourth transistor N4 connected between the second power supply VDDH and the output terminal.

In this case, the first to fourth transistors are all implemented with an N-type transistor, and in particular, the first and third transistors are diode-connected as shown.

However, this is the same as the configuration of the fifth embodiment of the present invention shown in FIG. 9, except that the first to fourth transistors are changed from a P-type transistor to an N-type transistor, and the operation principle thereof is the same. The detailed operation will be omitted.

On the other hand, the present invention is not limited to the above-described specific embodiments, it can be carried out by various modifications and modifications within the scope not departing from the gist of the present invention, the claims to which such modifications and modifications are attached If it is included in the obvious that it belongs to the present invention.

1 is a circuit diagram showing a conventional level shifter structure.

2 is a drive timing diagram of a conventional level shifter shown in FIG.

3 is a circuit diagram of a level shifter according to a first embodiment of the present invention.

4 is a drive timing diagram of the embodiment shown in FIG.

5A and 5B are circuit diagrams of a level shifter according to the second and third embodiments of the present invention.

6 is a circuit diagram of a level shifter according to a fourth embodiment of the present invention.

7 is a drive timing diagram of the embodiment shown in FIG. 6;

8 is a circuit diagram of a level shifter according to a fifth embodiment of the present invention.

9 is a drive timing diagram of the embodiment shown in FIG. 8;

10 is a circuit diagram of a level shifter according to a sixth embodiment of the present invention.

Claims (10)

A first transistor N1 connected to a gate electrode at an input terminal and connected between a ground power source GND and an output terminal; A second transistor N2 connected to a gate electrode of the first node A and connected between an output terminal and a second power source VDDH; A gate electrode is connected to an input terminal and includes a third transistor N3 connected between the first node A and the first power source VDD or between the input terminal and the first power source VDD. Level shifter. The method of claim 1, And a first capacitor (C1) further connected between the first node (A) and an output terminal (Output). The method of claim 1, And the first to third transistors are all implemented with an N-type transistor. The method of claim 1,  W (Width) / L (Length) value for the channel of the first transistor (N1) is designed to be larger than W (Width) / L (Length) for the channel of the second transistor (N2) Level shifter. A first transistor N1 connected to a gate electrode of the gate electrode and connected between a first node A and the input terminal; A second transistor (N2) connected to a gate electrode of the first node (A) and connected between an output terminal (Output) and an inverting input terminal (Input_b); A first capacitor C1 connected to the first node A and an input terminal; A third transistor N3 connected to a gate electrode of the gate electrode and to a second node B and the input terminal; A level shifter, wherein a gate electrode is connected to the second node (B) and includes a fourth transistor (N4) connected between a second power supply (VDDH) and an output terminal (Output). The method of claim 5, And the first to fourth transistors are all implemented with an N-type transistor. The method of claim 5,  W (Width) / L (Length) value for the channel of the second transistor (N2) is designed to be larger than W (Width) / L (Length) for the channel of the fourth transistor (N4) Level shifter. A first transistor P1 coupled to the inverting input terminal Input_b and connected between the first node A and an input terminal; A second transistor (P2) connected to a gate electrode of the first node (A) and connected between an output terminal and an input terminal; A first capacitor C1 connected to the inverting input terminal Input_b and the second node B; A third transistor (P3) having a gate electrode connected to the second node (B) and connected to the second node (B) and the input terminal (Input); And a fourth transistor (P4) connected to the second node (B) and connected between a second power supply (VDDH) and an output terminal (Output). The method of claim 8, And the first to fourth transistors are all implemented with a P-type transistor. The method of claim 8, W (Width) / L (Length) value for the channel of the fourth transistor (P4) is designed to be larger than W (Width) / L (Length) for the channel of the second transistor (P4) Level shifter.

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