KR20090103805A - Plasma processing apparatus and plasma etching method - Google Patents

Abstract

PURPOSE: A plasma processing apparatus and plasma etching method are provided to improve the uniformity of the etching property in the etching processes. CONSTITUTION: The plasma processing apparatus includes the treatment basin(10), the bottom electrode, the top of inside electrode(60), the outer side upper electrode(62), the processing gas supply part(76), the first radio frequency feeding unit, the first direct current feeding unit, and the second direct current feeding unit. The bottom electrode mounts the processed substrate within the process chamber. The inner side upper electrode is arranged to the front side of the bottom electrode within the process chamber. The processing gas supply part supplies the process gas to the process space of the gap of the inner side and outer side upper electrode and bottom electrode. The first direct current feeding unit applies the first direct current voltage to the top of inside electrode. The second direct current feeding unit applies the second direct current voltages of a variable to the outer side upper electrode.

Description

Plasma processing apparatus and plasma etching method {PLASMA PROCESSING APPARATUS AND PLASMA ETCHING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for performing a plasma treatment on a substrate to be treated, and more particularly, to a capacitively coupled plasma processing apparatus and a plasma etching method using the same.

Plasma is often used in the process of etching, deposition, oxidation, sputtering, etc. in a semiconductor device or a manufacturing process of a flat panel display (FPD) to perform a good reaction at a relatively low temperature with a processing gas. . Background Art Conventionally, in the single-piece plasma processing apparatus, a capacitively coupled plasma processing apparatus capable of easily realizing large-diameter plasma has become a mainstream.

In general, a capacitively coupled plasma processing apparatus arranges an upper electrode and a lower electrode in parallel in a processing chamber configured as a vacuum chamber, and processes a substrate (semiconductor wafer, glass substrate, etc.) on the lower electrode. ), And a high frequency is applied between both electrodes. Then, electrons accelerated by the high frequency electric field, secondary electrons emitted from the electrode, or heated electrons between the electrodes cause ionization collision with molecules of the processing gas, and plasma of the processing gas is generated. The desired microprocessing, for example, etching is performed on the surface of the substrate by radicals or ions in the plasma.

In the plasma etching apparatus, a relatively high frequency (typically 40 MHz or more), which is preferable for plasma generation (high frequency discharge), and a relatively low frequency (typically 13.56 MHz or less), which is preferable for the introduction (bias) of ions to a substrate. The lower 2 frequency application system which simultaneously applies the 2nd high frequency of to the lower electrode is used widely.

By the way, in the capacitively coupled plasma processing apparatus which handles large diameter plasma, it is difficult to make a plasma process uniform at each position on a board | substrate, and solving this from a viewpoint of product yield is a big subject. In general, in the plasma processing apparatus, the plasma density distribution in the chamber tends to vary according to process parameters (pressure, RF power, gas species, etc.), so that the process has good uniformity under any process conditions. Even if the results are obtained, the uniformity often deteriorates when the process conditions are changed in accordance with the requirements of the processing characteristics, and it is necessary to realize a chamber structure that can guarantee the uniformity of the process at all times over a wide range of process conditions. It is difficult. In particular, in the case where the multi-layered film on the substrate is etched continuously in a plurality of steps, the process parameters and etching masks used in each step or each of the processed films are different. It is difficult to obtain this good uniformity.

In this regard, since the method of controlling the impedance of an electrode known in the electric circuit (patent document 1) in order to vary the plasma density distribution is not an active control method, it is flexible to various kinds of processes or changes of process conditions. It was difficult to cope with, and was insufficient for the level of uniformity required in today's plasma processes.

(Patent Document 1) Japanese Patent Laid-Open No. 2004-96066

The present invention has been made in view of the problems of the prior art, and an object thereof is to provide a capacitively coupled plasma processing apparatus which can easily and freely control the distribution characteristics of electron density or process characteristics on a substrate to be processed. Moreover, an object of this invention is to provide the plasma etching method which improves the uniformity of an etching characteristic in various etching processes.

In order to achieve the above object, the plasma processing apparatus of the present invention is disposed in front of the lower electrode in the processing container, the lower electrode for mounting the substrate to be processed in the processing container, the vacuum dischargeable; Desired processing for an inner upper electrode, an outer upper electrode which is insulated from the inner upper electrode in the processing vessel, and arranged in a ring shape outside the radially outer side, and a processing space between the inner and outer upper electrodes and the lower electrode; A processing gas supply unit for supplying a gas, a first high frequency power supply unit for applying a first high frequency wave for generating a plasma of the processing gas by high frequency discharge to the lower electrode or the inner and outer upper electrodes, and the inner upper electrode A first DC power supply for applying a variable first DC voltage to the first DC power supply; And a second all-level direct current for applying a side of the second DC voltage.

In the above configuration, the substrate mounted on the lower electrode is independently varied by varying the first DC voltage applied from the first DC feeder to the inner upper electrode and the second DC voltage applied from the second DC feeder to the outer upper electrode independently. It is possible to control the electron density distribution or the process characteristics in the phase, and the uniformity of the process can be improved by appropriate combination of both DC voltages.

As one preferable aspect of the present invention, the first and second DC power supply units may have independent DC power supplies, respectively. As another preferable aspect, the variable for voltage drop in which a 1st and 2nd DC feeder has a common (single) DC power supply, and a 1st DC feeder is connected between the output terminal of the said DC power supply, and an inner upper electrode. It is good also as a structure which has a resistor.

Moreover, in order to strengthen the effect of a 2nd DC voltage, the structure which further protrudes and arrange | positions the outer upper electrode to the lower electrode side rather than an inner upper electrode is also preferable.

The present invention is applicable to any plasma processing apparatus, but is particularly preferably applicable to a plasma processing apparatus of a type having a second high frequency feeding portion for applying a second high frequency wave for introducing ions in the plasma to the lower electrode. .

The plasma etching method according to the first aspect of the present invention is a plasma etching method for etching the insulating film containing Si using the plasma processing apparatus of the present invention, wherein both the first and second DC voltages are larger than 0V. Instead, the absolute value of the second DC voltage is equal to or greater than the absolute value of the first DC voltage.

In one more specific aspect of the present invention, in an etching process for forming a contact hole in a SiO ₂ film, the first DC voltage is selected from -600V to -150V, and the second DC voltage is from -1000V to-. It is selected at 150V. The frequency of the second high frequency may be selected from 2 MHz to 3.2 MHz. By varying the second DC voltage, it is possible to effectively change the etching rate of the substrate edge portion with little or no change in the etching rate of the center portion of the substrate, thereby improving the uniformity of the etching rate. .

In another one aspect, in the etching process of forming a via hole in the SiOC film, the first DC voltage is selected from -900V to -300V, and the second DC voltage is selected from -1500V to -300V. . The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. As the processing gas, an etching gas containing a fluorocarbon gas, an inert gas, an O ₂ gas or an N ₂ gas can be preferably used. In addition, by varying the second DC voltage, it is possible to effectively change the etching rate of the substrate edge portion with little or no change in the etching rate of the center portion of the substrate, thereby improving the uniformity of the etching rate.

In another embodiment, the first DC voltage is -300 V to 0 V in an etching process for transferring a mask pattern to a SiN film of an intermediate layer or a lower layer in a multilayer resist method. The second DC voltage is selected from -900V to -300V. The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. In this case, by varying the second DC voltage, not only can the etching rate of the substrate center be changed, but also the etching rate of the substrate edge portion can be effectively changed, and the CD shift of the pattern is also lower than that of the substrate center. Since it can be effectively varied at the substrate edge portion, CD uniformity can be improved.

The plasma etching method according to the second aspect of the present invention is a plasma etching method for etching an organic film by using the plasma processing apparatus of the present invention, wherein both the first and second DC voltages are not greater than 0V, and the second DC voltage The absolute value of is greater than the absolute value of the first DC voltage. Preferably, the first DC voltage is selected from -100V to 0V and the second DC voltage is selected from -900V to 0V. The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. As the processing gas, an etching gas containing an O ₂ gas or an N ₂ gas can be preferably used. In this case, by varying the second DC voltage, the etching rate of the center portion of the substrate can be effectively changed with little or no change in the etching rate of the substrate edge portion, thereby improving the uniformity of the etching rate.

According to the plasma processing apparatus of the present invention, the distribution characteristics of the electron density or the process characteristics on the substrate to be processed can be easily and freely controlled by the above-described configuration and operation.

Moreover, according to the plasma etching method of this invention, the uniformity of an etching characteristic can be improved in various etching processes by the above structures and functions.

BRIEF DESCRIPTION OF THE DRAWINGS The longitudinal cross-sectional view which shows the structure of the capacitively coupled plasma etching apparatus in one Embodiment of this invention.

Figure 2 is a diagram showing the radial distribution characteristics of the etching rate (E / R) obtained in the experiment of the front etching SiO ₂ film according to the embodiment.

3 is a diagram showing an in-plane distribution characteristic of an E / R change rate when the value of the second DC voltage applied to the outer upper electrode in the etching of FIG. 2 is changed.

4 is a diagram showing in-plane distribution characteristics of an etching rate (E / R) obtained in an experiment of HARC etching in which contact holes are formed in a SiO ₂ film according to an embodiment.

Fig. 5 is a diagram showing the in-plane distribution characteristic of the E / R change rate when the value of the second DC voltage applied to the outer upper electrode in the etching of Fig. 4 is changed.

FIG. 6 is a diagram showing a configuration in which a step is provided in an electrode gap direction between an inner upper electrode and an outer upper electrode in the plasma etching apparatus of the embodiment; FIG.

FIG. 7 is a diagram showing an in-plane distribution characteristic of an etching rate (E / R) obtained in an experiment of HARC etching using the electrode structure of FIG. 6.

The figure which shows in-plane distribution characteristic of the electron density Ne obtained by the experiment of HARC etching in embodiment.

9 is a diagram showing an in-plane distribution characteristic of Ne change rate when the value of the second DC voltage applied to the outer upper electrode is changed in the etching of FIG.

10A to 10D are views showing the procedure of the multilayer resist method in the embodiment.

FIG. 11 is a diagram showing an in-plane distribution characteristic of an etching rate (E / R) obtained by etching of an organic film included in the multilayer resist of FIGS. 10A to 10D.

FIG. 12 is a diagram showing an in-plane distribution characteristic of an E / R change rate when the value of the second DC voltage applied to the outer upper electrode in the etching of FIG. 8 is changed. FIG.

FIG. 13 is a cross-sectional view (SEM photograph) showing the shape of a pattern obtained by etching of an antireflection film and an organic film included in the multilayer resist of FIGS. 10A to 10D.

FIG. 14 is a diagram showing in-plane distribution characteristics of an etching rate (E / R) obtained by etching of a SiN film included in the multilayer resist of FIGS. 10A to 10D.

FIG. 15 is a diagram showing an in-plane distribution characteristic of a CD shift when the value of the second DC voltage applied to the outer upper electrode in the etching of FIG. 8 is changed. FIG.

16 is a longitudinal cross-sectional view showing a configuration of a modification of the capacitively coupled plasma etching apparatus according to the embodiment.

Explanation of the sign

10: chamber (processing container)

12: susceptor (lower electrode)

26: exhaust system

30: the first high frequency power supply

32: second high frequency power supply

60: inner upper electrode (shower head)

62: outer top electrode

76: process gas supply

80, 82, 110: Variable DC Power

118: variable resistor

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described with reference to an accompanying drawing.

In FIG. 1, the structure of the plasma etching apparatus by one Embodiment of this invention is shown. This plasma processing apparatus is constituted as a capacitively coupled plasma etching apparatus of a cathode coupling that adopts a lower two-frequency application method, and is made of, for example, a metallic cylindrical chamber made of aluminum or stainless steel or the like (processing) Container) 10. Chamber 10 is securely grounded.

In the chamber 10, a disk-shaped susceptor 12 on which a semiconductor wafer W is mounted, for example, as a substrate to be processed is arranged horizontally as a lower electrode. The susceptor 12 is made of aluminum, for example, and is supported by an insulating cylindrical support 14 extending vertically upward from the bottom of the chamber 10. An annular shape is formed between the conductive cylindrical support portion (inner wall portion) 16 extending vertically upward from the bottom of the chamber 10 along the outer circumference of the cylindrical support portion 14 and the side wall of the chamber 10. An exhaust path 18 is formed, and a ring-shaped baffle plate (exhaust ring) 20 is attached to the inlet of the exhaust path 18, and the bottom of the exhaust path 18 is attached. An exhaust port 22 is provided. An exhaust device 26 is connected to the exhaust port 22 via an exhaust pipe 24. The exhaust device 26 has a vacuum pump such as a turbo molecular pump, and can reduce the processing space in the chamber 10 to a desired degree of vacuum. A gate valve 28 is attached to the sidewall of the chamber 10 to open and close the carrying in and out of the semiconductor wafer W. As shown in FIG.

First and second high frequency power supplies 30 and 32 are electrically connected to the susceptor 12 via a matching unit 34 and a feed bar 36. Here, the 1st high frequency power supply 30 outputs the 1st high frequency of the frequency (usually 40 MHz or more) which mainly contributes to generation | occurrence | production of a plasma. The second high frequency power supply 32 mainly outputs a second high frequency of a frequency (usually 13.56 MHz or less) that contributes to the introduction of ions into the semiconductor wafer W on the susceptor 12. The matching unit 34 includes a first matcher for matching between an impedance on the first high frequency power supply 30 side and an impedance on a load (mainly electrode, plasma, chamber) side, and a second high frequency power supply 32. A second matcher for matching between the impedance on the side and the impedance on the load side is accommodated.

The semiconductor wafer W to be processed is mounted on the susceptor 12, and a focus ring (correction ring) 38 is provided to surround the semiconductor wafer W. As shown in FIG. The focus ring 38 is made of a conductive material having a low adverse effect on the process, for example, Si, SiC, etc., and is attached to the upper surface of the susceptor 12 so as to be detachable and detachable.

The upper surface of the susceptor 12 is provided with an electrostatic chuck 40 for wafer adsorption. The electrostatic chuck 40 has a sheet-shaped or mesh-shaped conductor interposed therebetween in a film-like or plate-like dielectric. A DC power supply 42 disposed outside the chamber 10 is electrically connected to the conductor via an on / off switching switch 44 and a feed line 46. By the DC voltage applied from the DC power supply 42, the semiconductor wafer W can be adsorbed and held on the electrostatic chuck 40 with a Coulomb force.

Inside the susceptor 12, for example, an annular coolant chamber 48 extending in the circumferential direction is provided. The refrigerant chamber 48 is circulated and supplied with a coolant, for example, a predetermined temperature, from a chiller unit (not shown) through the pipes 50 and 52. The temperature of the semiconductor wafer W on the electrostatic chuck 40 can be controlled by the temperature of the refrigerant. In addition, in order to further increase the accuracy of the wafer temperature, the heat transfer gas, for example, the He gas from the heat transfer gas supply unit (not shown) passes through the gas supply pipe 54 and the gas passage 56 inside the susceptor 12. It is supplied between the electrostatic chuck 40 and the semiconductor wafer W.

On the ceiling of the chamber 10, the disk-shaped inner (or center) upper electrode 60 and the ring-shaped outer (or peripheral) upper electrode 62 face concentrically in parallel with the susceptor 12. It is prepared. The inner upper electrode 60 preferably has the same diameter (diameter) as the semiconductor wafer W, and the outer upper electrode 62 preferably has the same diameter as the focus ring (correction ring) 38. It has (inner diameter and outer diameter). However, the inner upper electrode 60 and the outer upper electrode 62 are electrically insulated from each other (more precisely, DC). In the illustrated structural example, a ring-shaped insulator 63 made of, for example, ceramic is inserted between the two electrodes 60 and 62.

The inner upper electrode 60 has an electrode plate 64 directly facing the susceptor 12 and an electrode support for supporting the electrode plate 64 so that the electrode plate 64 can be mounted and detached from the rear thereof. Has 66. The material of the electrode plate 64 is preferably a silicon-containing conductive material such as Si or SiC capable of less adversely affecting the process and maintaining good DC application characteristics. The electrode support 66 may be made of alumite treated aluminum.

The outer upper electrode 62 also has an electrode plate 68 facing the susceptor 12 and an electrode support 70 for supporting the electrode plate 68 so as to be detachable from the rear thereof. have. These electrode plates 68 and the electrode support 70 may also be made of the same material as the electrode plate 64 and the electrode support 66 of the inner upper electrode 60, respectively.

In this embodiment, in order to supply the processing gas to the processing space PS set between the upper electrodes 60 and 62 and the susceptor 12, a shower head serving as the inner upper electrode 60 is provided. I am preparing. More specifically, a gas diffusion chamber 72 is provided inside the electrode support 66, and a plurality of gas discharge holes 74 penetrating from the gas diffusion chamber 72 toward the susceptor 12 side are provided in the electrode support ( 66 and the electrode plate 64. The gas supply pipe 78 from the processing gas supply part 76 is connected to the gas introduction port 72a provided in the upper part of the gas diffusion chamber 72. In addition, not only the inner upper electrode 60 but also the outer upper electrode 62 may be provided to serve as a shower head.

Outside the chamber 10, for example, two variable DC power supplies 80 and 82 capable of outputting variable DC voltages V _C and V _E in the range of -2000 to +1000 V, respectively, are disposed. In the plasma etching method of the present invention, as will be described later, both DC voltages V _C and V _E are usually used at a value of 0 V or less, that is, a negative polarity (−) value, and each absolute value | When V _C | and | V _E | are set, the relationship of | V _C | ≤ | V _E | is maintained and used together.

The output terminal of one variable DC power supply 80 is electrically connected to the inner upper electrode 60 via an on / off switching switch 84 and a filter circuit 86. The filter circuit 86 passes through the first DC voltage V _C output from the variable DC power supply 80 to the inner upper electrode 60, while the processing space PS and the inner upper electrode from the susceptor 12. It is comprised so that the high frequency which entered the DC power supply line 88 through 60 may flow to a ground line, and not to the variable DC power supply 80 side.

The output terminal of the other variable DC power supply 82 is electrically connected to the outer upper electrode 62 via the on / off switching switch 90 and the filter circuit 92. The filter circuit 92 passes through the second DC voltage V _E output from the variable DC power supply 82 to the outer upper electrode 62, while the processing space PS and the outer upper electrode from the susceptor 12. It is comprised so that the high frequency which entered the DC power supply line 94 through 62 may flow to a ground line, and not to the variable DC power supply 82 side.

In addition, as a suitable location facing the processing space PS in the chamber 10, for example, a ring shape made of, for example, a conductive member such as Si or SiC on the radially outer side of the outer upper electrode 62. A DC ground component (direct current ground electrode) 96 is attached. The DC ground component 96 is attached to a ring-shaped insulator 98 made of ceramic, for example, and is also connected to the ceiling wall of the chamber 10 and is always grounded through the chamber 10. When the DC voltages V _C and V _E are applied from the variable DC power supplies 80 and 82 to the upper electrodes 60 and 62 during the plasma treatment, the upper electrodes 60 and 62 and the DC ground component 96 are passed through the plasma. The direct current electron current flows in between.

Each part in this plasma etching apparatus, for example, the exhaust device 26, the high frequency power supplies 30 and 32, the on / off switching switch 44 for the electrostatic chuck, the processing gas supply unit 76, and the on / off for DC application Individual operations such as changeover switches 84 and 90, chiller units (not shown), electrothermal gas supply units (not shown), and operations of the entire apparatus (sequences) are, for example, performed by a microcomputer. Controlled by a control unit (not shown).

In this plasma etching apparatus, in order to perform etching, first, the semiconductor wafer W to be processed is brought into the chamber 10 with the gate valve 28 opened, and mounted on the electrostatic chuck 40. Then, the etching gas (generally mixed gas) is introduced into the chamber 10 from the processing gas supply unit 76 at a predetermined flow rate, and the pressure in the chamber 10 is adjusted to the set value by the exhaust device 26. Further, by turning on the first and second high frequency power supplies 30 and 32, the first high frequency (40 MHz or more) and the second high frequency (13.56 MHz or less) are output at predetermined powers, respectively, The susceptor 12 is applied to the susceptor 12 via the matching unit 34 and the feeding rod 36. In addition, the switch 44 is turned on, and the electrothermal gas (He gas) is confined to the contact interface between the electrostatic chuck 40 and the semiconductor wafer W by the electrostatic attraction force. The etching gas discharged from the shower head 60 is made into a plasma by the high frequency discharge between both electrodes 12 and 60 and 62, and the surface of the semiconductor wafer W is generated by radicals and ions generated by this plasma. The processed film of is etched in a desired pattern.

This capacitively coupled plasma etching apparatus applies the first high frequency of a relatively high frequency suitable for plasma generation of 40 MHz or more to the susceptor 12, thereby densifying the plasma in a preferable dissociation state and further reducing the pressure. High density plasma can be formed even under the conditions. At the same time, a highly selective anisotropic etching is performed on the processing film of the semiconductor wafer W by applying the second high frequency wave of a relatively low frequency suitable for ion implantation below 13.56 MHz to the susceptor 12. can do. First of all, although the first high frequency wave for plasma generation is necessarily used in any plasma process, the second high frequency wave for ion introduction may not be used depending on the process.

The main feature of this capacitively coupled plasma etching apparatus is that the upper electrode is divided into the inner upper electrode 60 and the outer upper electrode 62 in the radial direction as described above, and the two variable DC power supplies 80 and 82 are used. The first and second DC voltages V _C and V _E are simultaneously applied to both upper electrodes 60 and 62. By the two direct-current voltage V _C, appropriately selecting the combination of the V _E, it is possible to improve the uniformity of the plasma etching process, or characteristic in a variety of applications (application) of the. Hereinafter, the Example of the etching method using this plasma etching apparatus is described.

As an etching process of an insulating film containing Si, a high aspect ratio contact (HARC) for forming thin and deep contact holes in an SiO ₂ film or a SiOC film, or a BEOL (Back for forming a relatively shallow via hole) End Of Line applications are well known.

FIG using, embodiment of a plasma etching apparatus in Figure 2, shows the characteristic radial distribution of the blanket (blanket) etching rate (E / R) obtained in the front (全面) etching a test SiO ₂ film. Main etching conditions are as follows.

Wafer diameter: 300 mm

Etching gas: C ₄ F ₈ / Ar / O ₂ = 45/200 / 30sccm

Pressure in chamber: 15 mTorr

High frequency power: 40MHz / 2MHz = 1000 / 3000W

Temperature: Top electrode / chamber sidewall / bottom electrode = 60/60/20 ° C.

DC voltage: V _C = -300V, V _E = -300V, -900V (2 types)

Further, FIG. 3, the second indicates the E / R rate of change in angular position on the wafer when eoteul change the direct current voltage V _E from -300V to -900V.

As shown in FIG. 2, in the case of V _C / V _E = -300 V / -300 V, the E / R on the wafer is larger than the center of the edge, but V _C / V _E = -300 V / -900 V. This reduces the difference between the center and the edge and greatly improves in-plane uniformity. What is important here is that as shown in FIG. 3, E / R of the center part hardly changes, but E / R of the edge part changes remarkably. Therefore, the first DC voltage V _C applied to the inner upper electrode 60 is selected to an appropriate value (preferably -600V to -150V), and the second DC voltage V _E applied to the outer upper electrode 62 is selected. By varying within an appropriate range (preferably -1500 V to -300 V), it is possible to freely control the in-plane distribution characteristic of the E / R, and the in-plane uniformity can also be easily improved.

Since the etching of BEOL is also the same process as the etching of the blanket SiO ₂ film, the plasma etching method can be applied as it is. In addition, it may be used in place of the N ₂ gas O ₂ gas as an additive gas in the etching gas used for etching of the Si-containing insulating film.

4 in using an embodiment of a plasma etching apparatus, shows the radial distribution characteristics of the etching rate (E / R) obtained in the experiment of HARC etching to form the contact hole of the aperture 0.25㎛ the SiO ₂ film. The main etching conditions are the same as the etching of the blanket SiO ₂ film, and the second DC voltage V _E is two kinds of -300V and -900V. 5 shows the E / R change rate at each position on the wafer when the second DC voltage V _E is changed from -300V to -900V.

And Fig. 4, a blanket etching SiO ₂ film and the properties of the same in, HARC, as shown in Figure 5 were obtained. That is, the first DC voltage V _C to be applied to the inner upper electrode 60 is selected to an appropriate value (for example, -300 V), and the second DC voltage V _E to be applied to the outer upper electrode 62 is -900 V to. When it is variable within the range of -300 V, the E / R of the edge portion is changed significantly with little change of the E / R of the center portion, and the edge portion of the E / R distribution characteristic on the wafer is lower than the center portion, It can be seen that both the profile in which the central portion and the edge portion become substantially flat (uniform) and the profile in which the edge portion becomes higher than the central portion can be easily realized.

In the plasma etching apparatus of this embodiment, a configuration in which a height difference is provided between the inner upper electrode 60 and the outer upper electrode 62 in the electrode gap direction is also possible. As described above, the outer upper electrode 62 may be protruded downward from the inner upper electrode 60. In FIG. 6, the inter-electrode gap D _C of the semiconductor wafer W on the inner upper electrode 60 and the susceptor 12 is set to 30 cm, for example, and the outer upper electrode 62 and the susceptor 12 are set. The inter-electrode gap D _E of the focus ring 38 on the ()) may be set to, for example, 20 to 25 cm.

In FIG. 7, the experimental result (E / R distribution characteristic) which applied this invention to HARC in the etching conditions similar to the above using the plasma etching apparatus of embodiment which takes the stepped electrode gap structure of FIG. 6 is shown. . According to the experimental results, the in-plane uniformity of E / R can be improved to ± 0.9% under the conditions of V _C = -300 V and V _E = -600 V.

In the application to the HARC of the present invention, the first DC voltage V _C can be selected within the range of -600 V to -150 V under the condition that | V _C | ≤ | V _E | The voltage V _E can be selected within the range of -1000V to -150V. In the etching processing of the connection hole, the second high frequency applied to the susceptor 12 is preferably a low frequency, and preferably 2 MHz to 3.2 MHz so as to strongly inject ions into the processing film.

In the Si-containing film is etched, it is capable of controlling the second DC voltage E / R profile of the distribution characteristics on the semiconductor wafer (W) by changing the value of the V _E as described above, the second DC voltage V _E This is because the electron density Ne distribution characteristics on the semiconductor wafer can be controlled by changing the value, and there is a correlation between the Ne distribution characteristics and the E / R distribution characteristics.

As an example, Ne distribution characteristics and Ne change rate distribution characteristics obtained when the value of the second DC voltage V _E is varied in the etching of the HARC are shown in FIGS. 8 and 9, respectively. As shown in the figure, when the absolute value of the second DC voltage V _E is increased from 0 V to 300 V to 600 V to 900 V, the Ne at the center of the wafer is little changed, but the Ne at the periphery of the wafer is greatly increased and changed to E / R. It was confirmed that there was a correlation with the distribution characteristics.

The plasma etching apparatus and the plasma etching method of the present invention can be preferably applied to an application in which a multilayer film on a substrate surface is continuously etched in a plurality of steps. Hereinafter, the Example of this invention regarding the multilayer resist method as shown to FIG. 10A-10D is demonstrated.

10A to 10D, the SiN layer is formed on the main surface of the semiconductor wafer W to be processed as a lowermost layer (final mask) on the original processed film (for example, a Si film for a gate) 100. 102 is formed, and an organic film (for example, carbon) 104 is formed thereon as an intermediate layer, and an uppermost layer is formed thereon via an Si-containing antireflection coating (BARC) (bottom antireflection coating) 106. Photoresist 108 is formed. In order to form the SiN layer 102, the organic film 104, and the anti-reflection film 106, a coating film by CVD (chemical vacuum deposition) or spin-on is used, and the photoresist 108 is formed. Photolithography is used for patterning.

First, as shown in FIG. 10A, the Si-containing antireflection film 106 was etched using the patterned photoresist 108 as a mask. Main etching conditions are as follows.

Wafer diameter: 300 mm

Etching gas: CF ₄ / O ₂ = 250 / 13sccm

Pressure in chamber: 30 mTorr

High frequency power: 40MHz / 13MHz = 400 / 0W

DC voltage: V _C = 0 V, V _E = 0 V, -300 V, -600 V (3 types)

Although not shown, the in-plane distribution characteristic of the etching rate can be changed by changing the absolute value of the second DC voltage V _E during the etching of the antireflection film 106.

Next, as shown in FIG. 10B, the organic film 104 was etched using the photoresist 108 and the antireflection film 106 as a mask. Main etching conditions are as follows.

Wafer diameter: 300 mm

Etching gas: O ₂ = 750sccm

Pressure in chamber: 20 mTorr

Temperature: Top electrode / chamber side wall / bottom electrode = 150/150/30 ° C.

High frequency power: 40MHz / 13MHz = 400 / 200W

DC voltage: V _C = 0 V, V _E = 0 V, -300 V, -600 V (3 types)

11 shows in-plane distribution characteristics of the etching rate (E / R) obtained by the etching process of the organic film 104. 12 shows in-plane distribution characteristics of the rate of change of E / R.

As shown in FIG. 11, in organic film etching, the first DC voltage V _C applied to the inner upper electrode 60 is fixed at a constant value (0 V), and the outer upper electrode 62 is negatively negative (−). If the absolute value of the second DC voltage V _{E to be} applied is changed, the E / R of the wafer edge portion is substantially constant, and if V _E = 0 V, a high mountain profile that swells greatly at the center of the wafer becomes large. In the case of V _E = -300 V, the E / R becomes a low-profile profile that swells small at the center of the wafer, and in the case of V _E = -600 V, it becomes a pot bottom profile that is largely recessed in the center of the wafer. Therefore, it can be easily estimated that an approximately flat E / R profile is obtained in the middle of V _E = -600 V to -300 V (near -400 V).

In this way, in the application to the organic film etching of the present invention, when the absolute value of the second DC voltage V _E is changed, unlike the etching of the Si-containing insulating film, the E / R of the wafer periphery hardly changes and the E of the wafer center is changed. / R changes Although this principle (action) is not yet clear, it is considered that the interaction between the plasma (oxygen plasma) and the upper electrodes 60, 62 dominates more than the distribution characteristic of the electron density Ne.

In the organic film etching according to the present invention, the first DC voltage V _C may be selected within the range of -100V to 0V, and the second DC voltage V _E may be selected within the range of -900V to 0V. In the case where emphasis is placed on the accuracy of pattern processing shapes, the frequency of the second high frequency may be selected to a slightly higher region (preferably 10 MHz to 13.56 MHz) so as to lower the energy of ion induction slightly. N ₂ gas, CO, COS, H _2, may be used by the addition of NH ₃ in the O ₂ gas as an etching gas. As a combination of gases in organic film etching, the following are mentioned.

O ₂ , O ₂ / N ₂ , O ₂ / CO, O ₂ / SO ₂ , O ₂ / COS, O ₂ / NH ₃ , N ₂ / H ₂ , NH ₃ , N ₂ / H ₂ / O ₂

13, sectional drawing (SEM photograph) of the pattern obtained by the etching process of the said anti-reflective film 106 and the organic film 104 is shown. As shown in the figure, when the absolute value of the second DC voltage V _E is increased from 0 V to 400 V to 900 V, the shoulder collapse 106 ′ of the antireflection film 106 at the upper end of the pattern is reduced, thereby improving the verticality of the pattern. It can be seen that. This effect is more remarkable in a smaller pattern (right) than in a dense pattern (left). In addition, if the value of the second DC voltage V _E is changed, the precision and uniformity of the pattern CD in the radial direction of the wafer (between the center and the edge) are changed, and the CD precision is increased by increasing V _E from 0 V to 400 V to 900 V. It is also understood that uniformity is improved.

10A to 10D, as shown in FIGS. 10C and 10D, the SiN film 102 was etched using the patterned antireflective film 106 and the organic film 104 as a mask. Main etching conditions are as follows.

Wafer diameter: 300 mm

Etching Gas: CHF ₃ / CF ₄ / Ar / O ₂ = 125/225/600 / 60sccm

Pressure in chamber: 75 mTorr

Temperature: Top electrode / chamber side wall / bottom electrode = 150/150/30 ° C.

High frequency power: 40MHz / 13MHz = 0 / 1000W

DC voltage: V _C = -300 V, V _E = 0 V, -300 V, -900 V (3 types)

14 shows in-plane distribution characteristics of the etching rate (E / R) obtained by the etching process of the SiN film 102. As shown in the figure, if the first DC voltage V _C is maintained at a constant value (-300 V) and the absolute value of the second DC voltage V _E is increased from 0 V to 300 V to 900 V, the E / R at the center of the wafer does not change very much. E / R of the wafer periphery is greatly increased and changed. This point is the same as in the case of HARC or BEOL.

Next, as shown in FIG. 15, when the absolute value of the second DC voltage V _E is changed from 300 V to 900 V, the CD shift of the pattern changes more at the wafer periphery (edge) than the wafer center. Therefore, by appropriately selecting the value of the second DC voltage V _E , the uniformity and precision of the CD can be improved for each semiconductor wafer, and further, the pattern transfer accuracy in the multilayer resist method can be improved.

In the etching of the SiN film according to the present invention, the first DC voltage V _C may be selected within the range of -300V to 0V, and the second DC voltage V _E may be selected within the range of -900V to -300V. In addition, in the etching of the SiN film, since high-density pattern etching by radicals is required, it is preferable to slightly lower the energy of ion induction, and to increase the frequency of the second high frequency slightly higher (preferably 10 MHz to 13.56 MHz). ) May be selected.

As mentioned above, although one preferable embodiment of this invention was described, this invention is not limited to the said embodiment at all, A various deformation | transformation is possible. In particular, in the plasma etching apparatus of the present invention, various selections and modifications can be made to the configurations around the inner upper electrode 60 and the outer upper electrode 62.

For example, a configuration in which independent first and second DC voltages V _C and V _E are applied to the inner upper electrode 60 and the outer upper electrode 62 using a single or common variable DC power supply, respectively, is also possible. Do. For example, in the structural example shown in FIG. 16, the output terminal of the variable DC power supply 110 is connected to the outer upper electrode 62 via the filter circuit 112 and the switching switch 114, and the filter circuit 112 ), And are connected to the inner upper electrode 60 via the changeover switch 116 and the variable resistor 118. The DC voltage V _A output from the variable DC power supply 110 is applied to the outer upper electrode 62 as a second DC voltage V _E without a voltage drop as it is, and the voltage drop of the variable resistor 118 from the DC voltage V _A is applied. The subtracted out is applied to the inner upper electrode 60 as the first DC voltage V _C. Each changeover switch 116, 114 has a terminal for passing the output voltage of the variable DC power supply 110 toward the corresponding upper electrode 60, 62, and the ground potential of each corresponding upper electrode 60, 62. It is to be switched between terminals for connecting to (i.e. applying 0 mu s).

In addition, in the structural example shown in FIG. 16, the shower head is provided in both the inner upper electrode 60 and the outer upper electrode 62. As shown in FIG. It is also possible to independently select and control the type or flow rate of the gas discharged from each shower head.

In addition, the present invention is not limited to the application to the lower two-frequency application method as in the above embodiment, and is, for example, a plasma etching apparatus of applying the first high frequency for plasma generation to the upper electrodes 60 and 62. Applicable to

In addition, the present invention is not limited to the plasma etching apparatus, and is applicable to other plasma processing apparatuses such as plasma CVD, plasma oxidation, plasma nitriding, sputtering, and the like. In addition, the to-be-processed board | substrate in this invention is not limited to a semiconductor wafer, Various board | substrates for flat panel displays (FPD), a photo mask, a CD board | substrate, a printed board, etc. are also possible.

Claims (17)

Vacuum exhaust treatment container, A lower electrode for mounting a substrate to be processed in the processing container; An inner upper electrode disposed in front of the lower electrode in the processing container; An outer upper electrode electrically insulated from the inner upper electrode in the processing container and disposed in a ring shape on an outer side thereof in a radial direction; A processing gas supply unit supplying a processing gas to the processing space between the inner and outer upper electrodes and the lower electrode; A first high frequency power supply unit for applying a first high frequency wave to generate the plasma of the processing gas by the high frequency discharge to the lower electrode or the inner and outer upper electrodes; A first DC feeder configured to apply a variable first DC voltage to the inner upper electrode; And a second DC feeder configured to apply a variable second DC voltage to the outer upper electrode. Plasma processing apparatus. The method of claim 1, Wherein the first and second DC power supply units have independent DC power supplies, respectively. Plasma processing apparatus. The method of claim 1, Wherein the first and second DC power supply units have a common DC power supply, and the first DC power supply unit has a variable resistor for voltage drop connected between an output terminal of the DC power supply and the inner upper electrode. Plasma processing apparatus. The method of claim 1, The outer upper electrode is projected to the lower electrode side than the inner upper electrode, and disposed. Plasma processing apparatus. The method of claim 1, And a second high frequency feeder configured to apply a second high frequency wave for introducing ions in plasma to the lower electrode to the substrate. Plasma processing apparatus. In the plasma etching method of etching the insulating film containing Si using the plasma processing apparatus as described in any one of Claims 1-4, The first and second DC voltages are not greater than 0 V, and the absolute value of the second DC voltage is equal to or greater than the absolute value of the first DC voltage. Plasma etching method. The method of claim 6, The insulating film is a SiO ₂ film, The etching process is a process of forming a contact hole in the SiO ₂ film, The first DC voltage is selected from -600V to -150V, Wherein the second DC voltage is selected from -1000V to -150V. Plasma etching method. The method of claim 7, wherein The plasma processing apparatus has a second high frequency feeder for applying a second high frequency to draw the ions in the plasma to the substrate to the lower electrode, wherein the frequency of the second high frequency is selected to be 2MHz to 3.2MHz. Characterized Plasma etching method. The method of claim 6, The insulating film is an SiOC film, The etching process is a process of forming a via hole in the SiOC film, The first DC voltage is selected from -900V to -300V, The second DC voltage is selected from -1500 V to -300 V Plasma etching method. The method of claim 9, The plasma processing apparatus has a second high frequency feeder for applying a second high frequency to draw in the ions in the plasma to the substrate to the lower electrode, the frequency of the second high frequency is selected from 10MHz to 13.56MHz Characterized Plasma etching method. The method of claim 6, The processing gas is an etching gas containing a fluorocarbon gas, an inert gas, an O ₂ gas or an N ₂ gas. Plasma etching method. The method of claim 6, The insulating film is a SiN film used for the intermediate layer or the lowest layer of the multilayer resist, The etching process is a process of forming a SiN mask for etching the underlying film or substrate, The first DC voltage is selected from -300V to 0V, Wherein the second DC voltage is selected from -900V to -300V. Plasma etching method. The method of claim 12, The plasma processing apparatus has a second high frequency feeder for applying a second high frequency to draw in the ions in the plasma to the substrate to the lower electrode, the frequency of the second high frequency is selected from 10MHz to 13.56MHz Characterized Plasma etching method. In the plasma etching method which etch-processes an organic film using the plasma processing apparatus as described in any one of Claims 1-4, The first and second DC voltages are not greater than 0 V, and the absolute value of the second DC voltage is equal to or greater than the absolute value of the first DC voltage. Plasma etching method. The method of claim 14, The first DC voltage is selected from -100V to 0V, Wherein the second DC voltage is selected from -900V to 0V. Plasma etching method. The method of claim 15, The plasma processing apparatus has a second high frequency feeder for applying a second high frequency to draw in the ions in the plasma to the substrate to the lower electrode, the frequency of the second high frequency is selected from 10MHz to 13.56MHz Characterized Plasma etching method. The method of claim 14, The processing gas is O ₂ It is an etching gas containing a gas or N ₂ gas Plasma etching method.