KR20090103792A - Liquid crystal device and driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to obtain a high response speed. CONSTITUTION: A liquid crystal display device comprises an array substrate(10), an opposite substrate(20) and a liquid crystal layer. The array substrate includes the first insulating substrate, a plurality of signal line groups and a plurality of pixel circuits. The signal line groups are supported on the first insulating substrate and include the first and second signal lines(105a,105b). The pixel circuits include the first and second switches(104a,104b). The first switch is connected between the first signal lines. The second switch is connected between the second signal lines. The opposite substrate is supported on the second insulating substrate.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to liquid crystal display technology.

In a liquid crystal display device of an OCB (Optically Compensated Bend) mode and a? Cell mode, a bend orientation is formed in the liquid crystal material. And the retardation of a light control layer is changed by changing the tilt angle of a liquid crystal molecule in the vicinity of each alignment film.

In the OCB mode and the? Cell mode, the liquid crystal material forms a spray orientation in the initial state before the power is turned on. This is because, inherently, the spray orientation is more stable than the bend orientation. Therefore, when starting the display device of OCB mode and (pi) cell mode, the process which transfers the orientation structure of a liquid crystal material from spray orientation to bend orientation is performed. In addition, after starting, in order to prevent the transition from a bend orientation to a spray orientation, as described in patent documents 1 and 2, when a reset voltage is applied at a fixed time interval between electrodes holding the liquid crystal layer, have.

The liquid crystal display device of the OCB mode and the? Cell mode can achieve a higher response speed as compared to the liquid crystal display device of other display modes such as IPS (In-Plane Switching) mode and VA (Vertically Aligned) mode. However, even in the liquid crystal display devices of OCB mode and [pi] cell mode, the response speed comparable to the CRT (Cathode-Ray Tube) display device is not achieved.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2003-140113

[Patent Document 2] Japanese Patent Application Laid-Open No. 2007-183563

An object of the present invention is to achieve a high response speed.

According to the first aspect of the present invention, a plurality of signal line groups, each of which is supported by a first insulating substrate and the first insulating substrate, each of which includes first and second signal lines, and are arranged along the plurality of signal line groups, A first switch connected between the first and second pixel electrodes facing the first insulating substrate, and the first signal line included in the first pixel electrode and one of the plurality of signal line groups, respectively; And an array substrate including a plurality of pixel circuits including a second switch connected between the second pixel electrode and the second signal line included in the one of the plurality of signal line groups, and the plurality of pixel circuits. A second insulating substrate facing the first insulating substrate, the opposite substrate supported by the second insulating substrate and facing the plurality of pixel circuits and facing the plurality of pixel circuits; The liquid crystal display device provided with the liquid crystal layer interposed between the opposing board | substrates is provided.

According to a second aspect of the present invention, there is provided a semiconductor device comprising an insulating substrate, an array substrate including a plurality of pixel circuits each including first and second pixel electrodes facing the first insulating substrate, and the plurality of pixel circuits. A second insulating substrate facing the first insulating substrate, an opposite substrate supported by the second insulating substrate and facing the plurality of pixel circuits, and between the array substrate and the opposite substrate. A method of driving a liquid crystal display device having an intervening liquid crystal layer, the method comprising: selecting the plurality of pixel circuits one by one or every row and first and second to the first and second pixel electrodes included in the selected pixel circuit; Performing a preliminary write operation including supplying 2 preliminary write signals, respectively, and applying a preliminary write voltage between the first and second pixel electrodes; After the operation, supplying the first and second image signals having the absolute value of the difference smaller than the absolute value of the preliminary write voltage to the first and second pixel electrodes included in the selected pixel circuit, respectively. A driving method is provided which includes performing an included write operation.

According to the present invention, it is possible to achieve a high response speed.

1 is a plan view schematically showing a liquid crystal display device according to a first aspect of the present invention.

FIG. 2 is a plan view schematically illustrating a display panel of the liquid crystal display shown in FIG. 1. FIG.

3 is a cross-sectional view taken along line III-III of the display panel of FIG. 2;

4 is a timing chart showing an example of a driving method of the liquid crystal display shown in FIG. 1;

5 is a timing chart showing another example of the method of driving the liquid crystal display shown in FIG. 1;

FIG. 6 is a timing chart illustrating another example of a method of driving the liquid crystal display shown in FIG. 1.

7 is a plan view schematically illustrating a display panel included in a liquid crystal display device according to a second aspect of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: display panel

2: scanning line driving circuit

3: signal line driving circuit

4: reference wiring drive circuit

5: controller

10: array substrate

20: facing substrate

30: liquid crystal layer

40: optical compensation film

50: polarizer

100: semipermeable substrate

101a: scanning line

101b: reference wiring

102: insulating film

103: semiconductor layer

104a. 104b: switch

105a, 105b: signal line

105c and 105d: source electrode

106a, 106b: capacitor

108a, 108b: pixel electrode

109: insulating film

111: alignment layer

200: light transmissive substrate

220: color filter layer

220B, 220G, 220R: colored layer

208: counter electrode

211: alignment layer

EMBODIMENT OF THE INVENTION Hereinafter, the aspect of this invention is described in detail, referring drawings. In addition, the component which exhibits the same or similar function is attached | subjected with the same reference numeral throughout all drawings, and the overlapping description is abbreviate | omitted.

First, the first aspect of the present invention will be described.

1 is a plan view schematically showing a liquid crystal display device according to a first aspect of the present invention. FIG. 2 is a plan view schematically illustrating a display panel of the liquid crystal display illustrated in FIG. 1. 3 is a cross-sectional view taken along line III-III of the display panel illustrated in FIG. 2. In addition, in FIG. 2, the color filter layer and reference wiring (auxiliary capacitance line) mentioned later are abbreviate | omitted.

The liquid crystal display device shown in FIG. 1 is an active matrix liquid crystal display device in OCB mode. The liquid crystal display device includes a liquid crystal display panel 1, a backlight (not shown) disposed so as to face the liquid crystal display panel 1, a scan line driver circuit 2 and a signal line driver circuit 3 connected to the liquid crystal display panel 1. And a reference wiring drive circuit 4 and a controller 5 connected to these drive circuits 2 to 4.

The liquid crystal display panel 1 includes an array substrate 10 and an opposing substrate 20. A frame-shaped seal layer (not shown) is interposed between the array substrate 10 and the counter substrate 20. The space surrounded by the array substrate 10, the counter substrate 20, and the seal layer is filled with a liquid crystal material, and the liquid crystal material forms the liquid crystal layer 30 shown in FIG. 3. The optical compensation film 40 and the polarizing plate 50 are sequentially arranged on the outer surface of the array substrate 10. The optical compensation film 40 and the polarizing plate 50 are sequentially arranged on the outer surface of the opposing substrate 20.

The array substrate 10 includes the light transmissive substrate 100 shown in FIGS. 1 and 3. The substrate 100 is, for example, a glass substrate or a plastic substrate.

On the board | substrate 100, the scanning line 101a and the reference wiring 101b shown in FIGS. 1-3 are arrange | positioned. The scanning lines 101a and the reference wiring 101b each extend in the X direction and are alternately arranged in the Y direction crossing the X direction.

In addition, the X direction and the Y direction are directions parallel to and intersecting with one main surface of the substrate 100. The Z direction mentioned later is a direction perpendicular | vertical to a X direction and a Y direction.

Each of the scanning lines 101a includes a protrusion projecting in the Y direction as shown in FIG. 2. These protrusions are used as gate electrodes of the thin film transistors described later.

Each of the reference wirings 101b includes a protrusion projecting in the Y direction. These protrusions are used as electrodes of a capacitor to be described later.

The scanning line 101a and the reference wiring 101b can be formed in the same process. In addition, as these materials, a metal or an alloy can be used, for example.

The scanning line 101a and the reference wiring 101b are covered with the insulating film 102 shown in FIG. As the insulating film 102, for example, a silicon oxide film can be used.

On the insulating film 102, the semiconductor layer 103 shown in FIG. 2 and FIG. 3 is arranged corresponding to the gate electrode mentioned above. These semiconductor layers 103 intersect with the gate electrodes, respectively. The semiconductor layer 103 is made of amorphous silicon, for example.

The gate electrode, the semiconductor layer 103, and the portion of the insulating film 102 located between the gate electrode and the semiconductor layer 103, that is, the gate insulating film, form a thin film transistor. These thin film transistors are used as the switches 104a and 104b shown in FIGS. 1 and 2.

In this embodiment, the switches 104a and 104b are n-channel thin film transistors. On each semiconductor layer 103, a channel protective layer and an ohmic layer (not shown) are formed.

The switches 104a and 104b may be p-channel thin film transistors. Alternatively, the switches 104a and 104b may be other switching elements such as diodes.

On the insulating film 102, as shown in FIG. 3, signal lines 105a and 105b and source electrodes 105c and 105d are further disposed.

As shown in FIG. 2, the signal lines 105a extend in the Y direction, and are arranged in the X direction corresponding to the columns formed by the pixel switch 104a. The signal line 105a covers the drain of the semiconductor layer 103 included in the pixel switch 104a. That is, part of the signal line 105a is a drain electrode connected to the pixel switch 104a.

As shown in FIG. 2, the signal lines 105b extend in the Y direction, and are arranged in the X direction corresponding to the columns formed by the pixel switch 104b. The signal line 105b covers the drain of the semiconductor layer 103 included in the pixel switch 104b. That is, part of the signal line 105b is a drain electrode connected to the pixel switch 104b.

The source electrode 105c is arranged corresponding to the pixel switch 104a as shown in FIG. The source electrode 105c covers the source of the switch 104a and faces the reference wiring 101b. The source electrode 105c, the reference wiring 101b, and the insulating film 102 interposed therebetween form a capacitor 106a.

The source electrode 105d is arranged corresponding to the pixel switch 104b as shown in FIG. The source electrode 105d covers the source of the switch 104b and faces the reference wiring 101b. The source electrode 105d, the reference wiring 101b, and the insulating film 102 interposed therebetween form a capacitor 106b.

On the insulating film 102, the first pixel electrode 108a shown in Figs. 1 to 3 is further arranged. As shown in Figs. 2 and 3, these pixel electrodes 108a at least partially cover the source electrodes 105c, respectively. As the material of the pixel electrode 108a, for example, indium tin oxide (ITO) can be used.

Each pixel electrode 108a is a continuous film in which no opening is formed. In each pixel electrode 108a, an opening may be formed in a portion facing the pixel electrode 108b described later.

The pixel electrode 108a is covered with the insulating film 109 shown in FIG. The insulating film 109 is, for example, a transparent inorganic layer such as a silicon oxide film and a silicon nitride film. As the insulating film 109, a transparent organic layer may be used.

The pixel electrodes 108a and 108b are typically transparent electrodes. When this liquid crystal display device is made into a reflective type, the pixel electrodes 108a and 108b may be reflective electrodes. In addition, when making this liquid crystal display device semi-transmissive, each of the pixel electrodes 108a and 108b may include the reflecting part and the transmission part.

On the insulating film 109, as shown in FIGS. 2 and 3, the second pixel electrode 108b is arranged corresponding to the first pixel electrode 108a. These pixel electrodes 108b are electrically insulated from the pixel electrodes 108a, and at least partially cover the source electrodes 105d, respectively. As a material of the pixel electrode 108b, IT0 can be used, for example.

The pixel electrode 108b faces only a part of the pixel electrode 108a. Each pixel electrode 108b has a plurality of slits each extending in the Y direction and arranged in the X direction.

The insulating film 109 and the pixel electrode 108b are covered with the alignment film 111 shown in FIG. In the vicinity of the alignment film 111, the liquid crystal molecules are inclinedly aligned at a relatively large pretilt angle, for example, 5 ° to 10 °. The alignment film 111 is obtained by performing, for example, rubbing or the like on an organic film made of acryl, polyimide, nylon, polyamide, polycarbonate, benzocyclobutene polymer, polyacrylonitrile, polysilane, or the like. . Or the alignment film 111 is obtained by vapor-depositing silicon oxide, for example. Among them, polyimide, polyacrylonitrile and nylon are excellent in terms of ease of film formation and chemical stability.

The direction in which the alignment film 111 tilts the liquid crystal molecules is arbitrary. Typically, the direction in which the alignment film 111 tilts the liquid crystal molecules is set such that the orthogonal projection to the XY plane in the direction and the longitudinal direction of the comb pattern of the pixel electrode 108b cross vertically or obliquely. Here, as an example, it is assumed that the polyimide film rubbed along the X direction is used as the alignment film 111.

In addition, the switches 104a and 104b, the capacitors 106a and 106b, and the pixel electrodes 108a and 108b shown in FIG. 1 form a pixel circuit. The pixel circuit may not include one or both of the capacitors 106a and 106b.

The opposing substrate 20 includes the light transmissive substrate 200 shown in FIG. 3. The substrate 200 is, for example, a glass substrate or a plastic substrate.

On the board | substrate 200, the black matrix which is not shown in figure and the color filter layer 220 shown in FIG. 3 are formed in this order.

The black matrix is a light shielding layer in which a portion facing the pixel electrode 108a is opened. The black matrix is, for example, a lattice pattern or a stripe pattern layer. As a material of a black matrix, metal or alloys, such as chromium, can be used, for example.

The color filter layer 220 includes the red colored layer 220R, the green colored layer 220G, and the blue colored layer 220B. The colored layers 220R, 220G, and 220B form a stripe arrangement corresponding to the columns formed by the pixel circuits. The colored layers 220R, 220G, and 220B may form another arrangement, such as a delta arrangement and a square arrangement.

On the color filter layer 220, the counter electrode 208 shown in FIG. 1 and FIG. 3 is formed. The counter electrode 208 is a common electrode facing the pixel electrodes 108a and 108b. As a material of the counter electrode 208, IT0 can be used, for example.

The counter electrode 208 is covered with the alignment film 211 shown in FIG. As the alignment film 211, a film similar to the alignment film 111 can be used. In this example, a polyimide film that is rubbed in the same direction as the alignment film 111 is used as the alignment film 211.

As shown in FIG. 3, the array substrate 10 and the counter substrate 20 are arranged such that their alignment films 111 and 211 face each other. A frame-shaped seal layer (not shown) is interposed between the array substrate 10 and the counter substrate 20. The seal layer joins the array substrate 10 and the counter substrate 20 to each other. As a material of a seal layer, an adhesive agent can be used.

A transfer electrode (not shown) is disposed outside the frame formed by the seal layer between the array substrate 10 and the counter substrate 20. The transfer electrode connects the counter electrode 208 to the array substrate 10.

Granular spacers are interposed between the array substrate 10 and the counter substrate 20, or the array substrate 10 and / or the counter substrate 20 further include columnar spacers. These spacers form a gap with a substantially constant thickness at a position corresponding to the pixel electrode 108a between the array substrate 10 and the counter substrate 20.

The space surrounded by the array substrate 10, the counter substrate 20, and the adhesive layer is filled with a liquid crystal material. This liquid crystal material forms the liquid crystal layer 30 shown in FIG. As this liquid crystal material, the nematic liquid crystal material which plus dielectric anisotropy can be used, for example.

The pixel electrodes 108a and 108b, the counter electrode 208, the alignment films 111 and 211, and the liquid crystal layer 30 form a liquid crystal element. Each pixel PX shown in FIG. 1 includes these liquid crystal elements, switches 104a and 104b, and capacitors 106a and 106b. The signal lines 105a and 105b connected to the same pixel PX constitute a signal line group. In addition, the array substrate 10, the counter substrate 20, and the liquid crystal layer 30 and the seal layer interposed therebetween form a liquid crystal cell.

The optical compensation film 40 shown in FIG. 3 is a biaxial film, for example. The optical compensation film 40 includes an optically anisotropic layer in which a uniaxial compound having a negative refractive index anisotropy, for example, a discotic liquid crystal compound, is bend-oriented such that its optical axis changes in a plane perpendicular to the X direction. Can be used.

The retardation of each optical compensation film 40 is made into about half of the retardation in the 0N state of the liquid crystal layer 30, for example. In this case, these optical compensation films 40 are arranged so that the retardation of the laminate of the liquid crystal layer 30 and the optical compensation film 40 in the 0N state becomes almost zero, for example.

The polarizing plate 50 shown in FIG. 3 is arrange | positioned so that their transmission axes may mutually orthogonally cross, for example. In addition, each polarizing plate 50 is provided so that the transmission axis may make an angle of 45 degrees with respect to an X direction and a Y direction, for example.

As shown in FIG. 1, the scan line driver circuit 2 is connected to the scan line 101a. The scan line driver circuit 2 sequentially supplies the first scan voltage for closing the switches 104a and 104b to the scan line 101a. The scan line driver circuit 2 supplies the second scan voltage for opening the switches 104a and 104b to the scan line 101a which is not supplying the first scan voltage.

As shown in FIG. 1, the signal lines 105a and 105b are connected to the signal line driver circuit 3. The signal line driver circuit 3 supplies the first and second signal voltages to the signal lines 105a and 105b, respectively. Specifically, the signal line driver circuit 3 supplies the first reset signal, the first preliminary write signal, and the first video signal as the first signal voltage to the signal line 105a. The signal line driver circuit 3 supplies the second reset signal, the second preliminary write signal, and the second video signal as the second signal voltage to the signal line 105b.

The reference wiring 101b is connected to the reference wiring driving circuit 4 as shown in FIG. 1. The reference wiring drive circuit 4 is, for example, when the signal line driver circuit 3 inverts the polarity of the first and second video signals output to the signal lines 105a and 105b from plus to minus, for example, those videos. At the start of supply of the reset signal to the pixel PX to write the signal, the potential of the reference wiring 101b to which the pixel PX to write these video signals is connected is changed from the first potential to the second potential. When the signal line driver circuit 3 inverts the polarity of the first and second video signals output to the signal lines 105a and 105b, respectively, from negative to positive, for example, to the pixel PX to write these video signals. At the start of supply of the reset signal, the potential of the reference wiring 101b to which the pixel PX to write these video signals is connected is changed from the second potential to the first potential. In addition, the term "polarity" means the polarity of the difference between the potential of the video signal and the potential of the counter electrode 208.

One of the drive circuits 2 to 4 includes a voltage source connected to the counter electrode 208. This voltage source includes a voltage source for controlling the potential of the counter electrode 208. For example, this voltage source keeps the potential of the counter electrode 208 constant. Alternatively, this voltage source periodically changes the potential of the counter electrode 208 between the first and second potentials. In the latter case, the signal line is driven when the potential of the counter electrode 208 is changed from the first electrostatic potential to the second electrostatic potential, and when the potential of the counter electrode 208 is changed from the second electrostatic potential to the first electrostatic potential. The polarities of the first and second signal voltages output by the circuit 3 are inverted.

The drive circuits 2 to 4 may be mounted with Chip 0n Glass (C0G). Alternatively, the drive circuits 2 to 4 may be mounted with a tape carrier package (TCP).

As shown in FIG. 1, the controller 5 is connected to the drive circuits 2 to 4. The controller 5 controls the operation of the drive circuits 2 to 4 according to the method described below, for example.

FIG. 4 is a timing chart showing an example of a driving method of the liquid crystal display shown in FIG. 1. In FIG. 4, the horizontal axis represents time, and the vertical axis represents voltage or potential. In addition, "V _scan 1" and "V _scan 2" have shown the 1st and 2nd scan voltage, respectively. "Scan voltage V _scan (m)" shows the waveform of the scan voltage which the scan line driver circuit 2 outputs to the m-th scan line 101a. The signal voltage V _sig 1 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105a connected to a certain pixel PX. The signal voltage V _sig 2 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105b connected to the preceding pixel PX.

In the driving method shown in Fig. 4, each frame is composed of three or more fields. In each field period, scanning is performed sequentially. The signal line driver circuit 3 simultaneously supplies the signal voltages to all the signal line groups. In this driving method, the potential V _com of the counter electrode 208 is made constant.

In the first field period of each frame period, a reset operation is performed. Specifically, in the first field period of each frame period, the signal line driver circuit 3 controls the first reset signals V _rst 1 and second to the signal lines 105a and 105b under the control by the controller 5. The reset signals V _rst 2 are supplied respectively. Thus, in each pixel PX, the first voltage V1 between the pixel electrode 108a and the counter electrode 208 is set to the first reset voltage V _rst 1-V _com , and the pixel electrode 108b and the counter electrode are set. The second voltage V2 between 208 is set to the second reset voltage V _rst 2-V _com .

The reset signals V _rst 1 and V _rst 2 are, for example, nearly equal in potential. The reset voltage V _rst 1-V _com is, for example, the maximum value of the voltage applied between the pixel electrode 108a and the counter electrode 208 after the initial transition of transferring the alignment structure of the liquid crystal material from the spray orientation to the bend orientation. The absolute value is almost equal to or greater than the value. The reset voltage V _rst 2-V _com is, for example, the maximum value of the voltage applied between the pixel electrode 108b and the counter electrode 208 after the initial transition of transferring the alignment structure of the liquid crystal material from the spray orientation to the bend orientation. The absolute value is almost equal to or greater than the value. The absolute value of the reset voltage V _rst 1-V _com is, for example, within a range of 3V to 8V. The absolute value of the reset voltage V _rst 2-V _com is, for example, within the range of 3V to 7V.

The reset voltage V _rst 1-V _com may be larger than the reset voltage V _rst 2-V _com in consideration of the voltage drop caused by the insulating film 109. That is, the same magnitude voltage is applied to the region of the liquid crystal layer 30 corresponding to the portion of the pixel electrode 108a not facing the pixel electrode 108b and the region corresponding to the pixel electrode 108b. The set voltages V _rst lV _com and V _rst 2-V _com may be set. By doing in this way, the fall of contrast ratio resulting from the difference in the transmittance | permeability of the part corresponding to these areas can be prevented.

In the second field period of each frame period, the preliminary write operation and the write operation are executed in this order within each selection period in which the scan line driver circuit 2 supplies the first scan voltage to one scan line 101a. .

Specifically, in each selection period, the signal line driver circuit 3 firstly controls the first preliminary write signal V _prw 1 and the second preliminary write signal to the signal lines 105a and 105b under the control by the controller 5. Supply V _prw 2 respectively. Thus, in each pixel PX, the third voltage V3 between the pixel electrodes 108a and 108b is set to the preliminary write voltages V _prw 1-V _prw 2.

The preliminary write voltage V _prw 1-V _prw 2 has a larger absolute value than the difference V _rst 1-V _rst 2 between the reset voltage V _rst 1 -V _com and the reset voltage V _rst 2 -V _com . The absolute value of the preliminary write voltage V _prw 1-V _prw 2 is, for example, within a range of 2V to 9V. Alternatively, the absolute value of the preliminary write voltage V _prw 1-V _prw 2 is, for example, within a range of 60% to 180% of the absolute value of the reset voltage V _rst 2-V _com .

In the pixel PX in which the voltage V3 is set to the preliminary writing voltage V _prw 1-V _prw 2, the voltage V1 is typically smaller in absolute value compared to the reset voltage V _rst 1-V _com, and the voltage V2 is reset. The absolute value is smaller compared to the voltage V _rst 2-V _com . The absolute value of the voltage V1 is, for example, 90% or less of the absolute value of the reset voltage V _rst 1-V _com . The absolute value of the voltage V2 is, for example, 90% or less of the absolute value of the reset voltage V _rst 2-V _com .

Next, the signal line driver circuit 3 supplies the first video signal V _video 1 and the second video signal V _video 2 to the signal lines 105a and 105b, respectively, under control by the controller 5. This sets the voltage V1 to the first video signal voltage V _video 1-V _com, and sets the voltage V2 to the second video signal voltage V _video 1-V _com . 4, 'V _video (m) 1' and 'V _video (m) 2' respectively represent video signals V _video 1 and video signals V _video 2 to be written into the m-th pixel PX.

Each of the video signals V _video 1 and V _video 2 is a signal corresponding to the image to be displayed. For example, each of the video signals V _video 1 and V _video 2 corresponds to the gradation of the image to be displayed. The video signal voltage V _video 1-V _com is equal to or smaller than the absolute value of the reset voltage V _rst 1-V _com . The video signal voltage V _video 2-V _com is equal to or smaller than the absolute value of the reset voltage V _rst 2-V _com .

The video signal voltage V _video 1-V _com may have a larger absolute value than the video signal voltage V _video 2-V _com in consideration of the voltage drop caused by the insulating film 109. That is, the same magnitude voltage is applied to the region corresponding to the portion of the liquid crystal layer 30 which is not facing the pixel electrode 108b of the pixel electrode 108a and the region corresponding to the pixel electrode 108b. The signal voltages V _video 1-V _com and V _video 2-V _com may be set. By doing in this way, the fall of contrast ratio resulting from the difference in the transmittance | permeability of the part corresponding to these areas can be prevented.

Next, a preliminary write operation and a write operation to the m + 1st pixel PX are performed in this order by the same method as described for the mth pixel PX. In the second and subsequent field periods of each frame period, preliminary write operations and write operations are performed on all the pixels PX in this manner.

In the third and subsequent field periods of each frame period, the above write operation is executed. In other words, the third and subsequent field periods of each frame period are the same as the second field period except that the preliminary write operation is omitted.

In this driving method, as described above, the reset operation is executed at a constant cycle. As such, no unwanted transition from bend orientation to spray orientation occurs.

In general, a liquid crystal display device in which the liquid crystal molecules form a bend alignment has a relatively quick response when increasing the voltage applied to the liquid crystal layer, and a relatively slow response when decreasing the voltage applied to the liquid crystal layer. . For example, the response time when the voltage applied to the liquid crystal layer is changed from the maximum value to zero is several to several tens of times the response time when the voltage applied to the liquid crystal layer is changed from zero to the maximum value. This means that when the voltage applied to the liquid crystal layer is changed from the maximum value to zero, the change of the alignment state occurs due to the action of the electric field, whereas only the elastic force is used when the voltage applied to the liquid crystal layer is changed from the maximum value to zero. This is because a change in the orientation state occurs. For this reason, for example, when a video signal with zero voltage applied to the liquid crystal layer is written into the pixel immediately after the reset operation, there is a possibility that a sufficient response speed cannot be achieved.

The preliminary write operation includes setting the voltage V3 to the preliminary write voltages V _prw 1-V _prw 2. In other words, the preliminary write operation includes applying a voltage between the pixel electrodes 108a and 108b and generating a transverse electric field substantially perpendicular to the Z direction in the vicinity of the alignment film 111. This transverse electric field inclines the liquid crystal molecules rapidly in the vicinity of the alignment film 111 with respect to the Z direction. Therefore, regardless of the magnitude of the video signal to be written by the write operation following the preliminary write operation, the change of the orientation state can be completed immediately after starting the write operation. Therefore, when the preliminary write operation is performed, high response speed can be achieved.

In this driving method, preliminary write operations and write operations may be performed in this order in each selection period of the third and subsequent field periods. In this way, a short response time can be achieved even in the field period immediately after writing the video signal whose maximum value is the absolute value of the voltage applied to the liquid crystal layer 30 to the pixel PX.

Each frame may be composed of two fields. In other words, the third field period described above may be omitted.

The field period for performing the reset operation may not be the first field period of each frame. For example, the write operation may be performed in the first field period, the reset operation may be performed in the second field period, and the preliminary write operation and the write operation may be performed in the third field period.

The reset operation may be performed only in some frame periods. In addition, the reset operation may be omitted. In any case, for example, a short response time can be achieved in the field period immediately after the video signal whose maximum value is the absolute value of the voltage applied to the liquid crystal layer 30 is written into the pixel PX.

FIG. 5 is a timing chart showing another example of the method for driving the liquid crystal display shown in FIG. 1. In Fig. 5, the horizontal axis represents time and the vertical axis represents voltage or potential. In addition, "V _scan 1" and "V _scan 2" have shown the 1st and 2nd scan voltage, respectively. "Scan voltage V _scan (m)" shows the waveform of the scan voltage which the scan line driver circuit 2 outputs to the m-th scan line 101a. The signal voltage V _sig 1 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105a connected to a certain pixel PX. The signal voltage V _sig 2 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105b connected to the preceding pixel PX.

In the driving method shown in Fig. 5, each frame is composed of one field. In each field period, the above-described reset operation, preliminary write operation, and write operation are executed in this order. Other than this, the drive method shown in FIG. 5 is the same as the drive method demonstrated while referring FIG.

The driving method shown in FIG. 5 has a larger number of operations performed in one selection period than in the driving method shown in FIG. 4. That is, when the driving method shown in FIG. 5 is employed, the load on the signal line driving circuit 3 is larger than when the driving method shown in FIG. 4 is adopted.

However, in the driving method shown in Fig. 5, since both the reset operation and the write operation are performed within one selection period, there is no period in which no image is displayed. Therefore, when the driving method shown in FIG. 5 is adopted, higher use efficiency of light or a higher contrast ratio can be achieved as compared with the case where the driving method shown in FIG. 4 is adopted.

In this driving method, each frame is composed of one field. Instead, each frame may consist of two or more fields. In this case, the reset operation and the preliminary write operation may be performed in each field period, or the reset operation and the preliminary write operation may be executed only in a part of the field period.

In this driving method, the reset operation and the preliminary write operation may be performed only in some frame periods.

FIG. 6 is a timing chart showing another example of the method of driving the liquid crystal display shown in FIG. 1. In Fig. 6, the horizontal axis represents time and the vertical axis represents voltage or potential. In addition, "V _scan 1" and "V _scan 2" have shown the 1st and 2nd scan voltage, respectively. "Scan voltage V _scan (m)" shows the waveform of the scan voltage which the scan line driver circuit 2 outputs to the m-th scan line 101a. The signal voltage V _sig 1 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105a connected to a certain pixel PX. The signal voltage V _sig 2 indicates the waveform of the signal voltage output by the signal line driver circuit 3 to the signal line 105b connected to the preceding pixel PX.

In the driving method shown in Fig. 6, each frame is composed of three or more fields. In the first field period of each frame engine, the above-described reset operation is executed. In the second field period of each frame period, the above-described preliminary writing operation is executed. In the third and subsequent field periods of each frame period, the above-described writing operation is executed. Except for this, the driving method shown in FIG. 6 is the same as the driving method described with reference to FIG. 4.

The driving method shown in Fig. 6 executes the preliminary write operation and the write operation in different field periods. Therefore, the driving method shown in FIG. 6 has a larger ratio of one frame period to the period in which no image is displayed than the driving method shown in FIG.

However, the driving method shown in FIG. 6 has a smaller number of operations performed in one selection period than in the driving method shown in FIG. 4. That is, when the driving method shown in FIG. 6 is adopted, the load on the signal line driving circuit 3 is smaller than in the case where the driving method shown in FIG. 4 is adopted.

In this driving method, the field period for performing the reset operation may not be the first field period of each frame. For example, the write operation is performed in the first field period, the reset operation is performed in the second field period, the preliminary write operation is performed in the third field period, and the write operation is performed in the fourth field period. You may perform an operation.

In this driving method, the reset operation and the preliminary write operation may be performed only in some frame periods.

In the driving method described with reference to FIGS. 4 to 6, the signal line driver circuit 3 simultaneously supplies the signal voltages to all the signal line groups. Instead, the signal line driver circuit 3 may supply the signal voltage to the signal line group sequentially.

When each frame includes two or more field periods for performing a write operation, the write operation performed in a certain field period and the write operation performed in another field period have the same waveform of the signal voltage output by the signal line driver circuit 3. It may be sufficient and may differ. In the latter case, gradation display by, for example, time division gray scale is possible.

The potential V _com of the counter electrode 208 may be changed periodically between the first and second potentials. For example, in synchronization with one or more frame periods, the potential V _com of the counter electrode 208 may be changed between the first and second electrostatic potentials.

Next, a second aspect of the present invention will be described.

7 is a plan view schematically illustrating a display panel included in the liquid crystal display device according to the second embodiment of the present invention.

The liquid crystal display device according to the second aspect is an active matrix liquid crystal display device in OCB mode. This liquid crystal display device is the liquid crystal display device described with reference to FIGS. 1 to 3 except that the gates of the switches 104a and 104b are connected to different scanning lines 101a in each pixel as shown in FIG. 7. Almost the same as In addition, in FIG. 7, the above-mentioned color filter layer 220 and the reference wiring 101b are abbreviate | omitted.

The display device employing the structure shown in FIG. 7 can be driven by, for example, the method described with reference to FIG. 6. In this case, display performance similar to that when the liquid crystal display device described with reference to FIGS. 1 to 3 is driven by the method described with reference to FIG. 6 can be achieved.

In the display device described above, the pixel electrode 108b may be formed on the insulating film 102. That is, the pixel electrode 108b may be adjacent to the pixel electrode 108a on the insulating film 102. In this case, for example, comb-shaped electrodes may be used as the pixel electrodes 108a and 108b, and they may be arranged so that the comb portions of the pixel electrodes 108a and the comb portions of the pixel electrodes 108b are alternately arranged. However, when such a structure is adopted, there is a possibility that light leakage occurs between the pixel electrode 108a and the pixel electrode 108b.

The above technique can also be applied to liquid crystal display devices having display modes other than the OCB mode. For example, the above-mentioned technique is applicable also to the liquid crystal display device of (pi) cell mode.

Hereinafter, the example of this invention is demonstrated.

<Example 1>

In this example, the liquid crystal display device described with reference to FIGS. 1 to 3 was manufactured by the following method.

In manufacturing the array substrate 10, first, the scanning line 101a and the reference wiring 101b were formed on the glass substrate 100. FIG. Chromium was used as a material of these wirings.

Next, these wirings and the glass substrate 100 were covered with the insulating film 102 made of silicon oxide. The amorphous silicon layer was formed on this insulating film 102, and the semiconductor layer 103 was obtained by patterning this. Thereafter, a channel protective layer (not shown) made of silicon nitride was formed on a part of each semiconductor layer 103, and an ohmic layer (not shown) was formed on the semiconductor layer 103 and the channel protective layer.

Next, signal lines 105a and 105b and source electrodes 105c and 105d were formed on the insulating film 102. On the insulating film 102, a pixel electrode 108a made of ITO was formed so as to partially cover the source electrode 105. The pixel electrode 108a was formed by forming an ITO film and patterning it using photolithography technique.

Thereafter, an insulating film 109 made of silicon nitride was deposited on the signal lines 105a and 105b, the source electrodes 105c and 105d, and the pixel electrode 108a. In this insulating film 109, contact holes were formed at positions corresponding to the source electrodes 105d.

Next, on the insulating film 109, the pixel electrode 108b made of ITO was formed so that they filled up the previous contact hole. The pixel electrode 108b was formed by forming the ITO layer as a continuous film on the insulating film 109, and patterning this ITO layer using photolithography technique.

In manufacturing the counter substrate 20, first, a chromium film was formed on the glass substrate 200, and this was patterned. This obtained the black matrix. Then, the stripe-shaped color filter 220 was formed using the photosensitive acrylic resin which mixed red, green, and blue pigment on it, respectively.

Next, the transparent acrylic resin was apply | coated on the color filter 220, and the planarization layer (overcoat) which is not shown in figure was formed. Thereafter, the counter electrode 208 was formed by sputtering ITO on the planarization layer. Further, on the counter electrode 208, columnar spacers (not shown) having a height of 5 m and a bottom of 5 m x 10 m were formed by the photolithography method. These columnar spacers were formed so as to be located on the signal line 105a when the array substrate 10 and the counter substrate 20 were bonded to each other.

After washing the pixel electrode 108b and the counter electrode 208, the polyimide solution (SE-5291 by Nissan Chemical) was apply | coated on them by offset printing. These coating films were heated at 90 degreeC for 1 minute using a hotplate, and were further heated at 200 degreeC for 30 minutes. In this manner, the alignment films 111 and 211 were formed.

Next, rubbing was performed to the alignment films 111 and 211 using an exempt cloth. The rubbing to these was performed so that the direction of rubbing with respect to the orientation film 111 and the direction of rubbing with respect to the orientation film 211 become the same direction when the array substrate 10 and the counter substrate 20 were bonded together. Specifically, the alignment films 111 and 211 were rubbed so that the rubbing direction was parallel to the X direction when the array substrate 10 and the counter substrate 20 were bonded to each other. Also, for each rubbing, an exempt rubbing cloth having a diameter of the hair tip of 0.1 µm to 10 µm was used, and the rotation speed of the rubbing roller was 500 rpm, the substrate movement speed was 20 mm / s, the indentation amount was 0.7 mm, and the number of rubbings. One time. After rubbing, the alignment films 111 and 211 were washed with an aqueous solution containing neutral surfactant as a main component.

Then, the epoxy adhesive which is a material of a sealing layer was apply | coated to the main surface of the opposing board | substrate 20 using the dispenser so that the alignment film 211 may be enclosed. In the mold formed by the adhesive layer, an opening used later as an injection hole was formed. Subsequently, the array substrate 10 and the counter substrate 20 were disposed so that the alignment films 111 and 211 faced each other and their rubbing directions were equal to each other. After the alignment, the array substrate 10 and the counter substrate 20 were bonded to each other, and the adhesive was cured by heating to 160 ° C. under pressure.

Next, the empty cell obtained in this way was carried into the vacuum chamber, and the inside of the cell was made into the vacuum. Thereafter, a liquid crystal material was injected into the cell from the injection port. As a liquid crystal material, the Melk Japan company E7 which is a nematic liquid crystal composition was used.

Thereafter, the inlet was sealed with an epoxy adhesive. As described above, a liquid crystal cell was obtained. In addition, the cell gap of this liquid crystal cell was about 5 micrometers.

Next, the optical compensation film 40 and the polarizing plate 50 were stuck in this order on one main surface of the liquid crystal cell. And the optical compensation film 40 and the polarizing plate 50 were also stuck in this order also to the other main surface of the liquid crystal cell. Here, in the state where a voltage of 5 V is applied between the pixel electrode 108b and the counter electrode 208, the retardation and the optical compensation film 40 of the region corresponding to the pixel electrode 108b of the liquid crystal layer 30 are applied. A design was adopted in which the sum of retardation was almost zero. Further, the polarizing plates 50 were arranged such that their transmission axes were substantially orthogonal to each other and that their transmission axes were substantially parallel to the X direction or the Y direction.

Thereafter, the drive circuits 2 to 4 and the like were connected to the array substrate 10, and the drive circuits 2 to 4 were connected to the controller 5. In addition, the display panel 1 and the backlight were combined. As described above, the QVGA type liquid crystal display device was completed.

This liquid crystal display device was driven by the method described with reference to FIG. 4.

Specifically, each frame was composed of two fields. That is, the third and subsequent field periods described with reference to FIG. 4 are omitted. The first field period for applying the reset voltage was 3.2 milliseconds, and the second field period was 13.5 milliseconds. In the second field period of each frame period, pre-write signals V _prw 1 and V _prw 2 are supplied to the signal lines 105a and 105b for 56 microseconds in each selection period.

The reset voltage V _prw 1-V _com was 6V and the reset voltage V _prw 2-V _com was 5V. The difference between the preliminary write signal V _prw 1 and the potential V _com of the counter electrode 208 was 2.5V, and the difference between the preliminary write signal V _prw 2 and the potential V _com of the counter electrode 208 was -2V. The video signal voltages V _video 1-V _com and V _video 2-V _com were 0V.

When the liquid crystal display device was driven under this condition, a response time of 3.5 milliseconds could be achieved. Moreover, when the white image and the black image were displayed on the liquid crystal display device under this condition, the contrast ratio of 1000: 1 was achieved.

<Example 2>

In this example, the liquid crystal display device manufactured in Example 1 was driven by the method described with reference to FIG. 5. Specifically, each frame is composed of one field, and each field period is 16.7 milliseconds. In each selection period, the pre-write signals V _prw 1 and V _prw 2 were supplied to the signal lines 105a and 105b for 23 microseconds. Conditions other than this were the same as that of Example 1.

When the liquid crystal display device was driven under this condition, a response time of 4 milliseconds could be achieved. Moreover, when a white image and a black image were displayed on the liquid crystal display device under this condition, the contrast ratio of 1200: 1 was achieved.

<Example 3>

In this example, the liquid crystal display device manufactured in Example 1 was driven by the method described with reference to FIG. 6. Specifically, each frame is composed of three fields, and the first field period for applying the reset voltage is 1.5 milliseconds, the second field period is 1.5 milliseconds, and the third The field period was 13.7 milliseconds. In the second field period of each frame period, pre-write signals V _prw 1 and V _prw 2 are supplied to the signal lines 105a and 105b for 1.5 milliseconds in each selection period. Conditions other than this were the same as that of Example 1.

When the liquid crystal display device was driven under this condition, a response time of 3 milliseconds could be achieved. Moreover, when the white image and the black image were displayed on the liquid crystal display device under this condition, the contrast ratio of 1000: 1 was achieved.

Comparative Example

A liquid crystal display device having a structure similar to that prepared in Example 1 was manufactured except that the pixel electrode 108b was omitted and the pixel electrode 108a was disposed between the insulating film 109 and the alignment film 111. The liquid crystal display device was driven by the same method as described in Example 3 except that the field period for the preliminary writing operation was omitted. The driving conditions were the same as in Example 3 except that the reset voltage V _rst 1-V _com was 5V and the reset voltage V _rst 2-V _com was 0V.

When the liquid crystal display device was driven under this condition, the response time was 5.5 milliseconds. Moreover, when a white image and a black image were displayed on the liquid crystal display device under this condition, the contrast ratio was 800: 1.

Claims (20)

A plurality of signal line groups supported by the first insulating substrate, the first insulating substrate, each of which includes first and second signal lines, and arranged along the plurality of signal line groups, and each of the first and second pixels A first switch connected between an electrode, the first pixel electrode and the first signal line included in one of the plurality of signal line groups, and the one of the second pixel electrode and the plurality of signal line groups; An array substrate comprising a plurality of pixel circuits including a second switch connected between said second signal lines; A second insulating substrate facing the first insulating substrate with the plurality of pixel circuits interposed therebetween, an opposing substrate supported on the second insulating substrate and including a counter electrode facing the plurality of pixel circuits; And a liquid crystal layer interposed between the array substrate and the opposing substrate. The method of claim 1, The liquid crystal molecule contained in the said liquid crystal layer forms a bend orientation at the time of image display. The method of claim 1, And the second pixel electrode faces the first insulating substrate with a portion of the first pixel electrode interposed therebetween. The method of claim 3, A plurality of slits are formed in the second pixel electrode. The method of claim 4, wherein The array substrate further includes a first alignment layer covering the first and second pixel electrodes, the counter substrate further includes a second alignment layer covering the counter electrode, and the length direction of the slit is the first alignment layer. And the first and second alignment layers are perpendicular or oblique to the orthographic projection to the first insulating substrate in the direction in which the liquid crystal molecules are inclined. The method of claim 1, The array substrate further includes a plurality of scanning lines supported on the first insulating substrate, and in each of the plurality of pixel circuits, the first switch is a first thin film transistor having a gate connected to one of the plurality of scanning lines. And the second switch is a second thin film transistor whose gate is connected to the scan line to which the gate of the first thin film transistor is connected. The method of claim 1, The array substrate further includes a plurality of scanning lines supported on the first insulating substrate, and in each of the plurality of pixel circuits, the first switch is a first thin film transistor having a gate connected to one of the plurality of scanning lines. And the second switch is a second thin film transistor having a gate connected to another one of the plurality of scan lines. The method of claim 1, The array substrate further includes a plurality of scan lines supported by the first insulating substrate, The display device, A scan line driver circuit for sequentially supplying scan voltages for closing the first and second switches to the plurality of scan lines; A signal line driver circuit for respectively supplying first and second signal voltages to the first and second signal lines included in each of the plurality of signal line groups; A controller connected to the scan line driver circuit and the signal line driver circuit, and controls an operation of the scan line driver circuit and the signal line driver circuit. It further comprises a liquid crystal display device. The method of claim 8, The controller controls the operations of the scan line driver circuit and the signal line driver circuit so that the preliminary write operation and the write operation are executed in this order, The preliminary write operation includes a first operation on the first and second signal lines included in each of the plurality of signal line groups within a selection period in which the scan line driver circuit supplies the scan voltage to one of the plurality of scan lines. And supplying a second preliminary write signal, respectively, to apply a preliminary write voltage between the first and second pixel electrodes. The write operation includes first and second operations in which the absolute value of the difference is smaller than the absolute value of the preliminary write voltage in the first and second signal lines included in each of the plurality of signal line groups within the selection period. 2. A liquid crystal display device comprising supplying two video signals, respectively. The method of claim 9, And the controller controls the operations of the scan line driver circuit and the signal line driver circuit so that the preliminary write operation and the write operation are executed in this order within each field period. The method of claim 9, The controller controls the operation of the scan line driver circuit and the signal line driver circuit so that a reset operation is performed prior to the preliminary write operation, The reset operation includes first and second signal lines in the first and second signal lines included in each of the plurality of signal line groups within a period during which the scan line driver circuit supplies the scan voltage to one of the plurality of scan lines. Supplying second reset signals, respectively, to apply first and second reset voltages between the first pixel electrode and the counter electrode and between the second pixel electrode and the counter electrode, respectively, The one reset voltage is equal to the voltage between the first pixel electrode and the counter electrode immediately after the preliminary writing operation and the voltage between the first pixel electrode and the counter electrode immediately after the writing operation is equal to the absolute value. Or greater than and the second reset voltage is a voltage between the second pixel electrode and the counter electrode immediately after the preliminary write operation and immediately after the write operation. And a voltage and an absolute value between the second pixel electrode and the counter electrode in the same or greater value. The method of claim 11, The controller is configured to perform the reset operation in the first field period and the scan line driver circuit and the signal line so that the preliminary write operation and the write operation are executed in this order within a second field period following the first field period. The liquid crystal display device which controls the operation | movement of a drive circuit. The method of claim 11, And the controller controls operations of the scan line driver circuit and the signal line driver circuit so that the reset operation, the preliminary write operation, and the write operation are executed in this order within each field period. An array substrate including a first insulating substrate, a plurality of pixel circuits each including first and second pixel electrodes facing the first insulating substrate, and the first insulating substrate having the plurality of pixel circuits interposed therebetween; A liquid crystal having a second insulating substrate facing each other, an opposite substrate including a counter electrode supported on the second insulating substrate and facing the plurality of pixel circuits, and a liquid crystal layer interposed between the array substrate and the opposite substrate; As a driving method of a display device, Selecting the plurality of pixel circuits one by one or per row; A preliminary write operation including supplying first and second preliminary write signals to the first and second pixel electrodes included in the selected pixel circuit, respectively, and applying a preliminary write voltage between the first and second pixel electrodes. To run, After the preliminary write operation, the first and second image electrodes included in the selected pixel circuit include first and second image signals having a smaller absolute value compared to an absolute value of the preliminary write voltage, respectively. A drive method comprising performing a write operation including supplying. The method of claim 14, The liquid crystal molecule contained in the said liquid crystal layer forms a bend orientation at the time of image display. The method of claim 14, And the write operation is executed in this order within each field period. The method of claim 14, Executing a reset operation prior to the preliminary write operation, The reset operation may be performed by supplying first and second reset signals to the first and second pixel electrodes included in the selected pixel circuit, respectively, between the first pixel electrode and the counter electrode and the second electrode. Applying first and second reset voltages between the pixel electrode and the counter electrode, respectively, wherein the first reset voltage is provided between the first pixel electrode and the counter electrode immediately after the preliminary write operation. A voltage and a voltage between the first pixel electrode and the counter electrode immediately after the write operation are equal to or greater than the absolute value, and the second reset voltage is the second pixel immediately after the preliminary write operation. The voltage between the electrode and the counter electrode and the voltage and absolute value between the second pixel electrode and the counter electrode immediately after the write operation are equal to or greater than Drive method to be used. The method of claim 17, And executing the reset operation in a first field period, and executing the preliminary write operation and the write operation in this order within a second field period following the first field period. The method of claim 17, And the reset operation, the preliminary write operation, and the write operation are executed in this order within each field period. The method of claim 18, And the reset operation, the preliminary write operation, and the write operation are executed in this order within each field period.