KR20090102623A - Output driving device - Google Patents

Abstract

PURPOSE: An output driving device controlling a slew rate of an output signal is provided to control an operation by not requiring an excessive transistor driving power for controlling a slew rate. CONSTITUTION: An output driving device includes a push pull type driver and a first body bias controller. A push pull type driver is comprised of a pull up PMOS transistor and a pull down NMOS transistor. An output driving device controls the body bias of the pull up PMOS transistor and the pull down NMOS transistor to control a slew rate. A first body bias controller controls the body bias of the pull up PMOS transistor. The first body bias controller controls the slew rate when the output signal is converted into low to high.

Description

Output Driving Device {OUTPUT DRIVING DEVICE}

The present invention relates to an output driving apparatus used in a semiconductor memory device, and more particularly, to an output driving apparatus capable of improving the slew rate of the output driving apparatus.

PUSH-PULL type drivers are widely used in buffers and driving amplifiers of semiconductor memory devices. In such a push pull type output driver, slew rate adjustment is very important.

Slew rate is the maximum change amount of the output voltage per unit time. For example, in the case of an output driving device with a gain of 1, in an ideal circuit, the input voltage immediately goes up from 0 volts to 1 volt, but in actual circuits, when the slew rate is K, the output voltage increases simultaneously along the input voltage. The slope function, which is not known, is inclined up to 1 volt. Therefore, it is very important to control the slew rate of the output driving device to match the product specifications.

1 illustrates an output driving apparatus of a general semiconductor memory device.

Looking at the output driving device shown, a pull-up PMOS transistor 101up and a pull-down NMOS transistor 101dn is provided.

In such an output driving device, a signal input to the input line 102 is inverted by the push-pull driving circuit and output to the output line 103.

2 shows a voltage waveform output from the output line 103 when the signal input through the input line 102 changes from a high state to a low state (the output is switched from low to high since the output is inverted). Indicates. In this case, if the size of the PMOS transistor 101up increases, the signal output from the output line 103 changes more rapidly from the low state to the high state.

3 illustrates a voltage waveform output from the output line 103 when the signal inputted through the input line 102 changes from a low state to a high state (in this case, the output is inverted and the low state is high). Switched to). In this case, if the size of the NMOS transistor 101dn is increased, the signal output through the output line 103 changes more rapidly from the high state to the low state.

That is, as can be seen from the above description, as the size of the pull-up PMOS transistor 101up and the pull-down NMOS transistor 101dn used in the output driving apparatus increases, the slew rate becomes larger.

Therefore, conventionally, as shown in Fig. 4, a slew rate control technique is introduced to configure the output driving apparatus.

The conventional output driving apparatus shown in the figure is composed of a pull-up driver 301up and a pull-down driver 301dn. The pull-up driver 301up and the pull-down driver 301dn comprise a plurality of transistors for slew rate control.

That is, the pull-up driving unit 301up includes the upper PMOS transistor group having the Pcode (0) to Pcode (1) as an input signal between the supply power supply VDD and the output line 103 and the input line 102. It consists of the PMOS transistor group of the lower stage which makes an input signal an input signal. The upper PMOS transistor group includes a PMOS transistor that connects a source terminal to a supply power supply VDD and inputs Pcode (0) to Pcode (1) to a gate terminal. It is composed. The PMOS transistor group at the lower end connects a source terminal to the drain terminal of the upper PMOS transistor, inputs an input signal of the input line 102 to the gate terminal, and connects the drain terminal to the output line 103. It consists of a transistor.

The pull-up driver 301up further includes a PMOS transistor for connecting a source terminal to a supply power supply VDD, a gate terminal to an input line 102, and an output line 103 to a drain terminal. do.

The pull-up driver 301up configured as described above is composed of a plurality of PMOS transistors for controlling the size of the pull-up PMOS transistor illustrated in FIG. 1 described above.

Similarly, the pull down driver 301dn is composed of a plurality of NMOS transistors.

In other words, the pull-down driving unit 301dn includes a lower NMOS transistor group having Ncode (0) to Ncode (1) as an input signal between the ground power supply VSS and the output line 103 and the input line 102. The upper input NMOS transistor group has an input signal as an input signal. The upper NMOS transistor group includes an NMOS transistor that connects a drain terminal to an output line and inputs a signal of an input line 102 to a gate terminal. The NMOS transistor group is configured by the amount of the Ncode signal. The lower NMOS transistor group connects the drain terminal to the source terminal of the upper NMOS transistor, inputs the Ncode (0) to Ncode (1) signals to the gate terminal, and connects the source terminal to the ground power supply (VSS). It is composed of an NMOS transistor.

The pull-down driver 301dn further includes an NMOS transistor for connecting a drain terminal to the output line 103, a gate terminal to the input line 102, and a ground power supply VSS to a source terminal. do.

The pull-down driver 301dn configured as described above is composed of a plurality of NMOS transistors for controlling the size of the pull-down NMOS transistor illustrated in FIG. 1 described above.

Therefore, the conventional output driving apparatus configured as described above has the effect of changing the size of the pull-up PMOS transistor shown in FIG. 1 by using the Pcode (0) and Pcode (1) signals. Similarly, the Ncode (0) and Ncode (1) signals are used to have the same effect as the size of the pull-down NMOS transistor shown in FIG.

That is, the pull-up driver 301up inputs a Pcode signal for adjusting the slew rate according to the product specification, and the corresponding upper PMOS transistor operates in response to the input Pcode signal. In addition, the PMOS transistor at the bottom operated by the input signal of the input line 102 is connected to the output line 103.

In addition, the pull-down driver 301dn inputs an Ncode signal for adjusting the slew rate according to the product specification, and a corresponding lower NMOS transistor operates in response to the input Ncode signal. In addition, a signal is output to the output line 103 while the upper NMOS transistor operated by the input signal of the input line 102 is linked together.

However, the driving power of the conventional output driving apparatus configured as described above should be set based on the largest size transistor since it should be configured to drive PMOS transistors and NMOS transistors of all sizes constituting the output driving apparatus. Because of this very inefficient characteristics. As a result, the conventional output driving apparatus generates the above problems due to the fact that the size of the transistor is used for adjusting the slew rate.

Accordingly, an object of the present invention is to provide an output driving apparatus capable of adjusting the slew rate of an output signal by adjusting a body bias of a transistor included in the output driving apparatus in order to solve the above problems.

An output driving apparatus according to the present invention for achieving the above object, in the device including a push-pull type drive unit consisting of a pull-up PMOS transistor and a pull-down NMOS transistor, the pull-up PMOS transistor and pull for adjusting the slew rate The body bias of the down NMOS transistor is adjusted.

That is, the present invention includes a first body bias adjuster for adjusting the body bias of the pull-up PMOS transistor, and when the output signal is switched from low to high, the slew rate adjustment is performed by the first body bias adjuster It is characterized by.

The present invention includes a second body bias control unit for adjusting the body bias of the pull-down NMOS transistor, and when the output signal is switched from high to low, performing the slew rate adjustment in the second body bias control unit It features.

The present invention is characterized by adjusting the body bias of the transistor used in the output driving device when there is a need to increase the slew rate. That is, when the NMOS transistor is used as a driving element, increasing the body bias of the NMOS transistor lowers the threshold voltage of the NMOS transistor. At this time, as the current flowing through the NMOS transistor increases, the effect is as if the size of the NMOS transistor is increased. Therefore, the present invention has the advantage that operation control can be performed very efficiently without requiring excessive transistor driving power for adjusting the slew rate.

1 is a block diagram of a general output driving device,

2 and 3 are waveform diagrams of output voltages of the output driving apparatus;

4 is a block diagram of an output driving device for adjusting the slew rate according to the prior art,

5 is a configuration diagram of an output driving device for adjusting the slew rate according to an embodiment of the present invention;

6 is a detailed block diagram of an output driving apparatus according to an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating in detail a circuit for generating a control signal input to a pull-up driving unit and a pull-down driving unit among components of an output driving apparatus according to the embodiment of the present invention shown in FIG.

FIG. 8 is a graph comparing the operation of the output driving apparatus according to the prior art illustrated in FIG. 4 with the operation of the output driving apparatus according to the embodiment of the present invention illustrated in FIG. 5.

Explanation of symbols on the main parts of the drawings

401up: pull-up driving unit 401dn; Pull-down drive

501up: NMOS transistor 501dn: PMOS transistor

102: input line 103: output line

Hereinafter, an output driving apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of an output driving apparatus according to the present invention.

As shown, in the output driving apparatus of the present invention, a pull-up driving unit 401up and a pull-down driving unit 401dn are configured between the input line 102 and the output line 103.

The pull-up driving unit 401up includes a PMOS transistor for connecting a source terminal to a supply power source, a gate terminal to the input line 102, and a drain terminal to an output line 103. And a bias adjuster for adjusting body bias.

In addition, the pull-down driver 401dn includes an NMOS transistor for connecting a source terminal to a ground power source, a gate terminal to the input line 102, and a drain terminal to an output line 103, and the NMOS transistor. And a bias adjuster for adjusting a body bias of the transistor.

According to the above configuration, the output driving apparatus of the present invention is driven as follows.

When the signal output to the output line 103 changes from a high state to a low state, if the slew rate needs to be increased, the body bias of the NMOS transistor of the pull-down driver 401dn is increased. This operation lowers the threshold voltage of the NMOS transistor, increases the current flowing through the NMOS transistor, and produces an effect as if the size of the NMOS transistor is increased.

In addition, when the signal output to the output line 103 changes from a low state to a high state, if it is necessary to increase the slew rate, the body bias of the PMOS transistor of the pull-up driver 401up is lowered. This operation lowers the threshold voltage of the PMOS transistor, increases the current flowing through the PMOS transistor, and produces an effect as if the size of the PMOS transistor is increased.

Next, Figure 6 shows a detailed configuration of the output driving apparatus according to an embodiment of the present invention.

In the illustrated embodiment, the bias control unit for controlling the slew rate of the output driving apparatus includes a resistor and one MOS transistor.

That is, the bias control unit of the pull-up driving unit 401up divides the potential level between the supply power supply VDD and the output line 103 at a ratio corresponding to the potential level of the control signal CONTROL_SIGNAL_up to distribute the distribution voltage DIV_VOL_up. And a body bias supply unit 405up for providing the divided voltage DIV_VOL_up as a body bias of the pull-up PMOS transistor.

Here, in the distribution voltage generator 403up, a resistor and an NMOS transistor 501up are connected in series between the supply power supply VDD and the output line 103, and between the resistor and the drain of the NMOS transistor 501up. The distribution voltage DIV_VOL_up is generated at the connection point.

The divided voltage DIV_VOL_up generated as described above may be connected to the body of the pull-up PMOS transistor by the body bias supply unit 405up, and may supply the divided voltage DIV_VOL_up as a body bias voltage of the pull-up PMOS transistor.

In this case, a control signal CONTROL_SIGNAL_up is applied to the gate terminal of the NMOS transistor 501up, a source terminal is connected to the output line 103, and a drain terminal is connected to a supply power supply VDD terminal.

The bias control unit of the pull-down driving unit 401dn divides the potential level between the output line 103 and the ground voltage VSS at a ratio corresponding to the potential level of the control signal CONTROL_SIGNAL_dn to generate the distribution voltage DIV_VOL_dn. And a body bias supply unit 405dn for providing the divided voltage DIV_VOL_dn as the body bias of the pull-down NMOS transistor.

Here, in the distribution voltage generator 403dn, a PMOS transistor 501dn and a resistor are connected in series between the output line 103 and the ground voltage VSS, and between the drain and the resistor of the PMOS transistor 501dn. The distribution voltage DIV_VOL_dn is generated at the connection point.

The divided voltage DIV_VOL_dn generated in this manner may be connected to the body of the pull-down NMOS transistor by the body bias supply unit 405dn to supply the divided voltage DIV_VOL_dn as the body bias voltage of the pull-down NMOS transistor.

At this time, the control signal CONTROL_SIGNAL_dn is applied to the gate terminal of the PMOS transistor 501dn, the source terminal is connected to the output line 103, and the drain terminal is connected to the ground power supply VSS terminal.

FIG. 7 is a circuit diagram illustrating in detail a circuit for generating a control signal input to a pull-up driving unit and a pull-down driving unit among components of an output driving apparatus according to an embodiment of the present invention shown in FIG. 6.

Referring to FIG. 7, the components of the output driving apparatus shown in FIG. 6 are input to the body bias control unit of the pull-up driving unit 401up and the body bias control unit of the pull-down driving unit 401dn. The circuit for generating the control signals CONTROL_SIGNAL_up and CONTROL_SIGNAL_dn responds to the control signals CONTROL_SIGNAL_up and CONTROL_SIGNAL_dn in response to the test code TEST_CODE <0: 5>, which consists of a plurality of bits applied from the outside through a predetermined pad in the test mode operation. Control the potential level of the control signal (CONTROL_SIGNAL_up, CONTROL_SIGNAL_dn) in response to the potential level control code (CV_CODE <0: 5>) consisting of a number of bits defined in the Mode Register Set (MRS) in normal mode operation. It can be seen that the potential level of) is adjusted.

In detail, the circuit generating the control signals CONTROL_SIGNAL_up and CONTROL_SIGNAL_dn input to the body bias control unit of the pull-up driving unit 401up and the body bias control unit of the pull-down driving unit 401dn includes a test code TEST_CODE <0: 5>. ) Or the greater the value of the potential level control code (CV_CODE <0: 5>), the greater the magnitude of the current provided from the supply voltage (VDD) than the magnitude of the current flowing out of the ground voltage (VSS). , The potential level of CONTROL_SIGNAL_dn is increased, and the smaller the value of the test code (TEST_CODE <0: 5>) or the potential level control code (CV_CODE <0: 5>), the more the current provided from the supply voltage (VDD) stage. It can be seen that the potential level of the control signals CONTROL_SIGNAL_up and CONTROL_SIGNAL_dn is lowered by increasing the amount of current flowing out to the ground voltage VSS terminal rather than.

In the output driving apparatus according to the present invention configured as described above, the slew rate control is performed as follows.

When the signal output to the output line 103 changes from a high state to a low state, if the slew rate needs to be increased, the body bias of the NMOS transistor of the pull-down driver 401dn is increased. In the case of the NMOS transistor, when the body bias (bulk voltage) is increased, that is, when the potential level of the divided voltage DIV_VOL_dn generated by the divided voltage generator 403dn among the components of the pull-down driver 401dn is increased, This is because the threshold voltage is lowered.

At this time, the potential level of the distribution voltage DIV_VOL_dn varies depending on how much the PMOS transistor 501dn included in the distribution voltage generator 403dn among the components of the pull-down driver 401dn is turned on.

That is, when the potential level of the control signal CONTROL_SIGNAL_dn applied to the gate terminal of the PMOS transistor 501dn is relatively increased, the output line 103 connected to the source terminal is connected to the body of the pull-down NMOS transistor connected to the drain terminal. The magnitude of the flowing current becomes relatively small, and accordingly, the potential level of the distribution voltage DIV_VOL_dn is relatively reduced.

On the other hand, when the potential level of the control signal CONTROL_SIGNAL_dn applied to the gate terminal of the PMOS transistor 501dn is relatively lowered, the output line 103 connected to the source terminal is transferred to the body of the pull-down NMOS transistor connected to the drain terminal. The magnitude of the flowing current becomes relatively large, and accordingly, the potential level of the distribution voltage DIV_VOL_dn is relatively increased.

Therefore, when the signal output to the output line 103 is changed from the high state to the low state, if the slew rate needs to be increased, the potential level of the control signal CONTROL_SIGNAL_dn is relatively lowered. As a result, the PMOS transistor 501dn is turned on relatively much, thereby increasing the body bias of the NMOS transistor, thereby lowering the threshold voltage of the pull-down NMOS transistor. This means that the magnitude of the current flowing through the pull-down NMOS transistor increases, so that the effect is the same as that of the pull-down NMOS transistor, and when the signal output to the output line 103 changes from the high state to the low state, The flow rate can be high.

On the contrary, when the signal output to the output line 103 changes from the high state to the low state, if the slew rate needs to be lowered, the potential level of the control signal CONTROL_SIGNAL_dn is relatively increased. As a result, the PMOS transistor 501dn is relatively turned on, thereby reducing the body bias of the NMOS transistor, thereby increasing the threshold voltage of the pull-down NMOS transistor. This means that the current flowing through the pull-down NMOS transistor is reduced, so that the effect is the same as the size of the pull-down NMOS transistor is reduced, and when the signal output to the output line 103 changes from the high state to the low state, The flow rate can be lowered.

When the signal output to the output line 103 changes from a low state to a high state, if the slew rate needs to be increased, the body bias of the pull-up PMOS transistor of the pull-up driver 401up is lowered. In the case of the pull-up PMOS transistor, when the body bias (bulk voltage) is lowered, that is, the potential level of the divided voltage DIV_VOL_up generated by the distribution voltage generator 403up among the components of the pull-up driver 401up is lowered. This is because the threshold voltage is lowered.

At this time, the potential level of the distribution voltage DIV_VOL_up varies depending on how much the NMOS transistor 501up included in the distribution voltage generator 403up among the components of the pull-up driver 401up is turned on.

That is, when the potential level of the control signal CONTROL_SIGNAL_up applied to the gate terminal of the NMOS transistor 501up is relatively lowered, the body of the pull-down NMOS transistor connected to the drain terminal is connected to the output line 103 connected to the source terminal. The magnitude of the flowing current becomes relatively small, thereby increasing the potential level of the distribution voltage DIV_VOL_up relatively.

On the other hand, when the potential level of the control signal CONTROL_SIGNAL_up applied to the gate terminal of the NMOS transistor 501up is relatively increased, the body of the pull-down NMOS transistor connected to the drain terminal is connected to the output line 103 connected to the source terminal. The magnitude of the flowing current becomes relatively large, whereby the potential level of the distribution voltage DIV_VOL_up is relatively reduced.

Therefore, when the signal output to the output line 103 changes from the low state to the high state, if it is necessary to increase the slew rate, the potential level of the control signal CONTROL_SIGNAL_up is relatively increased. As a result, the NMOS transistor 501up is turned on relatively much, thereby reducing the body bias of the pull-up PMOS transistor and lowering the threshold voltage of the pull-up PMOS transistor. This means that the magnitude of the current flowing through the pull-up PMOS transistor increases, so that the effect is the same as that of the pull-up PMOS transistor, and when the signal output to the output line 103 changes from a low state to a high state, The flow rate can be high.

On the contrary, when the signal output to the output line 103 changes from the low state to the high state, if the slew rate needs to be lowered, the potential level of the control signal CONTROL_SIGNAL_up is relatively lowered. As a result, the NMOS transistor 501up is turned on relatively little, thereby increasing the body bias of the pull-up PMOS transistor, thereby increasing the threshold voltage of the pull-up PMOS transistor. This means that the current flowing through the pull-up PMOS transistor is reduced, so that the effect is the same as that of the pull-up PMOS transistor is reduced. When the signal output to the output line 103 changes from the low state to the high state, The flow rate can be lowered.

FIG. 8 is a graph illustrating the operation of the output driving apparatus according to the prior art illustrated in FIG. 4 and the operation of the output driving apparatus according to the embodiment of the present invention illustrated in FIG. 5.

Referring to FIG. 8, the operation of the output driving apparatus according to the related art illustrated in FIG. 4 may be performed when the threshold voltage (VT) level of the MOS transistor—a pull-up PMOS transistor and a pull-down NMOS transistor—is fixed. It can be seen that the current amount of the MOS transistor changes with the increase.

In addition, the operation of the output driving apparatus according to the embodiment of the present invention shown in FIG. It can be seen that the threshold voltage VT is in a state of fluctuation (VT1 <-> VT0 <-> VT2).

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to adjusting the body bias of the transistor to control the slew rate improvement in the output driving circuit. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

As an example, the embodiment of the present invention is described by applying a configuration for improving the slew rate to the portion corresponding to the main driver in the output driving device. However, the present invention is not limited thereto. For example, the present invention may also be applied to a sub-driver in front of the main driver.

Claims (14)

In a device including a push-pull type driver consisting of a pull-up PMOS transistor and a pull-down NMOS transistor, an output driving method comprising adjusting body biases of the pull-up PMOS transistor and the pull-down NMOS transistor for slew rate adjustment. Device. The method of claim 1, Further comprising a first body bias control unit for adjusting the body bias of the pull-up PMOS transistor, And when the output signal is switched from low to high, the slew rate adjustment is performed by the first body bias adjuster. The method of claim 2, And the first body bias adjuster lowers the body bias of the pull-up PMOS transistor when the slew rate is increased, and increases the body bias of the pull-up PMOS transistor when the slew rate is decreased. The method of claim 3, wherein The first body bias adjuster may include a resistor and a switch connected between a power supply and an output node, and a voltage determined according to whether the switch is operated is provided as a body bias of the pull-up PMOS transistor. Device. The method of claim 3, The first body bias adjustment unit, A distribution voltage generator for generating a distribution voltage by distributing a potential level between a supply power supply and an output node at a ratio corresponding to the potential level of the control signal; And And a body bias supply for providing the divided voltage to the body bias of the pull-up PMOS transistor. The method of claim 5, The first body bias adjustment unit, And a potential level of the control signal in response to a test code consisting of a plurality of bits applied from the outside through a predetermined pad during a test mode operation. The method of claim 6, The first body bias adjustment unit, And a potential level of the control signal in response to a potential level control code consisting of a plurality of bits defined in a mode register set during normal mode operation. The method of claim 1, A second body bias control unit for adjusting the body bias of the pull-down NMOS transistor further, And when the output signal is switched from high to low, the slew rate adjustment is performed by the second body bias adjuster. The method of claim 8, And the second body bias adjuster increases the body bias of the pull-down NMOS transistor when the slew rate is increased, and lowers the body bias of the pull-down PMOS transistor when the slew rate is decreased. The method of claim 9, The second body bias adjuster may include a resistor and a switch connected between an output node and a ground power supply, and a voltage determined according to whether the switch is operated is provided as a body bias of a pull-down NMOS transistor. . The method of claim 9, The second body bias adjusting unit, A distribution voltage generator for generating a distribution voltage by distributing a potential level between the output node and the ground voltage at a ratio corresponding to the potential level of the control signal; And And a body bias supply for providing the divided voltage to the body bias of the pull-down NMOS transistor. The method of claim 11, The second body bias adjusting unit, And a potential level of the control signal in response to a test code consisting of a plurality of bits applied from the outside through a predetermined pad during a test mode operation. The method of claim 12, The second body bias adjusting unit, And a potential level of the control signal in response to a potential level control code consisting of a plurality of bits defined in a mode register set during normal mode operation. The method according to claim 4 or 10, And said switch comprises a MOS transistor.