KR20090102074A - Method for forming a pattern in semiconductor device - Google Patents
Method for forming a pattern in semiconductor deviceInfo
- Publication number
- KR20090102074A KR20090102074A KR1020080027311A KR20080027311A KR20090102074A KR 20090102074 A KR20090102074 A KR 20090102074A KR 1020080027311 A KR1020080027311 A KR 1020080027311A KR 20080027311 A KR20080027311 A KR 20080027311A KR 20090102074 A KR20090102074 A KR 20090102074A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- hard mask
- layer
- forming
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000011651 chromium Substances 0.000 claims description 6
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000007261 regionalization Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 229910003481 amorphous carbon Inorganic materials 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000003667 anti-reflective effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002835 absorbance Methods 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000003431 cross linking reagent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 패턴 형성 방법에 관한 것이다. 특히, 유기 반사방지막과 하드마스크의 역할을 동시에 하는 물질을 이용하여 하드마스크층을 형성하는 방법에 관한 것이다. The present invention relates to a method of forming a pattern of a semiconductor device. In particular, the present invention relates to a method of forming a hard mask layer using a material that simultaneously serves as an organic antireflection film and a hard mask.
반도체 소자 제조 공정 중 리소그라피(Lithography)용 포토레지스트 패턴 형성 공정에 사용되는 유기 반사방지층 (BARC; Bottom Anti-Reflective Coating)은 하부층으로부터의 난반사를 방지하고 포토레지스트 자체의 두께 변화에 의한 정재파를 제거하여 포토레지스트의 두께 균일도를 증가시키는 반사방지층의 역할을 수행해왔다.The bottom anti-reflective coating (BARC) used in the photoresist pattern forming process for lithography in the semiconductor device manufacturing process prevents diffuse reflection from the bottom layer and removes standing waves due to the thickness change of the photoresist itself. It has served as an antireflective layer to increase the thickness uniformity of the photoresist.
한편, 소자가 점점 미세화되어감에 따라, 포토레지스트 패턴의 쓰러짐을 방지하기 위해 포토레지스트층의 두께 또한 급속히 줄어들고 있다.On the other hand, as the device becomes finer, the thickness of the photoresist layer is also rapidly decreasing to prevent the photoresist pattern from falling down.
이에 따라 포토레지스트 패턴을 식각 마스크로 이용하여 유기 반사방지층을 식각할 때 식각 속도를 증가시켜 유기 반사방지층이 쉽게 제거될 수 있도록 하기 위해, 다양한 유기 반사방지층용 중합체 및 가교제가 개발되어 왔다.Accordingly, a variety of polymers and crosslinking agents for organic antireflective layers have been developed to increase the etch rate when the organic antireflective layer is etched using the photoresist pattern as an etch mask so that the organic antireflective layer can be easily removed.
그럼에도 불구하고, 종래에는 포토리소그래피 공정 시 하드마스크의 식각 선택비 문제를 고려하여 피식각층 상부에 비정질 탄소막 하드마스크층 및 상기 비정질 탄소 하드마스크층에 대하여 바람직한 식각 선택비를 갖는 실리콘 산화질화막 하드마스크층, 유기 반사방지막 및 포토레지스트 패턴이 순차적으로 형성되는 복잡한 다층 구조를 이룰 수밖에 없다.Nevertheless, the silicon oxynitride hardmask layer having a preferred etching selectivity with respect to the amorphous carbon film hardmask layer and the amorphous carbon hardmask layer on the etching layer in consideration of the etching selectivity problem of the hard mask in the conventional photolithography process. In addition, the organic anti-reflection film and the photoresist pattern may form a complicated multilayer structure in which a sequence is formed.
도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 패턴 형성 방법을 도시한 단면도이다. 1A and 1B are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art.
도 1a을 참조하면, 반도체 기판(100)에 피식각층(110), 비정질 탄소막(Amorphous Carbon)(120), 실리콘 산화질화막(SiON)(130) 및 유기 반사방지막(140)을 순차적으로 형성한다. Referring to FIG. 1A, an etched layer 110, an amorphous carbon film 120, a silicon oxynitride layer 130, and an organic antireflection film 140 are sequentially formed on the semiconductor substrate 100.
다음에, 유기 반사방지막(140) 상부에 포토레지스트(Photoresist)를 도포하고, 상기 포토레지스트에 대한 노광 및 현상 공정으로 포토레지스트 패턴(150)을 형성한다. Next, a photoresist is applied on the organic antireflection film 140, and a photoresist pattern 150 is formed by an exposure and development process of the photoresist.
이때, 종래의 유기 반사방지막(140)만으로 충분한 반사율 방지가 어려우며, 포토레지스트 패턴(130)을 제거하는 공정 시 비정질 탄소막(120)에도 영향을 미치게 된다. 그러므로, 유기 반사방지막(140) 및 비정질 탄소막(120) 사이에 실리콘 산화질화막(130)을 추가적으로 형성하는 것이 바람직하다.In this case, it is difficult to prevent sufficient reflectance only with the conventional organic antireflection film 140, and also affect the amorphous carbon film 120 during the process of removing the photoresist pattern 130. Therefore, it is preferable to further form the silicon oxynitride film 130 between the organic antireflection film 140 and the amorphous carbon film 120.
도 1b를 참조하면, 포토레지스트 패턴(150)을 마스크로 유기 반사방지막(140), 실리콘 산화질화막(130) 및 비정질 탄소막(120)을 순차적으로 식각하여 마스크 패턴(미도시)을 형성한다.Referring to FIG. 1B, a mask pattern (not shown) may be formed by sequentially etching the organic antireflection film 140, the silicon oxynitride film 130, and the amorphous carbon film 120 using the photoresist pattern 150 as a mask.
다음에, 포토레지스트 패턴(150)을 제거하고, 상기 마스크 패턴(미도시)을 마스크로 피식각층(110)을 식각한 후 상기 마스크 패턴(미도시)을 제거하여 최종 패턴(110a)을 형성한다. Next, the photoresist pattern 150 is removed, the etched layer 110 is etched using the mask pattern (not shown) as a mask, and the mask pattern (not shown) is removed to form a final pattern 110a. .
상술한 종래 기술에 따른 반도체 소자의 패턴 형성 방법은 구현해야 할 패턴이 미세화되면서, 하드마스크는 비정질 탄소막, 실리콘 산화질화막 및 유기 반사방지막의 다층 구조를 이룰 수밖에 없게 된다. 따라서, 다층 구조를 형성하게 되면, 공정이 복잡해지며, 상기 하드마스크의 재료를 선정하는데 어려움이 있게되므로 소자의 특성이 저하되는 문제가 있다. As the pattern formation method of the semiconductor device according to the prior art described above is miniaturized, the hard mask may have a multilayer structure of an amorphous carbon film, a silicon oxynitride film, and an organic antireflection film. Therefore, when the multilayer structure is formed, the process becomes complicated, and it is difficult to select the material of the hard mask, thereby deteriorating the characteristics of the device.
본 발명은 EUV 광원을 이용한 미세 패턴 형성 공정 시 기존의 유기 반사방지막, 비정질 탄소막 및 실리콘 산화질화막의 다층 구조를 대체할 수 있는 하드마스크를 형성하여 공정을 단순화시키고, 공정 비용을 절감시켜 소자 제조 효율을 향상시키는 반도체 소자의 패턴 형성 방법을 제공하는 것을 목적으로 한다. The present invention forms a hard mask that can replace the multilayer structure of the conventional organic anti-reflection film, amorphous carbon film, and silicon oxynitride film during the fine pattern forming process using the EUV light source, simplifying the process, reducing the process cost, and device manufacturing efficiency It is an object of the present invention to provide a method for forming a pattern of a semiconductor device that improves the resistance.
본 발명에 따른 반도체 소자의 패턴 형성 방법은 The method of forming a pattern of a semiconductor device according to the present invention
반도체 기판 상부에 피식각층을 형성하는 단계와,Forming an etched layer on the semiconductor substrate;
상기 피식각층 상부에 탄탈륨 및 탄소를 포함하는 하드마스크층을 형성하는 단계와,Forming a hard mask layer including tantalum and carbon on the etched layer;
상기 하드마스크층 상부에 포토레지스트 패턴을 형성하는 단계와,Forming a photoresist pattern on the hard mask layer;
상기 포토레지스트 패턴을 마스크로 상기 하드마스크층을 식각하여 하드마스크 패턴을 형성하는 단계와,Etching the hard mask layer using the photoresist pattern as a mask to form a hard mask pattern;
상기 하드마스크 패턴을 마스크로 상기 피식각층을 식각하여 최종 패턴을 형성하는 단계를 포함하는 것을 특징으로 하고,And etching the layer to be etched using the hard mask pattern as a mask to form a final pattern.
상기 하드마스크층은 TaC, TaCN 및 이들의 조합 중 선택된 어느 하나로 형성하는 것과,The hard mask layer is formed of any one selected from TaC, TaCN, and combinations thereof,
상기 하드마스크층은 알루미늄(Al), 크롬(Cr) 또는 텅스텐(W) 중 어느 하나를 포함하여 형성하는 것과,The hard mask layer is formed by containing any one of aluminum (Al), chromium (Cr) or tungsten (W),
상기 하드마스크층은 CVD 방식으로 증착하는 것과, The hard mask layer is deposited by CVD,
상기 하드마스크층을 식각하는 공정은 BCl3와 N2O2의 혼합 가스 또는 Cl2를 이용한 건식 식각인 것과,The process of etching the hard mask layer is a dry etching using a mixed gas or Cl 2 of BCl 3 and N 2 O 2 ,
상기 하드마스크층을 식각하는 공정은 BOE 또는 03 용액을 이용한 습식 식각인 것과,The process of etching the hard mask layer is a wet etching using a BOE or 0 3 solution,
상기 포토레지스트 패턴 형성 공정은 EUV(Extreme Ultra Violet) 광원을 이용하여 진행하는 것을 특징으로 한다. The photoresist pattern forming process may be performed using an extreme ultra violet (EUV) light source.
본 발명에 따른 반도체 소자의 패턴 형성 방법은 유기 반시방지막 및 하드마스크의 역할을 동시에 할 수 있도록 탄탈륨 및 실리콘 산화질화막을 포함하는 하드마스크층을 형성함으로써, 공정을 단순화시키고 원가를 절감시켜 소자의 수율이 향상되는 효과가 있다. In the method of forming a semiconductor device according to the present invention, a hard mask layer including tantalum and silicon oxynitride film is formed to simultaneously serve as an organic anti-reflective film and a hard mask, thereby simplifying a process and reducing costs, thereby yielding device yields. This has the effect of being improved.
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 패턴 형성 방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 패턴 형성 방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
200 : 반도체 기판 210 : 피식각층200 semiconductor substrate 210 etched layer
220 : 하드마스크층 230 : 감광막 패턴220: hard mask layer 230: photosensitive film pattern
220a : 하드마스크 패턴 210a : 최종 패턴220a: hard mask pattern 210a: final pattern
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 패턴 형성 방법을 도시한 것이다. 2A to 2C illustrate a method of forming a pattern of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 기판(200) 상부에 피식각층(210) 및 하드마스크층(220)을 순차적으로 형성하고, 하드마스크층(220) 상부에 포토레지스트(미도시)를 도포한다. Referring to FIG. 2A, the etched layer 210 and the hard mask layer 220 are sequentially formed on the semiconductor substrate 200, and a photoresist (not shown) is applied on the hard mask layer 220.
여기서, 하드마스크층(220)은 탄탈륨(Ta) 및 탄소(Carbon)를 포함하는 물질로 형성하는 것이 바람직하다. 예를 들어, TaC, TaCN 및 이들의 조합 중 선택된 어느 하나로 형성할 수 있다. Here, the hard mask layer 220 is preferably formed of a material containing tantalum (Ta) and carbon (Carbon). For example, it may be formed of any one selected from TaC, TaCN, and a combination thereof.
이때, 상기 TaCN은 굴절율(n)이 1.8 이며, 흡수율(k)은 0.3 이하로 조절이 가능하여 유기 반사방지막(Bottom Anti-Reflective Material)의 역할을 할 수 있다. In this case, the TaCN has a refractive index n of 1.8 and an absorbance k of 0.3 can be adjusted to 0.3 or less, thereby serving as an organic anti-reflective material.
그리고, 상기 TaCN은 CVD(Chemical Vapor Deposition) 방식을 이용하여 증착하는 것이 바람직하다.In addition, the TaCN is preferably deposited using CVD (Chemical Vapor Deposition) method.
또한, 하드마스크층(220)은 알루미늄(Al), 크롬(Cr) 또는 텅스텐(W) 중 어느 하나를 포함하여 형성할 수도 있다.In addition, the hard mask layer 220 may include any one of aluminum (Al), chromium (Cr), or tungsten (W).
다음에, 상기 포토레지스트(미도시)에 대해 노광 및 현상 공정을 수행하여 포토레지스트 패턴(230)을 형성한다.Next, the photoresist pattern 230 is formed by performing exposure and development processes on the photoresist (not shown).
여기서, 상기 노광 공정은 주로 EUV(Extreme Ultra Violet) 광원을 사용하나, KrF, ArF, VUV, E-빔, X-선 또는 이온빔을 사용하여 진행할 수도 있다.Here, the exposure process mainly uses an EUV (Extreme Ultra Violet) light source, but may be performed using KrF, ArF, VUV, E-beam, X-ray or ion beam.
도 2b를 참조하면, 포토레지스트 패턴(230)을 마스크로 하드마스크층(220)을 식각하여 하드마스크 패턴(220a)을 형성한다. Referring to FIG. 2B, the hard mask layer 220 is etched using the photoresist pattern 230 as a mask to form the hard mask pattern 220a.
여기서, 하드마스크 패턴(220a) 형성을 위한 식각 공정은 Cl2 또는 BCl3와 N2O2의 혼합 가스를 이용한 건식 식각(Dry Etch)으로 진행하거나, BOE(Buffered Oxide Etchant) 또는 03를 이용한 습식 식각(Wet Etch)으로 진행하는 것이 바람직하다.The etching process for forming the hard mask pattern 220a may be performed by dry etching using a mixture gas of Cl 2 or BCl 3 and N 2 O 2 , or using a buffered oxide etchant (BOE) or 0 3 . It is preferable to proceed with wet etching.
다음에, 포토레지스트 패턴(230)을 제거한다. Next, the photoresist pattern 230 is removed.
도 2c를 참조하면, 하드마스크 패턴(220a)을 마스크로 피식각층(210)을 식각한 후 하드마스크 패턴(220a)을 제거하고 최종 패턴(210a)을 형성한다.Referring to FIG. 2C, after etching the etched layer 210 using the hard mask pattern 220a as a mask, the hard mask pattern 220a is removed to form a final pattern 210a.
상기와 같이 탄탈륨(Ta) 및 탄소(Carbon)을 포함하는 물질로 하드마스크층을 형성함으로써, 하나의 층으로 유기 반사방지막 및 하드마스크의 역할을 동시에 할 수 있도록 한다.By forming a hard mask layer made of a material containing tantalum (Ta) and carbon as described above, it is possible to simultaneously serve as an organic antireflection film and a hard mask as one layer.
Claims (7)
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| CN104445049A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | MEMS device forming method |
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