KR20090100677A - Nonvolatile memory device selecting dummy word lines and method for operating the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device selecting dummy word lines is provided to improve an operation performance and/or yield by reducing the difference between the threshold voltage of memory cells adjacent to selection lines and the threshold voltage of the memory cells which are not adjacent to the selection lines. CONSTITUTION: A nonvolatile memory device(200) selecting dummy word lines includes a memory cell array, a plurality of word lines, and a dummy word line selecting circuit. The plurality of word lines are connected to the memory cell array. The dummy word line selecting circuit is connected to the memory cell array through the plurality of word lines. The dummy word line selecting circuit selects one of the plurality of word lines or more as the dummy word lines.

Description

A nonvolatile memory device for selecting dummy word lines and a method of operating the same.

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device for selecting dummy word lines and a method of operating the same.

A semiconductor memory device is a memory device that stores data and can be read out when needed. The semiconductor memory device may be largely divided into a random access memory (RAM) and a read only memory (ROM). RAM is a volatile memory device in which stored data is lost when power is lost. ROM is a nonvolatile memory device that does not destroy stored data even when its power supply is cut off. RAM includes Dynamic RAM (DRAM), Static RAM (SRAM), and the like. The ROM includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a flash memory device, and the like. Flash memory devices are classified into NOR type and NAND type. NAND flash memory devices have a higher density than Noah flash memory devices.

Due to an error in the manufacturing process, the threshold voltage distributions of the memory cells adjacent to the string selection line and the ground selection line may appear differently than the threshold voltage distributions of the memory cells not adjacent to the selection lines. The difference between the threshold voltages of the memory cells adjacent to the selection lines and the threshold voltages of the memory cells not adjacent to the selection lines is one of the causes of deterioration in the operating performance and / or yield of the memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having improved operating performance and / or yield by reducing a difference between threshold voltages of memory cells adjacent to select lines and threshold voltages of memory cells not adjacent to select lines. There is.

A nonvolatile memory device according to the present invention includes a memory cell array; A plurality of word lines connected to the memory cell array; And a dummy word line selection circuit connected to the memory cell array through the plurality of word lines, wherein the dummy word line selection circuit selects one or more of the plurality of word lines as dummy word lines. It is characterized by.

In example embodiments, the memory cell array may include cell strings having a plurality of memory cells each connected to the plurality of word lines; String select transistors connected to a string select line and respectively connected between the cell strings and the bit lines; And ground select transistors connected to the ground select line and connected between the cell strings and the common source line, respectively. The dummy word line selection circuit selects a word line adjacent to the ground selection line or the string selection line among the plurality of word lines as a dummy word line. The dummy word line selection circuit may include memory cells having a threshold voltage distribution indicating a relatively large difference from a threshold voltage distribution of memory cells not adjacent to the selection lines among memory cells adjacent to the string selection line and the ground selection line. The connected word line is selected as the dummy word line.

In an embodiment, the dummy word line selection circuit selects one or more word lines adjacent to the string select line and one or more word lines adjacent to the ground select line as the dummy word lines. The number of dummy word lines adjacent to the string select line and the number of dummy word lines adjacent to the ground select line are different.

A nonvolatile memory device according to the present invention includes a memory cell array consisting of a plurality of memory blocks; A plurality of word lines connected to each of the plurality of memory blocks; And a dummy word line selection circuit connected to each of the plurality of memory blocks through the plurality of word lines, wherein the dummy word line selection circuit is one of the plurality of word lines of each of the plurality of memory blocks. Alternatively, more than the dummy word lines are selected, and the selection of the dummy word lines of each of the plurality of memory blocks is independently performed.

In example embodiments, the dummy word line selection circuit may be connected to each of the memory blocks, and configured to select the one or more of the plurality of word lines of each of the memory blocks as dummy word lines. Dummy word line selectors. And a storage circuit configured to store dummy selection information for selecting the one or more of the plurality of word lines of each of the plurality of memory blocks as dummy word lines. The storage circuit includes a plurality of fuses respectively corresponding to the plurality of memory blocks, and the dummy selection information is stored in the storage circuit through cutting of the plurality of fuses. The dummy word line selection circuit further includes an address comparison circuit, wherein the address comparison circuit receives a block address from an external device, and receives information indicating whether a fuse corresponding to the transferred block address is cut out of the dummy selection information. The dummy word line selector is transferred to a dummy word line selector corresponding to the transferred block address.

In example embodiments, the dummy selection information may be stored in the memory cell array, and each of the plurality of dummy word line selectors may include a latch. When the nonvolatile memory device is powered on, the dummy selection information may include the plurality of dummy selection information. Are stored in latches of corresponding dummy word line selectors, respectively.

A method of operating a nonvolatile memory device including a plurality of memory blocks including a plurality of word lines includes receiving a block address for a read and / or write operation; And selecting one or more of the plurality of word lines of the memory block corresponding to the block address among the plurality of memory blocks as dummy word lines.

A memory system according to the present invention includes a nonvolatile memory device; And a memory controller configured to control an operation of the nonvolatile memory device, wherein the nonvolatile memory device comprises: a memory cell array; A plurality of word lines connected to the memory cell array; And a dummy word line selection circuit connected to the memory cell array through the plurality of word lines, wherein the dummy word line selection circuit selects one or more of the plurality of word lines as dummy word lines. It is characterized by.

According to the present invention, one or more of the plurality of word lines are selected as dummy word lines. Among the memory cells adjacent to the selection lines, word lines connected to memory cells having threshold voltages representing a relatively large difference compared to threshold voltage distributions of memory cells not adjacent to the selection lines are selected as dummy word lines. Thus, the threshold voltage distribution of the nonvolatile memory device is improved, and the yield is improved.

The nonvolatile memory device according to the present invention selects one or more of the plurality of word lines as dummy word lines. Among the memory cells adjacent to the selection lines, word lines connected to memory cells having threshold voltages representing a relatively large difference compared to threshold voltage distributions of memory cells not adjacent to the selection lines are selected as dummy word lines. Thus, the threshold voltage distribution of the nonvolatile memory device is improved, and the yield is improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For convenience of description, the present invention will be described in detail with reference to the NAND flash memory device. However, it will be understood that the nonvolatile memory and its operation method according to the present invention are not limited to the NAND flash memory device.

1 is a block diagram illustrating a flash memory device 400. Referring to FIG. 1, a flash memory device 400 includes a memory cell array 410, a read / write circuit 420, a row decoder 430, and a control logic 440.

The memory cell array 410 is connected to the read / write circuit 420 through bit lines BL and to the row decoder 430 through word lines WL. The memory cell array 410 includes strings of a plurality of memory cells MC. String select transistors SST are respectively provided between the strings and the bit lines of the memory cells MC. Ground select transistors GST are respectively provided between the strings of the memory cells MC and the common source line CSL. The memory cells MC are connected to the corresponding word lines WL1 ˜WLm, the string select transistors SST are connected to the string select line SSL, and the ground select transistors GST are connected to the ground select line ( GSL).

The read / write circuit 420 is connected to the memory cell array 410 and the control logic 440. The read / write circuit 420 operates under the control of the control logic 440. The read / write circuit 420 exchanges data DATA with an external device. The read / write circuit 420 writes data to or reads data from the memory cells MC through the bit lines BL.

The row decoder 430 is connected to the memory cell array 430 and the control logic 440. The row decoder 430 operates under the control of the control logic 440. The row decoder 430 receives the address ADDR from the outside, and selects word lines WL of the memory cell array 410 in response to the address ADDR.

The control logic 440 controls the overall operation of the flash memory device 400. The control logic 440 may operate in response to a control signal CTRL transmitted from the outside. In exemplary embodiments, the control signal CTRL may be provided from a memory controller (not shown).

2 is a diagram illustrating a threshold voltage distribution of memory cells MC of the flash memory device 400 of FIG. 1. In FIG. 2, the horizontal axis represents voltage and the vertical axis represents the number of memory cells.

Referring to FIGS. 1 and 2, curve A may represent a threshold voltage distribution of memory cells that are not adjacent to the selection lines SSL and GSL. Curve B may represent a threshold voltage distribution of memory cells connected to the word line WLm adjacent to the string select line SSL. Curve C will represent a threshold voltage distribution of memory cells connected to word line WL1 adjacent to ground select line GSL.

As shown in FIG. 2, due to a process error, the threshold voltage distributions of the memory cells adjacent to the selection lines SSL and GSL may be different from those of the memory cells not adjacent to the selection lines SSL and GSL. Will appear differently. Therefore, when the word lines WL1 and WLm connected to the memory cells adjacent to the selection lines SSL and GSL are selected as dummy word lines, the threshold voltage distribution of the flash memory device 400 may be improved.

In FIG. 2, the threshold voltage distribution C of the memory cells adjacent to the ground selection line GSL is compared to the threshold voltage distribution A of the memory cells not adjacent to the selection lines SSL and GSL. The difference will be greater than the threshold voltage distribution B of the memory cells adjacent to SSL. That is, when one word line of the plurality of word lines WL1 to WLm is selected as the dummy word line, the word line WL1 connected to the memory cells adjacent to the ground select line GSL is selected as the dummy word line. The threshold voltage distribution will be improved than when the word line WLm connected to the memory cells adjacent to the string select line SSL is selected as the dummy word lines.

The memory cell array 410 of the flash memory device 400 is composed of a plurality of memory blocks. In FIG. 1, one memory block of the plurality of memory blocks is shown. Threshold voltage distributions of each of the plurality of memory blocks will appear differently. For example, as shown in FIG. 2, compared to memory cells not adjacent to the selection lines SSL and GSL, the threshold voltage distribution of the memory cells adjacent to the ground selection line GSL is equal to the string selection line SSL. There will be a memory block that exhibits a difference that is relatively greater than the threshold voltage distribution of the adjacent memory cells. On the contrary, in comparison with the threshold voltage distributions of the memory cells not adjacent to the selection lines SSL and GSL, the threshold voltage distributions of the memory cells adjacent to the string selection line SSL are compared to those of the memory cells adjacent to the ground selection line GSL. There will be memory blocks that exhibit a difference that is relatively larger than the threshold voltage distribution.

Testing of each of the memory blocks results in threshold voltage distribution of memory cells not adjacent to the selection lines SSL and GSL, threshold voltage distribution of memory cells adjacent to the string selection line SSL, and ground selection line GSL. Threshold voltage distributions of adjacent memory cells will be compared. In each memory block, a threshold voltage indicating a relatively large difference among memory cells adjacent to the selection lines SSL and GLS is compared with a threshold voltage distribution of memory cells not adjacent to the selection lines SSL and GSL. The word line connected to the memory cells having the same will be selected as the dummy word line. The operation of selecting the dummy word line may be performed independently for each of the plurality of memory blocks. Thus, the threshold voltage distribution of the flash memory device 400 will be improved.

3 is a block diagram illustrating a memory system 10 according to the present invention. Referring to FIG. 3, the memory system 10 according to the present invention includes a memory controller 100 and a flash memory device 200.

The memory controller 100 is connected to a host and a flash memory device 200. The memory controller 100 transfers data read from the flash memory device 200 to the host or stores data transferred from the host in the flash memory device 200. The flash memory device 200 will be described in more detail with reference to FIG. 4.

The memory controller 100 includes a RAM 110, a processing unit 120, a host interface 130, an error correction block 140, and a memory interface 150. RAM 110 will be used as the operating memory of processing unit 120. The processing unit 120 will control the overall operation of the memory controller 100. The host interface 130 may include a protocol for performing data exchange between the host and the memory controller 100.

The error correction block 140 may detect and correct an error of data read from the flash memory device 200. The memory interface 150 will interface with the flash memory device 200. Each component of the memory controller 100 is well known to those having ordinary skill in the art, and thus, further description thereof is omitted.

4 is a block diagram illustrating the flash memory device 200 of FIG. 3. Referring to FIG. 4, a flash memory device 200 according to the present invention includes a memory cell array 210, a read / write circuit 220, a row decoder 230, and a control logic 240.

The memory cell array 210 is connected to the read / write circuit 220 through the bit lines BL and to the row decoder 230 through the word lines WL. The memory cell array 210 is composed of a plurality of memory blocks BLK. Each memory block BLK includes strings of a plurality of memory cells MC. String select transistors SST are respectively provided between the strings and the bit lines of the memory cells MC. Ground select transistors GST are respectively provided between the strings of the memory cells MC and the common source line CSL. The memory cells MC are connected to the word lines WL1 ˜WLm, the string select transistors SST are connected to the string select line SSL, and the ground select transistors GST are connected to the ground select line GSL. Is connected to. One or more of the plurality of word lines WL of each of the memory blocks BLK of the memory cell array 210 according to the present invention may be selected as dummy word lines. Selecting one or more of the word lines WL of each of the memory blocks BLK as dummy word lines may be performed independently for each of the plurality of memory blocks BLK.

The read / write circuit 220 is connected to the memory cell array 210 and the control logic 240. The read / write circuit 220 operates under the control of the control logic 240. The read / write circuit 220 exchanges data DATA with an external device. The read / write circuit 220 writes data to or reads data from the memory cells MC through the bit lines BL.

The row decoder 230 is connected to the memory cell array 230 and the control logic 240. The row decoder 230 operates under the control of the control logic 240. The row decoder 230 receives the address ADDR from the outside and selects the word lines WL of the memory cell array 210 in response to the address ADDR. The row decoder 230 according to the present invention will include a dummy word line selection circuit 250. The dummy word line selection circuit 250 may select one or more of the plurality of word lines of the memory cell array 210 as dummy word lines.

The control logic 240 controls overall operations of the flash memory device 200. The control logic 240 may operate in response to the control signal CTRL transmitted from the outside. In exemplary embodiments, the control signal CTRL may be provided from the memory controller 100 (see FIG. 3).

5 is a block diagram illustrating the memory cell array 210 and the dummy word line selection circuit 250 of FIG. 4. In FIG. 5, components of the dummy word line selection circuit 250 corresponding to one memory block BLK and one memory block BLK of the memory cell array 210 are illustrated. The dummy word line selection circuit 250 corresponding to one memory block BLK includes a dummy word line controller 252 and a dummy word line selector 254.

The dummy word line controller 252 may receive a block select signal BS from the outside. The block select signal BS may be a signal for selecting a memory block BLK to perform a read, write, and / or erase operation. The dummy word line controller 252 may be provided with dummy selection information (DSI) from the outside. The dummy selection information DSI may be information for selecting one or more of the word lines of the memory block BLK corresponding to the provided block address as dummy word lines. When the block select signal BS is transmitted from the outside, the dummy word line controller 252 generates the control signal S using the dummy select information DSI. The control signal S will be provided to the dummy word line selector 254.

The dummy word line selector 254 may receive a control signal S from the dummy word line controller 252. The dummy word line selector 254 may select one or more of the plurality of word lines of the corresponding memory block BLK as dummy word lines in response to the control signal S. FIG.

6 is a circuit diagram illustrating in detail the components of the memory block BLK and the dummy word line selection circuit 250 corresponding to the memory block BLK of the memory cell array 210 illustrated in FIG. 5.

Referring to FIG. 6, the memory block BLK includes cell strings composed of a plurality of memory cells MC. String select transistors SST are respectively provided between the bit lines BL and the cell strings. Ground select transistors GST are respectively provided between the cell strings and the common source line CSL. The memory cells MC are connected to the word lines L1 to Lk. The string select transistors SST are connected to the string select line SSL. Ground select transistors GST are connected to a ground select line GSL.

One or more of the plurality of word lines L1 to Lk of the memory block BLK of the memory cell array 210 according to the present invention may be selected as dummy word lines. For example, when the number of normal word lines NA1 to NAm for read, write, and / or erase operations is 32, and the number of word lines selected as dummy word lines DA1 and DA2 is 1, The number of word lines L1 to Lk of the memory block BLK may be 33. As another example, when the number of normal word lines NA1 to NAm for read, write, and / or erase operations is 32, and the number of word lines selected as dummy word lines DA1 and DA2 is three, The number of word lines L1 to Lk of the memory block BLK may be 35. 6, the number of word lines L1 to Lk selected as dummy word lines DA1 and DA2 is illustrated as one.

The word line selector 254 is connected to the word lines L1 to Lk. In response to the control signal S, the word line selector 254 may connect the word lines L1 to Lk to the normal word lines NA1 to NAm or the dummy word lines DA1 to DA2. The dummy word line selector 254 will include a plurality of NMOS transistors and a plurality of PMOS transistors.

As shown in FIG. 6, the word lines L1 to Lk may be connected to the NMOS transistor and the PMOS transistor, respectively. Each of the word lines L1 to Lk may be connected to two adjacent ones of the normal word lines NA1 to NAm and the dummy word lines DA1 and DA2 through an NMOS transistor and a PMOS transistor.

When the control signal S is logic high, the NMOS transistors of the dummy word line selector 254 will be turned on and the PMOS transistors will be turned off. In this case, the word line L1 may be selected as the dummy word line DA1. The word lines L2 to Lk may be selected as normal word lines NA1 to NAm. When the control signal S is logic low, the NMOS transistors of the dummy word line selector 254 will be turned off and the PMOS transistors will be turned on. In this case, the word line Lk may be selected as the dummy word line DA2. The word lines L1 to Lk-1 may be selected as normal word lines NA1 to NAm. That is, according to the state of the control signal S, the word line Lk adjacent to the string select line SSL or the word line L1 adjacent to the ground select line GSL will be selected as the dummy word line.

When a high voltage for the program operation is provided to the memory cells MC through the transistors of the dummy word line selector 254, the transistors of the dummy word line selector 254 may be formed as high voltage transistors.

Memory connected to the word line Lk adjacent to the string select line SSL as compared to the threshold voltage distribution of memory cells connected to the word lines L2 to Lk-1 not adjacent to the select lines SSL and GSL. When the threshold voltage distribution of the cells shows a relatively larger difference than the threshold voltage distribution of the memory cells connected to the word line L1 adjacent to the ground select line GSL, the control signal S will be set to logic low. That is, the word line Lk adjacent to the string select line SSL is set as a dummy word line and will not be used for write, read, and / or erase operations. Therefore, the threshold voltage distribution of the memory cells MC of the memory cell array 210 may be improved. In the opposite case, it will be appreciated that the threshold voltage distribution of the memory cells MC can be improved by setting the control signal S to logic high.

The dummy word lines DA1 and DA2 may be connected to the ground voltage Vss. The memory cells connected to the word line set as the dummy word line by the dummy word line selector 254 among the word lines L1 to Lk will remain erased. Since the dummy word line is connected to the ground voltage Vss and the memory cells are erased, the memory cells connected to the dummy word line will always be turned on. Thus, regardless of the dummy word line, the memory device will operate normally.

The dummy word line controller 252 and the dummy word line selector 254 shown in FIG. 6 will be provided to each of the plurality of memory blocks of the memory cell array 210. In this case, in response to the dummy selection information DSI, dummy word lines of each of the plurality of memory blocks may be independently selected. That is, even when threshold voltage distributions of memory cells connected to word lines adjacent to the selection lines SSL and GSL are different in each memory block, the threshold voltages of the memory cells MC of the memory cell array 210 may be different. Dispersion will improve.

The dummy word line controller 252 may receive dummy selection information DSI from a storage circuit (not shown). By way of example, the storage circuit would be a fuse box. When the block select signal BS is transmitted, the dummy word line controller 252 may determine whether a fuse corresponding to the selected memory block is cut. By way of example, if a power supply voltage Vcc is delivered through a corresponding fuse, it will be determined that the corresponding fuse is connected. In this case, the dummy word line selection circuit 252 may output a logic high as the control signal S. FIG. If the power supply voltage Vcc is not delivered through the corresponding fuse, it will be determined that the corresponding fuse has been cut. At this time, the dummy word line selection circuit 252 will output a logic low as the control signal (S).

As another example, the dummy selection information DSI may be stored in the memory cell array 210. In this case, the dummy word line controller 252 may include a latch. When power is supplied to the flash memory device 200, a power on reset operation and a power on read operation may be performed. In the power on read operation, the dummy selection information DSI stored in the memory cell array 210 may be read. The dummy selection information may be stored in the latch of the dummy word line controller 252 of the corresponding memory block BKL. When the block select signal BS is transferred, the dummy word line controller 252 may output the dummy select information DSI stored in the latch as the control signal S. FIG.

The dummy selection information DSI may be determined through a test of the flash memory device 200. In a test operation of the flash memory device 200, threshold voltage distributions of memory cells connected to word lines L1 to Lk of each of the plurality of memory blocks may be measured. Using the test result, dummy selection information DSI may be stored in the fuse box or the memory cell array 210.

In exemplary embodiments, the threshold voltage distribution of the memory cells adjacent to the string selection line SSL may be compared to the ground selection line GSL in comparison with the threshold voltage distribution of the memory cells not adjacent to the selection lines SSL and GSL. The dummy selection information DSI corresponding to the memory block representing a difference that is relatively larger than the threshold voltage distribution of the cells may be set to a logic low. In the opposite case, the dummy selection information DSI will be set to logic high.

FIG. 7 is a circuit diagram illustrating another example of components of the memory block BLK and the dummy word line selection circuit 250 corresponding to the memory block BLK of the memory cell array 210 illustrated in FIG. 6. In FIG. 7, the dummy word line selector 254 ′ selects the word lines L1 to Lk as normal word lines NA1 to NAm or dummy word lines DA1 to DA4. The number of word lines selected as dummy word lines DA1 to DA4 among the word lines L1 to Lk may be three.

When the control signal S is logic high, the word lines L0, L1, and Lk may be selected as dummy word lines DA1, DA2, and DA3. If the control signal S is logic low, the word lines L0, Lk-1, and Lk will be selected as dummy word lines DA2, DA3, and DA4. Larger number of dummy on the side of memory cells with threshold voltages showing a greater difference compared to the threshold voltage distribution of memory cells adjacent to select lines SSL and GSL that are not adjacent to select lines SSL and GSL. Word lines will be selected.

In exemplary embodiments, the threshold voltage distribution of the memory cells adjacent to the string selection line SSL may be compared to the ground selection line GSL in comparison with the threshold voltage distribution of the memory cells not adjacent to the selection lines SSL and GSL. If the difference is greater than the threshold voltage distribution of the cells, two word lines Lk-1, Lk adjacent to the string select line SSL are selected as dummy word lines, and adjacent to the ground select line GSL. One word line L1 will be selected as a dummy word line. In the opposite case, one word line Lk adjacent to the string select line SSL is selected as a dummy word line, and two word lines L1 and L2 adjacent to the ground select line GSL are dummy word lines. Will be selected.

As described above with reference to FIG. 6, the dummy word lines DA1 to DA4 are connected to the ground voltage, and the memory cells connected to the word lines selected as the dummy word lines among the word lines L1 to Lk are erased. Will remain. The operation of selecting dummy word lines among the plurality of word lines L1 to Lk of the memory block BLK may be independently performed for each of the plurality of memory blocks. The dummy selection information DSI for generating the control signal S may be stored in a storage circuit such as a fuse box or a memory cell array. In addition, the dummy selection information DSI may be determined through a test of the flash memory device 200. In exemplary embodiments, the threshold voltage distribution of the memory cells connected to the plurality of word lines L1 to Lk of each of the plurality of memory blocks of the memory cell array 210 ′ may be determined.

According to the present invention, dummy word lines are selected among the plurality of word lines according to the dummy selection information DSI. Among the memory cells adjacent to the selection lines, word lines connected to memory cells having threshold voltages representing a relatively large difference compared to threshold voltage distributions of memory cells not adjacent to the selection lines are selected as dummy word lines. Thus, the threshold voltage distribution of the nonvolatile memory device is improved, and the yield is improved.

8 is a block diagram illustrating a computing system 300 including a flash memory device 200 according to the present invention. Referring to FIG. 8, the computing system 300 according to the present invention includes a central processing unit 310, a RAM 320, a user interface 330, a power source 340, and a memory system 10.

The memory system 10 includes a memory controller 100 and a flash memory device 200 according to the present invention. The memory system 10 is electrically connected to the power source 340, the central processing unit 310, the RAM 320, and the user interface 330 through the system bus 350. Data provided through the user interface 330 or processed by the CPU 310 is stored in the flash memory device 200 through the memory controller 100.

When the memory system 10 is mounted as a semiconductor disk device (SSD), the booting speed of the computing system 300 may be dramatically increased. Although not shown in the drawings, it will be understood by those skilled in the art that the system according to the present invention may further include an application chipset, a camera image processor, and the like.

In the above-described embodiment, the flash memory device according to the present invention selects one or three of the plurality of word lines as dummy word lines. However, it will be appreciated that the number of dummy word lines in accordance with the present invention is not limited to one or three. In the above-described embodiment, the dummy word line selector according to the present invention has been described as being composed of a plurality of NMOS transistors and a plurality of PMOS transistors. However, the dummy word line selector for selecting dummy word lines according to the present invention is not limited to being composed of a plurality of NMOS transistors and a plurality of PMOS transistors. In the above-described embodiment, it is described that the dummy selection information according to the present invention is stored in a fuse box or a memory cell array. However, the dummy selection information according to the present invention is not limited to being stored in a fuse box or a memory cell array. It is to be understood that the present invention may be variously modified or applied within the technical scope of the present invention.

In the detailed description of the present invention, specific embodiments have been described, but it is obvious that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a block diagram illustrating a flash memory device.

FIG. 2 is a diagram illustrating a threshold voltage distribution of memory cells of the flash memory device of FIG. 1.

3 is a block diagram illustrating a memory system according to the present invention.

FIG. 5 is a block diagram illustrating a memory cell array and a dummy word line selection circuit of FIG. 4.

FIG. 6 is a circuit diagram illustrating in detail the components of the memory block and the dummy word line selection circuit corresponding to the memory block of the memory cell array shown in FIG. 5.

FIG. 7 is a circuit diagram illustrating another example of components of a memory block of the memory cell array illustrated in FIG. 6 and a dummy word line selection circuit corresponding to the memory block.

Claims (14)

Memory cell arrays; A plurality of word lines connected to the memory cell array; And A dummy word line selection circuit connected to the memory cell array through the plurality of word lines, The dummy word line selection circuit selects one or more of the plurality of word lines as dummy word lines. The method of claim 1, The memory cell array Cell strings each having a plurality of memory cells each connected to the plurality of word lines; String select transistors connected to a string select line and respectively connected between the cell strings and the bit lines; And And a ground select transistor connected to a ground select line and connected between the cell strings and the common source line, respectively. The method of claim 2, The dummy word line selection circuit selects a word line adjacent to the ground selection line or the string selection line among the plurality of word lines as a dummy word line. The method of claim 3, wherein The dummy word line selection circuit is The dummy word includes a word line connected to memory cells having a threshold voltage distribution indicating a relatively large difference from a threshold voltage distribution of memory cells not adjacent to the selection lines among the memory cells adjacent to the string selection line and the ground selection line. Nonvolatile memory device selected by line. The method of claim 2, The dummy word line selection circuit is And one or more word lines adjacent to the string select line and one or more word lines adjacent to the ground select line as the dummy word lines. The method of claim 5, wherein And a number of dummy word lines adjacent to the string select line and a number of dummy word lines adjacent to the ground select line are different. A memory cell array consisting of a plurality of memory blocks; A plurality of word lines connected to each of the plurality of memory blocks; And A dummy word line selection circuit connected to each of the plurality of memory blocks through the plurality of word lines, The dummy word line selection circuit selects one or more of the plurality of word lines of each of the plurality of memory blocks as dummy word lines, And selecting the dummy word lines of each of the plurality of memory blocks is independently performed. The method of claim 7, wherein The dummy word line selection circuit is connected to each of the memory blocks, the plurality of dummy word line selectors configured to select the one or more of the plurality of word lines of each of the memory blocks as dummy word lines Nonvolatile memory device comprising a. The method of claim 8, And a storage circuit configured to store dummy selection information for selecting the one or more of the plurality of word lines of each of the plurality of memory blocks as dummy word lines. The method of claim 9, The storage circuit includes a plurality of fuses respectively corresponding to the plurality of memory blocks, The dummy selection information is stored in the storage circuit through the cutting of the plurality of fuses. The method of claim 10, The dummy word line selection circuit further comprises an address comparison circuit, The address comparison circuit receives a block address from an external source and corresponds to the transferred block address among the dummy word line selectors with information indicating whether a fuse corresponding to the transferred block address is cut among the dummy selection information. A nonvolatile memory device for transferring a dummy word line selector. The method of claim 9, The dummy selection information is stored in the memory cell array, Each of the plurality of dummy word line selectors includes a latch, And, upon powering on the nonvolatile memory device, the dummy selection information is stored in a latch of a corresponding dummy word line selector of the plurality of dummy word line selectors, respectively. A method of operating a nonvolatile memory device including a plurality of memory blocks including a plurality of word lines, the method comprising: Receiving a block address for a read and / or write operation; And Selecting one or more of the plurality of word lines of the memory block corresponding to the block address of the plurality of memory blocks as dummy word lines. Nonvolatile memory devices; And A memory controller configured to control an operation of the nonvolatile memory device; The nonvolatile memory device Memory cell arrays; A plurality of word lines connected to the memory cell array; And A dummy word line selection circuit connected to the memory cell array through the plurality of word lines, And the dummy word line selection circuit selects one or more of the plurality of word lines as dummy word lines.

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