KR20090099711A - Interface apparatus of radio access station - Google Patents

Abstract

PURPOSE: An interface device of a base station is provided to minimize the loss by a transmission cable by interfacing a transceived signal through an RF processing unit and intermediate frequency. CONSTITUTION: An interface device(202) of a base station comprises digital up converters(226a,226b), a digital/analog converter, a digital combiners(230a,230b) and digital down converters(228a,228b). The digital up-converters up-convert the frequency of a transmission IQ signal according to the frequency allocation for the IQ signal of a baseband. The digital/analog converter converts the transmission IQ signal having the up-converted frequency into a transmission IQ signal of the first serial intermediate frequency, and generates plural analog output signals of the first intermediate frequency so as to be transmitted through plural paths by performing the analog conversion for the transmission IQ signal of the first intermediate frequency.

Description

Interface device of base station {Interface Apparatus of Radio Access Station}

The present invention relates to an interface device of a base station, and more particularly, to an apparatus for interfacing a baseband digital IQ signal and an intermediate frequency analog signal transmitted and received as a unified device.

The baseband digital IQ signal is converted into an intermediate frequency analog signal and a reverse conversion technology is required for the interface between the channel card that is responsible for digital processing of the transmission and reception data at the base station and the RF processing unit or repeater of the base station.

1 is an interface device of a general base station, which performs an interface to an RF processor or a repeater of a channel card and a base station.

As shown in the figure, an interface device of a general base station is divided into a transceiver unit 102 and a repeater interface unit 104 which are responsible for signal processing of a transceiver path with respect to a transmitted IQ signal. It performs the interface function of the channel card 106 in charge of processing and the RF processing unit (not shown) or repeater (not shown).

Referring to the transmission signal processing procedure of the transceiver unit 102, the transceiver unit 102 receives a serial transmission IQ signal from the channel card 106, converts it into a parallel transmission IQ signal, and converts the digital up converter (not shown). Increase the sampling frequency for the parallel IQ signal and perform frequency up-conversion according to frequency allocation (FA).

Frequency up-conversion according to frequency allocation means up-converting the frequency into signals based on three center frequencies for I and Q components, respectively, according to 3FA. As an example, the I component may be up-converted based on center frequencies of 16 MHz, 25 MHz, and 34 MHz.

Thereafter, the frequency-converted transmit IQ signal is up-converted back into an analog signal based on an intermediate frequency IF of 125 MHz while undergoing a digital analog converting process. Subsequently, the mixer is converted into an RF signal and transmitted to the power amplifier of the RF processing unit of the base station existing outside the transceiver unit 102.

Meanwhile, referring to the received signal processing process of the transceiver unit 102, the transceiver unit 102 receives an RF signal from a low noise amplifier (LNA) of the RF processing unit and performs the reverse process of the above-described transmission signal processing process.

For example, the transceiver unit 102 analog-to-digital converts a received IQ signal based on an intermediate frequency of 75 MHz from the RF processor of the base station and downconverts the frequency according to 3FA using a digital down converter (not shown). Thus, the transceiver unit 102 may transmit the baseband signal to the channel card 106.

The repeater interface unit 126 differs from the transceiver unit 102 in that the repeater interface unit 126 interfaces with a repeater (not shown) rather than the RF processing unit of the base station, and thus detailed description thereof will be omitted.

However, since the interface device of the general base station described above must interface with both the RF processing unit and the repeater of the base station, a number of logic devices, such as logic devices for digital up-converting, digital down-converting, digital analog converting, analog-digital converting, and other functions, There is a problem that the wiring is necessary and complicated for signal processing.

In addition, in the case of 3FA, there is a problem in that a corresponding logic device of three times is needed to perform frequency up-conversion according to FA, and two more corresponding logic devices are needed to obtain diversity transmission gain.

Therefore, there is a problem that the interface device of a general base station should be separated into the transceiver unit 102 and the repeater interface unit 104 as a space problem necessary for implementing the interface device.

Furthermore, since the transceiver unit 102 and the repeater interface unit 104 exist separately, the serial and / or parallel conversion unit is also doubled, resulting in heavy waste of logic devices and complicated signal lines on the backboard where the interface device is inserted. There was a problem.

In addition, when interfacing the transmission and reception signals to the RF processing unit and a high frequency RF signal, there is a problem that the loss of the signal generated in the transmission cable is large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and in the interface device of a base station, providing a device that can reduce the size and cost of the interface device and the base station system by unifying the transceiver unit and the repeater interface unit into one device. It is a technical problem.

Another object of the present invention is to provide an apparatus capable of simplifying a signal line on a back board by unifying an interface device into one device by reducing an element for interfacing with a transceiver or a repeater.

In addition, another object of the present invention is to provide a device for minimizing loss caused by a transmission cable by interfacing a transmission / reception signal with an RF processor at an intermediate frequency.

In accordance with an aspect of the present invention, an interface apparatus of a base station includes: a digital up-converter unit for up-converting a frequency of the transmission IQ signal according to frequency allocation of a baseband transmission IQ signal; Converting the up-converted transmit IQ signal into a first transmit intermediate IQ signal in series and performing analog conversion on the transmit IQ signal of the first intermediate frequency to transmit a plurality of first paths; A digital analog converter for generating an analog output signal of an intermediate frequency; A digital combiner unit configured to perform digital combining on a plurality of received IQ signals of a plurality of second intermediate frequencies obtained through the plurality of paths; And a digital down converter configured to down-convert the received IQ signal on which the digital combining has been performed according to frequency allocation to generate a baseband receive IQ signal.

In the interface device of the base station according to another aspect of the present invention for achieving the above object, in the interface device of the base station for receiving the baseband transmission IQ signal from the channel card of the base station to interface with the transceiver and the repeater of the base station, A digital up-converter configured to upconvert the frequency of the transmit IQ signal according to the frequency allocation of the baseband transmit IQ signal; And converts one of the up-converted transmission IQ signals into a serial transmission IQ signal of a first intermediate frequency and performs analog conversion on the transmission IQ signal of the first intermediate frequency to be transmitted to the transceiver and the repeater. And a digital-to-analog converter for generating a plurality of first intermediate frequency analog output signals.

As described above, according to the present invention, the transmitter outputs a plurality of analog-converted signals after upconverting the transmission IQ signal into a series of desired intermediate frequency IQ signals in one interpolation path. The receiving unit digitally combines the received IQ signal obtained from the RF processor and the repeater of the base station at the rear of the analog-to-digital converter. Therefore, since the interface logic for the RF processing unit and the logic for the repeater do not need to exist separately, the total number of interface logics can be reduced, so that the interface device can be implemented as a single device.

In addition, the present invention has another effect of reducing the size and cost of the base station system and simplifying the signal line on the back board by unifying the interface device into one device.

 In addition, the present invention has another effect that can reduce the loss of the signal by the transmission cable by transmitting and receiving a signal at an intermediate frequency with the RF processor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an interface device of a base station according to an embodiment of the present invention, wherein the interface device 202 of the base station interfaces a digital signal of a baseband and an analog signal of an intermediate frequency band with a digital radio interface unit (DRIU). )

As shown, the interface device 202 of the base station according to an embodiment of the present invention includes a serial-to-parallel converter 204, an FPGA unit 206, a digital-to-analog converter unit 208a, 208b, Amplifier sections 210a, 210b, 216a, and 216b, and attenuators 214a, 214b, 218a, and 218b. In addition, the interface device 202 of the base station further includes analog-to-digital converters 220a and 220b, amplifiers 222a and 222b, and attenuators 224a and 224b to interface the received signals.

In terms of the interface for the transmission signal from the channel card 234 of the base station to the terminal, the interface device 202 of the base station receives a series of baseband transmission IQ signals from the channel card 234 to allocate the frequency. FA) and convert it into a complex analog signal with intermediate frequencies of 116 MHz, 125 MHz, and 134 MHz with a main RF transceiver (not shown), and then into a main RF transceiver (not shown) and a main repeater (not shown) for RF processing. send.

In addition, the interface device 202 of the base station transmits to the diversity RF transceiver (not shown) and diversity repeater (not shown) in the same manner to obtain a transmission gain using diversity.

In terms of the interface to the received signal from the terminal to the channel card 234, the interface device 202 of the base station receives a complex analog signal based on intermediate frequencies of 66 MHz, 75 MHz, and 84 MHz according to 3FA from the main RF transceiver and the main repeater. It receives and converts it into a baseband received IQ signal, which is then sent to the channel card 234 for digital processing.

In addition, the interface device 202 of the base station converts a signal received from the diversity RF transceiver and the diversity repeater into a baseband received IQ signal in the same manner to obtain a transmission gain using diversity, and then the channel card ( 234).

The serial-to-parallel conversion unit 204 converts the serial transmission IQ signal received from the channel card 234 into parallel transmission IQ signals separated by I and Q components, thereby converting the main digital up-converter unit of the FPGA unit 206 ( 226a) and diversity digital up-converter 226b.

The serial-to-parallel converter 204 converts the parallel received IQ signal received from the main digital down converter 228a and the diversity digital down converter 228b into a serial received IQ signal and transmits it to the channel card 234. do.

The field programmable gate array block 206 may include a main digital up converter 226a, a diversity digital up converter 226b, a main digital down converter 228a, a diversity digital down converter 228b, A first digital combiner unit 230a, a second digital combiner unit 230b, a first delay unit 232a, and a second delay unit 232b are included.

In terms of signal transmission, the FPGA unit 206 upconverts the frequency of the transmission IQ signal according to the frequency allocation for the baseband transmission IQ signal, thereby generating a complex digital signal having a center frequency of 16 MHz, 25 MHz, or 34 MHz. . Then, interpolation and filtering are performed on the 10Msps (10M Sampling Per Second) transmission IQ signal received from the serial-to-parallel converter 204 to oversample the signal to 100Msps.

In terms of signal reception, the FPGA unit 206 down-converts a complex digital signal having an intermediate frequency of 16 MHz, 25 MHz, and 34 MHz received from the first digital combiner unit 230a according to frequency allocation to receive baseband. Generate an IQ signal. In addition, decimation and filtering are performed on the 100 Msps composite digital signal and downsampled into a 10 Msps signal.

In addition, the FPGA unit 206 performs the interface for the above-described transmission and reception signals in the same manner for diversity.

The main digital up-converter 226a performs frequency allocation on the parallel baseband transmission IQ signal received from the serial-to-parallel converter 204 and up-converts the frequency for frequency allocation. Then, the sampling frequency is adjusted upward from 10Msps to 100Msps.

4 is a diagram illustrating an internal circuit of the main digital up converter unit 226a according to an embodiment of the present invention. The main digital up converter unit 226a includes three digital up converter blocks 302, 304, and 306 to perform 3FA. For convenience of description, an interpolator and a filter for oversampling are omitted in the digital up converter blocks 302, 304, and 306.

As shown, the main digital up-converter 226a includes a 1FA digital up-converter 302, a 2FA digital up-converter 304, a 3FA digital up-converter 306, and the like, and the frequency according to FA. Perform up-conversion.

The 1FA digital up converter unit 302 includes an FIR filter 308, an NCO 310 for 1FA, a multiplier 312 for 1FA, and the like.

The FIR filter 308 removes harmonic components and filters the output characteristics by filtering the received baseband transmit I signal. The 1FA NCO 310 generates a 16 MHz local signal and transmits it to the 1FA multiplier 312. The 1FA multiplier 312 multiplies the transmit I signal by a 16 MHz local signal to base the frequency of the transmit I signal. The band upconverts to an intermediate frequency of 16MHz.

Here, the frequency allocation FA will be described as an example. The FA is divided into three channels 3FA having a transmission bandwidth of 30 MHz and a transmission bandwidth of 10 MHz. It means to allocate channel.

Subsequently, the frequency up-converted I signal is summed with the I signal outputs of the 2FA digital up-converter 304 and the 3FA digital up-converter 306 by the I-signal adder 318, and the result is It is output to the digital-analog converter 208a.

The 1FA digital up-converter 302 performs interpolation and filtering to oversample from 10Msps to 100Msps for the sampling frequency of the transmission I signal.

Since the 2FA digital up-converter 304 and the 3FA digital up-converter 306 use NFA 314 for 2FA and NCO 316 for 3FA, respectively, the 1FA digital up-converter has a 25MHz and 34MHz frequency increase width according to FA. Since only the output of the unit 302 is different, and the functions of the various blocks are obvious as described above, the description of the 2FA digital up converter unit 304 and the 3FA digital up converter unit 306 will be omitted.

In addition, the Q signal frequency up-converted in the same manner is combined with the Q signal outputs of the 2FA digital up-converter 304 and the 3FA digital up-converter 306 by the Q-signal adder 320, and the result is a digital analog signal. It is output to the converter section 208a.

Referring back to FIG. 2, the diversity digital up converter unit 226b performs the same operation as the main digital up converter unit 226a to obtain the diversity transmission gain of the transmission IQ signal. As described above, since the operation of the diversity digital up-converter 226b is self-explanatory, the description thereof is omitted.

The main digital down converter unit 228a down-converts the frequency according to frequency allocation for a complex digital signal having an intermediate frequency of 16 MHz, 25 MHz, or 34 MHz received from the first digital combiner unit 230a, thereby paralleling the baseband. Convert to the received IQ signal. Then, the sampling frequency is adjusted downward from 100Msps to 10Msps.

4 is a diagram illustrating an internal circuit of the main digital down converter 228a according to an embodiment of the present invention. The main digital down converter section 228a includes three digital down converter blocks 402, 404, 406 to perform 3FA. For convenience of description, an interpolator and a filter for oversampling are omitted from the digital down converter blocks 402, 404, and 406.

As shown, the main digital down converter section 228a includes a 1FA digital down converter section 402, a 2FA digital down converter section 404, a 3FA digital down converter section 406, and the like, and a frequency according to FA. Perform down conversion.

The 1FA digital down converter unit 402 includes a 1FA NCO 408, a 1FA multiplier 410, an FIR filter 412, and the like.

The NCO 408 for 1FA generates a 16 MHz local signal and sends it to the 1FA multiplier 410. The 1FA multiplier 412 multiplies the received I signal with a 16 MHz local signal to multiply the frequency band at an intermediate frequency band of 16 MHz. Downconvert to baseband.

The FIR filter 412 removes the 2FA and 3FA components and harmonic components of the received I signal by filtering the baseband down-converted received I signal using a center frequency of 0 Hz and a BandWidth (BW) characteristic of 9 MHz. Subsequently, the frequency down-converted filtered I signal is output to the serial-to-parallel converter 204.

The 1FA digital down converter 402 performs decimation and filtering to downsample from 100Msps to 10Msps with respect to the sampling frequency of the received I signal.

Since the 2FA digital down converter unit 404 and the 3FA digital down converter unit 406 use the NCO 414 for the 2FA and the NCO 416 for the 3FA, respectively, the 1FA digital down converter has a frequency downlink width of 25 MHz and 34 MHz according to FA. Since only the output of the unit 402 is different, detailed description thereof will be omitted.

In addition, the received Q signals of the digital down converter blocks 402, 404, 406 which are frequency down-converted in the same manner are output to the serial-to-parallel converter 204.

Referring back to FIG. 2, the diversity digital down converter 228b performs the same operation as the main digital down converter 228a to obtain the diversity transmission gain of the received IQ signal.

The first digital combiner unit 230a receives a complex digital signal having intermediate frequencies of 16 MHz, 25 MHz, and 34 MHz from the analog digital converter units 220a and 220b in the receiving path to perform digital combining.

However, when the signal received by the first digital combiner unit 230a is synchronized at the time of reception, the synchronization of the signal must be exactly matched, and the output of the combiner can guarantee normal data if one clock is changed due to a delay of a specific reception path. There will be no.

Therefore, by inserting the first delay unit 232a in the path between the first digital combiner unit 230a and the analog-to-digital converter unit 220b and performing time advance, the first digital combiner unit ( The input signals of 230a are synchronized.

For example, the RF transceiver or the repeater transmits a signal to the interface device 202 as early as a time corresponding to a time advance value, and delays a predetermined time in the first delay unit 232a so that the first digital combiner unit 230a receives the signal. To match the motives. Here, the time advance value may be transmitted to each other by the interface device 202 and the RF transceiver or the repeater using frequency shift keying (FSK) or amplitude shift keying (ASK) communication.

Due to the function of the first digital combiner unit 230a, only one digital down converter is required for each FA in the interface process of the signals received from the main RF transceiver and the main repeater. This has the effect that the complex logic devices shown in FIG. 4 are cut in half. In addition, there are fewer devices in the path connected to the digital down converter and less space for line placement. The result is a reduction in the size and cost of the interface device.

Since the second digital combiner 230b and the second delay unit 332b perform the same digital combining and synchronization functions as described above, description thereof will be omitted.

The digital analog converters 208a and 208b convert 3FA composite digital signals of intermediate frequencies 16MHz, 25MHz, and 34MHz into composite analog signals of intermediate frequencies 116MHz, 125MHz, and 134MHz. Specifically, a sampling clock used for digital / analog conversion is adjusted to be converted into an analog signal having a desired frequency band, thereby performing secondary frequency up-conversion.

In addition, the digital analog converters 208a and 208b generate a plurality of analog output signals so that the output is transmitted in a plurality of paths.

5 is a block diagram showing a digital-to-analog converter 208a according to an embodiment of the present invention.

The digital analog converter unit 208a includes an I interpolator 502a, a Q interpolator 502b, an I modulator 504a, a Q modulator 504b, a combining unit 506, a first converter unit 508a, and A second converting portion 508b is included.

Hereinafter, the operation will be described as a representative example of 25 MHz among intermediate frequencies according to FA of the input signal of the digital-to-analog converter 208a.

The I interpolator 502a and the Q interpolator 502b oversample the transmitted I and transmit Q signals of 100 Msps and 25 MHz, respectively, to have a sampling frequency of fs = 400 MHz.

The I modulator 504a and the Q modulator 504b perform a 100 MHz frequency up operation, and generate a carrier of 100 MHz by quadrature dividing a 400 MHz sampling clock into four divisions (fs / 4 Modulation), thereby generating 125 MHz (= 100 MHz +). A transmit I signal and a transmit Q signal having an intermediate frequency of 25 MHz).

The combining unit 506 combines the 125 MHz transmit I signal and the transmit Q signal to generate a serial transmit IQ signal.

The first converter unit 508a and the second converter unit 508b digitally convert the combined serial transmission IQ signal to generate two analog outputs.

One of these two analog signals is sent to the main RF transceiver and the other is sent to the main repeater.

As a result, the logic for oversampling and modulation and the logic devices present in the path to the digital analog converter are cut in half, rather than using two digital analog converters for transmission to the main RF transceiver and the main repeater. .

This means that the size of the interface device is reduced, which means that the interface device for the RF transceiver and the repeater can be unified into one device.

Meanwhile, as described above, when the 3FA composite digital signal is input to the digital analog converter 208a, the 3FA composite analog signal of 100 MHz + 16 MHz, 100 MHz + 25 MHz, and 100 MHz + 34 MHz is generated. In addition, since another digital-to-analog converter 208b for diversity transmission performs the same operation as described above, a description thereof will be omitted.

In one embodiment, the 3FA composite analog signal is sent to a bandpass filter (e.g., SAW filter) (not shown), where the bandpass filter filters the signal at, for example, center frequency = 125 MHz and BW = 30 MHz, thereby eliminating carrier waves. 3FA analog signals of desired 116 MHz (FA1), 125 MHz (FA2), and 134 MHz (FA3) can be obtained.

Referring back to FIG. 2, the outputs of the digital-to-analog converters 208a and 208b pass through the predetermined amplifier units 210a, 210b, 216a and 216b in the path of the main RF transceiver direction, and the attenuators 214a, 214b and 218a. After limiting to a specific voltage level at 218b, it is transmitted to the main RF transceiver, the main repeater, the diversity RF transceiver and the diversity repeater.

On the other hand, when a complex analog signal having intermediate frequencies of 66 MHz, 75 MHz, and 84 MHz is received from the main RF transceiver, the attenuator 224a is limited to a specific voltage level, and then passes through a predetermined amplifier unit 222a and the analog-to-digital converter unit ( 220a).

The analog-to-digital converter 220a samples the received signal at 100 Msps and converts the analog / digital signal. In this case, down-conversion of the intermediate frequency occurs. As an example, a component based on an intermediate frequency of 75 MHz in the received analog signal has an image signal at 25 MHz as shown in FIG. 6. This intermediate frequency of 25MHz, the digitally converted received IQ signal is output to the first digital combiner unit 230a.

As a result, the analog-to-digital converter 220a outputs a 3FA composite digital signal having an intermediate frequency of 16 MHz, 25 MHz, and 34 MHz.

On the other hand, when a complex analog signal having intermediate frequencies of 66 MHz, 75 MHz, and 84 MHz is received from the main repeater, the signal is limited to a specific voltage level in the attenuator 224b, and then passed through a predetermined amplifier unit 222b and then the analog-to-digital converter. It is input to the part 220b. The corresponding operation is for diversity gain, and the detailed description thereof will be omitted since it is the same as the process of processing the signal received from the main RF transceiver.

On the other hand, since the operation of each block in the signal reception path from the diversity RF transceiver and the diversity repeater as described above will be omitted.

7 is a flowchart illustrating a transmission signal processing procedure of an interface device of a base station according to an embodiment of the present invention.

First, the serial / parallel conversion unit 204 converts the transmission IQ signal received from the channel card 234 into a parallel signal (S702).

Next, the digital up-converter 226a up-converts the baseband transmit IQ signal into a signal having intermediate frequencies of 16 MHz, 25 MHz, and 34 MHz according to 3FA. In addition, the 100Msps signal is generated from the 10Msps signal through the oversampling process (S704).

Next, the digital-to-analog converter 208a performs digital / analog conversion, and generates a complex analog signal having an intermediate frequency of 116 MHz, 125 MHz, and 134 MHz through interpolation and modulation (S706). At this time, a plurality of analog signals are output for transmission to the RF transceiver and the repeater.

Next, the 3FA analog signal is transmitted to the RF transceiver and the repeater (S708).

8 is a flowchart illustrating a received signal processing procedure of an interface device of a base station according to an embodiment of the present invention.

First, a complex analog signal having an intermediate frequency of 66 MHz, 75 MHz, and 84 MHz is received from an RF transceiver and a repeater (S802).

Next, the analog-to-digital converters S220a and S220b perform analog / digital conversion on the received analog signal and generate a complex digital signal having an intermediate frequency of 16 MHz, 25 MHz, and 34 MHz through a 100 Msps sampling process (S804).

Next, the digital combiner 230a performs digital combining on the received IQ signals output from the analog-digital converters S220a and S220b (S806).

Next, the digital down-converting unit 228a performs frequency downconversion on the received IQ signal on which digital combining has been performed to generate a baseband received IQ signal, and performs serial-to-parallel conversion to the channel card 234. (S808). At this time, the digital down converting unit 228a performs down sampling to generate a received IQ signal of 10 Msps.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features.

Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing an interface device of a general base station.

2 is a block diagram illustrating an interface device of a base station according to an embodiment of the present invention.

3 is a diagram illustrating an internal circuit of a main digital up converter unit according to an embodiment of the present invention.

4 is a diagram illustrating an internal circuit of a main digital down converter unit according to an embodiment of the present invention.

5 is a block diagram showing a digital analog converter according to an embodiment of the present invention.

6 is a view showing the output of the analog-to-digital converter unit according to an embodiment of the present invention.

7 is a flowchart illustrating a transmission signal processing procedure of an interface device of a base station according to an embodiment of the present invention.

 8 is a flowchart illustrating a received signal processing procedure of an interface device of a base station according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

204: serial-to-parallel conversion unit 206: FPGA unit

208a, 208b: digital-to-analog converter section

210a, 210b, 216a, 216b, 222a, 222b: Amplifier section

214a, 214b, 218a, 218b, 224a, 224b: attenuation part

220a, 220b: analog-to-digital converter section

Claims (20)

A digital up-converter configured to upconvert the frequency of the transmit IQ signal according to frequency allocation of a baseband transmit IQ signal; Converting the up-converted transmit IQ signal into a first transmit intermediate IQ signal in series and performing analog conversion on the transmit IQ signal of the first intermediate frequency to transmit a plurality of first paths; A digital analog converter for generating an analog output signal of an intermediate frequency; A digital combiner unit configured to perform digital combining on a plurality of received IQ signals of a plurality of second intermediate frequencies obtained through the plurality of paths; And A digital down converter configured to down-convert the received IQ signal on which the digital combining is performed according to frequency allocation to generate a baseband received IQ signal; Interface device of the base station comprising a. The method of claim 1, wherein the plurality of paths, And a path connected to the transceiver of the base station and a path connected to the repeater. The method of claim 1, And a serial-to-parallel converter for converting a serial first IQ signal into a parallel baseband transmit IQ signal and converting a parallel down-converted baseband received IQ signal into a serial second IQ signal. Interface device of the base station, characterized in that. The method of claim 1, wherein the digital to analog converter, An interpolation unit configured to perform interpolation on the transmitted IQ signal whose frequency is up-converted; A modulation unit for performing modulation on a frequency corresponding to 1/4 times a sampling frequency with respect to the transmitted IQ signal on which the interpolation has been performed; And A combining unit configured to combine the I and Q components of the modulated transmit IQ signal to generate the transmit IQ signal of the first intermediate frequency in series; Interface device of the base station comprising a. The method of claim 1, And an analog-to-digital converter configured to generate the received IQ signal of the second intermediate frequency by performing digital conversion and frequency downconversion on the received IQ signal of the third intermediate frequency acquired through a specific path among the plurality of paths. An interface device of a base station characterized in that. The method of claim 1, wherein the digital up converter unit, A frequency uplink NCO (Numerically Controlled Oscillator) for generating a frequency uplink local signal according to frequency allocation; And A frequency uplink multiplier that multiplies the baseband transmit IQ signal by a frequency uplink local signal according to the frequency assignment; Interface device of the base station comprising a. The method of claim 6, wherein the digital up converter unit, And the frequency uplink NCO and the frequency uplink multiplier corresponding to a frequency allocation for the baseband transmit IQ signal. The method of claim 1, wherein the digital up converter unit, And a channel filter and an FIR filter to interpolate the sampling frequency of the baseband transmit IQ signal. The method of claim 1, wherein the digital down converter unit, A frequency down NCO for generating a frequency down local signal according to frequency allocation; And A frequency down multiplier for multiplying the received IQ signal on which the digital combining is performed by a frequency down local signal according to the frequency allocation; Interface device of the base station comprising a. The method of claim 9, wherein the digital down converter unit, And the frequency downlink NCO and the frequency downlink multiplier corresponding to a frequency allocation for the received IQ signal on which the digital combining has been performed. The method of claim 1, wherein the digital up converter unit, And a decimation of a sampling frequency of the received IQ signal on which the digital combining has been performed using a channel filter and an FIR filter. The method of claim 1, And a digital up converter unit and a digital analog converter unit for diversity transmission on the baseband transmit IQ signal. The method of claim 1, And a digital down converter unit and a digital combiner unit for diversity reception on the received IQ signal of the second intermediate frequency. The method of claim 1, And an attenuator for attenuating a level of the analog output signal of the first intermediate frequency to a specific level. The method of claim 1, And a delay unit configured to perform time advance to synchronize a plurality of second intermediate frequency received IQ signals on which the digital combining is performed. An interface apparatus of the base station for receiving a baseband transmit IQ signal from a channel card of a base station and interfacing with a transceiver and a repeater of the base station. A digital up-converter configured to upconvert the frequency of the transmit IQ signal according to the frequency allocation of the baseband transmit IQ signal; And A plurality of transmission IQ signals of which one frequency is up-converted into transmission IQ signals of a first intermediate frequency in series, and analog conversion of the transmission IQ signals of the first intermediate frequency to be transmitted to the transceiver and the repeater A digital analog converter for generating an analog output signal of a first intermediate frequency of the digital signal; Interface device of the base station comprising a. The method of claim 16, wherein the digital-to-analog converter, An interpolation unit configured to perform interpolation on the transmitted IQ signal whose frequency is up-converted; A modulation unit for performing modulation on a frequency corresponding to 1/4 times a sampling frequency with respect to the transmitted IQ signal on which the interpolation has been performed; And A combining unit configured to combine the I and Q components of the modulated transmit IQ signal to generate the transmit IQ signal of the first intermediate frequency in series; Interface device of the base station comprising a. The method of claim 16, wherein the digital up converter unit, A frequency uplink NCO for generating a frequency uplink local signal according to the frequency assignment; And A frequency uplink multiplier that multiplies the baseband transmit IQ signal by a frequency uplink local signal according to the frequency assignment; Interface device of the base station comprising a. The method of claim 16, wherein the digital up converter unit, And a channel filter and an FIR filter to interpolate the sampling frequency of the baseband transmit IQ signal. The method of claim 16, And a digital up converter unit and a digital analog converter unit for diversity transmission on the baseband transmit IQ signal.

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