KR20090097450A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor IC is provided to improve the process margin by preserving different types of transistors from being adjacently arranged. A semiconductor IC comprises a plurality of cell arrays(100), the first latch unit(110) and the second latch unit(120). The cell arrays are connected to a pair of bit lines. The bit lines are a bit line and a bit bar line. The first latch unit is connected to one side of a cell array through the bit line pair and corresponds to an NMOS transistor among transistors forming a sense amplifier. The second latch unit is connected to the other side of the cell array through the bit line pair and corresponds to a PMOS transistor. The semiconductor IC amplifies data loaded on the bit line pair by the first and second latch units.

Description

Semiconductor Integrated Circuits

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit capable of reducing the area of a sense amplifier and improving process margins.

1 is a circuit diagram of a semiconductor integrated circuit including a sense amplifier according to the prior art.

The semiconductor integrated circuit shown in FIG. 1 includes a plurality of cell arrays 10 and sense amplifiers 40.

The sense amplifier 40 senses and amplifies data carried on the bit line BL and the bit bar line / BL according to the level of the first electrode RTO and the level of the second electrode SB. The sense amplifier 40 includes fourth and fifth NMOS transistors N4 and N5 and first and second PMOS transistors P1 and P2. The sense amplifier 40 is a sense amplifier shared by both cell arrays 10 of the sense amplifier 40.

Although not shown, the semiconductor integrated circuit according to the related art includes an equalizing unit, a bit line isolation unit, and a column select transistor unit.

The equalizing unit equalizes the bit line BL and the bit bar line / BL according to a bit line equalizing signal BLEQ.

The bit line isolation unit branches the bit line pairs BL and / BL according to bit line isolation signals BISH and BISL.

The column select transistor unit transfers data carried on the bit line BL and the bit bar line / BL to segment input / output line pairs SIO and / SIO according to a column select signal Yi.

In the semiconductor integrated circuit according to the related art, the NMOS transistor and the PMOS transistor are disposed adjacent to each other to implement the sense amplifier 40. The NMOS transistor and the PMOS transistor may perform a tilt implant as an ion implant to prevent short channel effects. Each transistor requires a space between adjacent transistors due to the height of the material deposited in the vertical direction by a gate, a hard mask, or the like when performing the tilt implant. Moreover, when the well type of each transistor is different, the required space is further increased and process margin is further required.

Since the NMOS transistor and the PMOS transistor constituting the sense amplifier are formed in different types of wells, the required space is further increased. As such, when the tilt implant is performed to implement the sense amplifier in a limited space, there is a problem in that a shadowing effect that covers the implant region is formed by a material deposited thereon.

In addition, the higher the degree of integration, the greater the necessity of reducing the area of the semiconductor integrated circuit, and therefore, the necessity of reducing the area of the sense amplifier is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor integrated circuit capable of preventing shadow effects, increasing process margins, and reducing the area of a sense amplifier.

The semiconductor integrated circuit of the present invention for achieving the above technical problem is a cell array; A first latch unit connected to one side of the cell array through a bit line pair and configured of a first transmission element of the same type; And a second latch portion connected to the other side of the cell array through the bit line pair and configured of a second transmission element of a type different from the first latch portion, wherein the first latch portion and the second latch portion And sensing and amplifying data carried on the pair of bit lines.

In addition, another embodiment of a semiconductor integrated circuit according to the present invention includes a plurality of cell arrays; A plurality of first latch units composed of the same type of first transmission element; And a plurality of second latch portions formed of a second transmission element of a different type from the first latch portion, wherein the first latch portion and the second latch portion are alternately connected between each of the plurality of cell arrays, and each cell The array may amplify data of the plurality of cell arrays by the first latch unit and the second latch unit disposed at both sides.

In the semiconductor integrated circuit according to the present invention, the area occupied by the sense amplifier is reduced.

In addition, in the semiconductor integrated circuit according to the present invention, since different types of transistors are not disposed adjacent to each other, process margins can be improved, shadowing effects can be prevented, and further area reduction effects can be obtained.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a semiconductor integrated circuit in accordance with the present invention.

The semiconductor integrated circuit illustrated in FIG. 2 includes a plurality of cell arrays 100, a first latch unit 110, and a second latch unit 120.

The cell array 100 is connected to a pair of bit lines (the pair of bit lines includes a bit line BL and a bit bar line / BL).

The first latch unit 110 is connected to one side of the cell array 100 through the bit line pairs BL and / BL. The first latch unit 110 corresponds to an NMOS transistor among the transistors constituting the sense amplifier of FIG. 1.

The second latch unit 120 is connected to the other side of the cell array 100 through the bit line pairs BL and / BL. The second latch unit 120 is a configuration corresponding to a PMOS transistor among the transistors constituting the sense amplifier of FIG. 1.

The semiconductor integrated circuit according to the present invention senses and amplifies data carried on the bit line pair BL / BL by the first latch unit 110 and the second latch unit 120.

The first latch unit 110 includes a fourth NMOS transistor N4 and a fifth NMOS transistor N5.

The fourth NMOS transistor N4 has a gate connected to the bit bar line / BL, a drain connected to the second electrode SB, and a source connected to the bit line BL.

The fifth NMOS transistor N5 has a gate connected to the bit line BL, a drain connected to the second electrode SB, and a source connected to the bit bar line / BL.

The second latch unit 120 includes a first PMOS transistor P1 and a second PMOS transistor P2.

In the first PMOS transistor P1, a first electrode RTO is connected to a source, the bit line BL is connected to a drain, and the bit bar line / BL is connected to a gate.

In the second PMOS transistor P2, the first electrode RTO is connected to a source, the bit bar line / BL is connected to a drain, and the bit line BL is connected to a gate.

Although not illustrated in FIG. 2, the semiconductor integrated circuit according to the present invention may further include a precharging unit, an equalizing unit, and a column select transistor unit.

The equalizing unit equalizes the bit line pair BL // BL according to a bit line equalizing signal BLEQ.

The precharging unit precharges the bit line pair BL // BL to a bit line precharging voltage VBLP according to the bit line equalizing signal BLEQ.

The column select transistor unit transfers the data loaded on the bit line pair BL, / BL to the segment input / output line pair SIO, / SIO according to the column select signal Yi.

The operation of the semiconductor integrated circuit illustrated in FIG. 2 will be described below.

First, it is assumed that a case of amplifying data carried in the illustrated cell array 100 among the illustrated cell arrays 100 is assumed. In the active operation mode, as word lines are activated, data carried in cells in the cell array 100 are transferred to the bit line pairs BL and / BL. In addition, the first electrode RTO receives a core voltage and the second electrode SB receives a ground voltage. The voltage difference between the first electrode RTO and the second electrode SB is generated, and the fourth and fifth NMOS transistors N4 and N5 and the first and second PMOS transistors P1 and P2 are generated. Is activated. Therefore, the first latch unit 110 and the second latch unit 120 sense and amplify data carried on the bit line pair BL // BL.

In addition, in the precharging mode, the precharging unit precharges the voltage level of the pair of bit lines BL and / BL as the bit line equalizing signal BLEQ is activated.

In the read or write operation mode, when the column select signal Yi is enabled, the column select transistor unit connects the bit line pair BL, / BL and the segment input / output line pair SIO, / SIO.

In the prior art, if a sense amplifier is provided in one direction in both directions with respect to a cell array, the present invention is provided with the first latch unit 110 corresponding to one half of a conventional sense amplifier based on the cell array 100. On the other side, the second latch unit 120 corresponding to the other half of the conventional sense amplifier is provided.

In the semiconductor integrated circuit according to the present invention, the cell array 100, the first latch unit 110, the cell array 100, the second latch unit 120, the cell array 100, and the like are repeated in the same order. Can be implemented.

Therefore, the semiconductor integrated circuit according to the present invention can reduce the area occupied by the sense amplifier by about one-half compared to the prior art. In addition, the present invention improves the process margin and further reduces the area since it is not necessary to form different types of wells by arranging transistors of the same type while performing the amplification operation of the conventional sense amplifier. . In addition, the present invention can secure the space during the tilt implant can prevent the shadowing effect (shadowing effect).

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a semiconductor integrated circuit according to the prior art;

2 is a circuit diagram of a semiconductor integrated circuit according to the present invention.

<Description of Signs for Main Parts of Drawings>

10: cell array 40: sense amplifier

100: cell array 110: first latch portion

120: second latch portion

Claims (6)

Cell arrays; A first latch unit connected to one side of the cell array through a bit line pair and configured of a first transmission element of the same type; And A second latch part connected to the other side of the cell array through the bit line pair and configured of a second transmission element of a different type from the first latch part, wherein the first latch part and the second latch part are connected to each other by the second latch part. And sensing and amplifying data carried on a pair of bit lines. The method of claim 1, The first latch unit, A first transmission element configured to supply a voltage of a second electrode to the bit bar line of the bit line pair according to a voltage level of the bit line of the bit line pair; And And a second transfer element configured to supply the voltage of the second electrode to the bit line according to the voltage level of the bit bar line. The method of claim 1, The second latch unit, A first transmission element supplying a voltage of a first electrode to a bit bar line of the pair of bit lines according to the voltage level of the bit line; And And a second transfer element configured to supply a voltage of the first electrode to a bit line of the pair of bit lines according to the voltage level of the bit bar line. A plurality of cell arrays; A plurality of first latch units composed of the same type of first transmission element; And A plurality of second latches composed of a second transmission element of a different type from the first latch, The first latch unit and the second latch unit are alternately connected between the plurality of cell arrays, and each cell array is connected to each other by the first latch unit and the second latch unit disposed at both sides of the plurality of cell arrays. A semiconductor integrated circuit characterized by amplifying data. The method of claim 4, wherein The first latch unit, A first transmission element configured to supply a voltage of a second electrode to the bit bar line of the bit line pair according to a voltage level of a bit line among the bit line pairs connected to the cell array; And And a second transfer element configured to supply the voltage of the second electrode to the bit line according to the voltage level of the bit bar line. The method of claim 4, wherein The second latch unit, A first transmission element configured to supply a voltage of a first electrode to a bit bar line of the bit line pair according to a voltage level of a bit line among the pair of bit lines connected to the cell array; And And a second transfer element configured to supply a voltage of the first electrode to a bit line of the pair of bit lines according to the voltage level of the bit bar line.

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