KR20090090004A - Receiver of semiconductor integrated circuit - Google Patents

Receiver of semiconductor integrated circuit Download PDF

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Publication number
KR20090090004A
KR20090090004A KR1020080015211A KR20080015211A KR20090090004A KR 20090090004 A KR20090090004 A KR 20090090004A KR 1020080015211 A KR1020080015211 A KR 1020080015211A KR 20080015211 A KR20080015211 A KR 20080015211A KR 20090090004 A KR20090090004 A KR 20090090004A
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KR
South Korea
Prior art keywords
signal
code
response
termination
circuit
Prior art date
Application number
KR1020080015211A
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Korean (ko)
Inventor
강신덕
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to KR1020080015211A priority Critical patent/KR20090090004A/en
Publication of KR20090090004A publication Critical patent/KR20090090004A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Abstract

A receiving device of a semiconductor integrated circuit is provided to suppress the increase of the current consumption by increasing a termination resistance. An on die termination circuit(130) implements a first termination resistance and a second termination resistance value in response to the activation of at least one of an enable signal and a control signal. The on die termination circuit includes an or logic(131), a code shifter(132), a code selector(133), and a driver leg(134). A code shifter shifts the code signal in response to the activation of the control signal. The code selector outputs the output signal of the code shifter or the or logic according to the activation or non-activation of the control signal. The driver leg implements the first termination resistance and the second termination resistance according to the output signal of the code selector.

Description

RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to a receiving device of a semiconductor integrated circuit.

In general, a semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory) is provided with a receiving device for receiving various signals from the memory controller. The receiving device is provided with an on die termination circuit to improve the signal integrity of the receiving circuit and the receiving circuit (SI).

A configuration example of a receiving apparatus according to the prior art is shown in FIG.

As shown in FIG. 1, the receiving apparatus of the semiconductor integrated circuit 20 according to the related art includes a receiving circuit RX 21 connected to a transmitting circuit TX 11 of a memory controller such as the GPU 10. And a 120Ω ODT 22 and a 240Ω ODT 23 as an On Die Termination Circuit (OTT) connected to the receiving circuit 21.

By selectively operating the 120Ω ODT 22 and the 240Ω ODT 23, the termination resistance of the receiver circuit 21 may be 120Ω, 240Ω, or 80Ω.

However, in the case of a semiconductor integrated circuit according to the related art, in particular, a semiconductor memory used for a mobile device, the signal preservation performance is deteriorated because the signal reception operation is performed while the on die termination circuit is turned off to reduce current, which is the most important performance index. There is a problem.

It is an object of the present invention to provide a receiving device of a semiconductor integrated circuit capable of improving signal integrity while minimizing current consumption.

A receiving device of a semiconductor integrated circuit according to the present invention includes a receiving circuit; And an on-die termination circuit configured to selectively implement a termination resistance of the receiving circuit among a first termination resistance value and a second termination resistance value in response to activation of at least one of an enable signal and a control signal. do.

A receiving device of a semiconductor integrated circuit according to the present invention includes a receiving circuit; And set the termination resistor of the receive circuit to a first termination resistor value in response to the activation of the enable signal and to set the termination resistor of the receive circuit to a second termination resistor value in response to the deactivation of the enable signal. Another feature is the provision of a die termination circuit.

Since the receiving device of the semiconductor integrated circuit according to the present invention can greatly increase the termination resistance value as necessary, it is possible to increase the signal integrity while suppressing the increase in the consumption current to improve the high-speed operation stability of the semiconductor integrated circuit.

Hereinafter, a preferred embodiment of a reception device for a semiconductor integrated circuit according to the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 2, a receiving device of a semiconductor integrated circuit according to the present invention includes a receiving circuit (RX) 110, a first on die termination circuit (ODT1) 120, and a second on die termination circuit (ODT2). 130 is provided.

The receiving circuit 110 is connected to a memory controller, that is, the transmitting circuit 11 of the GPU 10 through a signal line.

As illustrated in FIG. 3, the first on die termination circuit 120 inputs a code signal pcode <0: 5> to the driver legs 122 according to the first enable signal enb1. It is configured to implement the termination resistance value 120Ω.

As shown in FIG. 3, the first on die termination circuit 120 includes a logic sum logic 121 and a driver leg 122.

The logic sum logic 121 includes a plurality of NOR gates NR1 to NR6 and a plurality of inverters IV1 to IV6 respectively receiving output signals of the plurality of NOR gates NR1 to NR6. The plurality of NOR gates NR1 to NR6 receive the code signal pcode <0: 5> at a first input terminal and the first enable signal enb1 in common at a second input terminal.

The driver leg 122 includes a plurality of transistors WP / 4 to WP * 8 connected to a power supply terminal and a plurality of resistors RP * 64 to RP connected between the plurality of transistors WP / 4 to WP * 8 and an output terminal. * 2). The output signals pcode1 <0: 5> of the logic sum logic 121 are input to gates of the plurality of transistors WP / 4 to WP * 8. The plurality of resistors RP * 64 to RP * 2 are selectively operated according to the output signal pcode1 <0: 5> of the logic sum logic 121 to implement the first termination resistance value 120Ω. . The numerals given to the signs of the plurality of transistors WP / 4 to WP * 8 represent a magnification of the width. The numerals given to the codes of the plurality of resistors RP * 64 to RP * 2 represent the resistance values.

As illustrated in FIG. 4, the second on die termination circuit 130 uses a code signal pcode <0: 5> in response to the activation of the second enable signal enb2 to generate a second termination resistance value. (240Ω) or the code signal (pcode <0: 5>) is shifted in response to the activation of the shift control signal (shift) to implement the third termination resistance value (480Ω).

As illustrated in FIG. 4, the second on die termination circuit 130 includes an OR logic 131, a code shifter 132, a code selector 133, and a driver leg 134.

The logic sum logic 131 includes a plurality of NOR gates NR11 to NR16 and a plurality of inverters IV11 to IV16 respectively receiving output signals of the plurality of NOR gates NR11 to NR16. The plurality of NOR gates NR11 to NR16 receive the code signal pcode <0: 5> at a first input terminal and a second enable signal enb2 in common at a second input terminal.

The code shifter 132 is configured to shift and output the code signal pcode <0: 5> by a predetermined bit in response to the activation of the shift control signal shift.

As illustrated in FIG. 5, the code shifter 132 includes a plurality of pass gates PG21 to PG26 ′ and an inverter IV21. The code shifter 132 has a plurality of multiplexer structures. That is, each of the plurality of pass gate pairs PG21 / PG21 'to PG26 / PG26' forms a multiplexer structure. Any one of two pass gates constituting the plurality of pass gate pairs PG21 / PG21 'to PG26 / PG26' is selected in response to the shift control signal, and an input of the selected pass gate is output. It is composed. The code signal pcode <0: 5> is input to a first group PG21 to PG26 among the plurality of pass gates PG21 to PG26 ', and the code signal to a second group PG21' to PG26 '. A code signal pcode <1: 5> obtained by shifting (pcode <0: 5>) by one bit is input, and a power supply voltage vvd is applied to the last pass gate PG26Ω. 5 illustrates an example in which the code shifter 132 is configured to perform a 1-bit shifting operation. As shown in the diagram on the right side of FIG. 5, a third termination resistance value 480Ω may be implemented through 1-bit shifting. Can be. The shifting operation of two or more bits may be performed according to a code signal input to the second group PG21 'to PG26' among the plurality of pass gates PG21 to PG26 '. When the code signal pcode <0: 5> is shifted 2 bits, the termination resistance value may be implemented as 960Ω.

The code selector 133 selects an output of the OR logic 131 when the shift control signal is activated, outputs the result to the driver leg 134, and when the shift control signal is inactivated, And select an output of the code shifter 132 to output to the driver leg 134.

As illustrated in FIG. 6, the code selector 133 includes a plurality of pass gates PG41 to PG46 ′ and an inverter IV41. In the code selector 133, each of the plurality of pass gate pairs PG41 / PG41 ′ to PG46 / PG46 ′ forms a multiplexer structure. One of the two pass gates constituting the plurality of pass gate pairs PG41 / PG41 ′ to PG46 / PG46 ′ is selected in response to the shift control signal, and an input of the selected pass gate is output. It is composed. The output signal pcode2 <0: 5> of the logical sum logic 131 is input to the first group PG41 to PG46 among the plurality of pass gates PG41 to PG46 ', and the second group PG41' to PG46 is input. The output signal pcode3 <0: 5> of the code shifter 132 is input to ').

The driver leg 134 includes a plurality of transistors WP / 8 to WP * 4 connected to a power supply terminal and a plurality of resistors RP * 128 to RP connected between the plurality of transistors WP / 8 to WP * 4 and an output terminal. * 4). The output signals scode <0: 5> of the code selector 133 are input to gates of the plurality of transistors WP / 8 to WP * 4. The plurality of resistors RP * 128 to RP * 4 may be selectively operated according to the output signal scode <0: 5> of the code selector 133 so that the second termination resistance value 240Ω or the third Termination resistance value (480Ω) is implemented. The numerals given to the signs of the plurality of transistors WP / 8 to WP * 4 represent a magnification of the width. The numerals given to the signs of the plurality of resistors RP * 128 to RP * 4 represent the resistance values.

The operation of the receiving apparatus of the semiconductor integrated circuit according to the present invention configured as described above is as follows.

The first enable signal enb1 and the second enable signal enb2 are activated at a low level, and the shift control signal shift is a signal activated at a high level. The first enable signal enb1, the second enable signal enb2, and the shift control signal shift may be in a state suitable for an operating condition using a mode register set (MRS) or an extended mode register set (EMRS). Can be programmed.

When the normal on die termination operation is performed, the first enable signal enb1 and the second enable signal enb2 are selectively activated to set a termination resistance value of 120Ω, 240Ω, or 80Ω. The shift control signal shift may be activated as needed when the second enable signal enb2 is deactivated. In this case, the termination resistance value may be set to 480 Ω.

For example, when the first enable signal enb1 is activated and the second enable signal enb2 is deactivated, the driver leg 122 of the first on die termination circuit 120 of FIG. 3 is code signal pcode1. <0: 5>), the termination resistance value of the receiving circuit 110 is set to 120Ω accordingly. When the shift control signal shift is in an inactive state, the code selector 133 of FIG. 4 selects the output of the OR logic 131, but the output signal pcode2 <0: 5 of the OR logic 131. Since>) are all at the high level, all the transistors WP / 8 to WP * 4 of the driver leg 134 are turned off.

The receiving circuit 110 of FIG. 2 performs a signal receiving operation according to the set termination resistance value.

Meanwhile, when the on die termination operation is to be stopped, both the first enable signal enb1 and the second enable signal enb2 are deactivated. At this time, when the shift control signal (shift) is activated, the second on die termination circuit 130 is operated and the termination resistance value is set variable from 240Ω to 480Ω.

That is, since the first enable signal enb1 is inactivated, all the transistors WP / 4 to WP * 8 of the driver leg 122 of the first on die termination circuit 120 are turned off.

On the other hand, since the second enable signal enb2 is inactive and the shift control signal shift is activated, the code shifter 132 of the second on die termination circuit 130 of FIG. 4 has a code signal pcode <0: 5>) is output by shifting 1 bit.

Since the shift control signal shift is activated, the code selector 133 selects the output signal pcode3 <0: 5> of the code shifter 132 and outputs it to the driver leg 134.

The driver leg 134 receives the output signal pcode3 <0: 5> of the code shifter 132, and accordingly, the termination resistance of the receiving circuit 110 is set to 480 Ω.

The receiving circuit 110 of FIG. 2 performs a signal receiving operation according to the termination resistance value set to 480Ω.

On the other hand, it is also possible to set the termination resistance value to 96Ω when the first enable signal enb1 and the shift control signal shift are activated.

In the above-described embodiment of the present invention, in order to minimize current consumption, the termination resistance value is changed in an operation mode in which both of the first enable signal enb1 and the second enable signal enb2 are inactivated to stop the on die termination operation. By greatly increasing the current consumption is to suppress the maximum and improve the signal integrity performance. It can also be used to implement a wider variety of termination resistors, even in normal on-die termination mode of operation, as needed.

As described above, since the signal reception operation is performed in a state in which the termination resistance is greatly increased to 480 Ω according to the present invention, signal preservation performance can be improved in the state in which the increase in current consumption is suppressed as much as possible. Is shown. Referring to FIG. 7, it can be seen that the signal preservation performance is improved in the case of the present invention (b) as compared with the conventional technique (a) of performing the signal reception without using the on die termination function.

Hereinafter, a reception device of a semiconductor integrated circuit according to another embodiment of the present invention will be described.

Another embodiment of the present invention is configured to operate by varying the termination resistance value of the receiving circuit 110 to the maximum value automatically in the operation mode to turn off the on die termination function.

In another embodiment of the present invention, as shown in FIG. 8, the configuration of the second on die termination circuit 130 ′ is changed.

The second on die termination circuit 130 'includes a code shifter 132' and a driver leg 134 ', as shown in FIG.

The code shifter 132 ′ may be configured in the same manner as the code shifter 132 of FIG. 5 except for using the second enable signal enb2 instead of the shift control signal shift as illustrated in FIG. 10. Can be.

The driver leg 134 ′ may be configured in the same manner as the driver leg 134 of FIG. 4.

Since the code shifter 132 ′ uses the second enable signal enb2 as a signal for controlling the code shifting operation, when the second enable signal enb2 is activated in the normal on die termination operation mode, the code shifter 132 ′ is inputted. Outputs the code signals pcode <0: 5> without shifting them.

The termination resistance value of the driver leg 134 'is set to 240 Ω according to the output signal scode <0: 5> of the code shifter 132'.

On the other hand, when the on-die termination operation is stopped, the second enable signal enb2 is inactivated, so the code shifter 132 ′ shifts the input code signal pcode <0: 5> by one bit and outputs it.

The termination resistance value of the driver leg 134 'is set to 480Ω in accordance with the output signal scode <0: 5> of the code shifter 132'.

As described above, another embodiment of the present invention uses the second enable signal enb2 as a signal for controlling the shifting operation of the code shifter 132 ', thereby activating the second enable signal enb2. Depending on whether or not normal on-die termination operation or the termination resistance value adjustment for improved signal integrity performance is automatically switched, the circuit configuration can be simplified compared to the previous embodiment.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a receiving apparatus of a semiconductor integrated circuit according to the prior art;

2 is a block diagram of a receiving device of a semiconductor integrated circuit according to an embodiment of the present invention;

3 is a circuit diagram of a first on die termination circuit of FIG. 2;

4 is a circuit diagram of a second on die termination circuit of FIG. 2;

5 is a circuit diagram of the code shifter of FIG. 4;

6 is a circuit diagram of a code selector of FIG. 4;

7 is a simulation waveform diagram of a receiving device according to the present invention;

8 is a block diagram of a receiving device of a semiconductor integrated circuit according to another embodiment of the present invention;

9 is a circuit diagram of a second on die termination circuit of FIG. 8;

10 is a circuit diagram of the code shifter of FIG. 9.

<Description of Symbols for Main Parts of Drawings>

110: receiving circuit 120: first on die termination circuit

121, 131: logical OR logic 122, 134: driver leg

130, 130: second on die termination circuit

132, 132: code shifter 133: code selector

Claims (17)

Receiving circuit; And An on-die termination circuit configured to selectively implement a termination resistance of the receiving circuit among a first termination resistance value and a second termination resistance value in response to activation of at least one of an enable signal and a control signal. Receiving device. The method of claim 1, The on die termination circuit is And implement the first termination resistance value by using a code signal in response to the activation of the enable signal or by shifting the code signal in response to the activation of the control signal. A receiver for a semiconductor integrated circuit. The method of claim 2, The on die termination circuit is OR logic for ORing the code signal and the enable signal, A code shifter for shifting and outputting the code signal in response to activation of the control signal; A code selector configured to select and output an output signal of the OR logic code or an output signal of a code shifter according to whether the control signal is activated; And a driver leg for implementing the first termination resistance value or the second termination resistance value according to an output signal of the code selector. The method of claim 3, wherein The logical OR logic is And each bit of the code signal is ORed with the enable signal. The method of claim 3, wherein The code shifter And a multiplexer configured to output the code signal in response to the deactivation of the control signal, and output a code signal corresponding to the shift of the code signal by a predetermined bit in response to the activation of the control signal. Receiver of integrated circuit. The method of claim 5, wherein The multiplexer The code signal is input to a first group of transmission elements operating in response to deactivation of the control signal among the plurality of transmission elements, and activation of the control signal among the plurality of transmission elements. And a code signal corresponding to the shift of the code signal by a predetermined bit is input to the second group of transfer elements operating in response to the response. The method of claim 3, wherein The code selector And a multiplexer configured to select and output an output signal of the logic sum logic in response to deactivation of the control signal, and to select and output an output signal of the code shifter in response to activation of the control signal. Receiving device of the circuit. The method of claim 7, wherein The multiplexer An output signal of the logic sum logic is input to a first group of transfer elements operating in response to deactivation of the control signal among the plurality of transfer elements, and the control signal is input from the plurality of transfer elements. And the output signal of the code shifter is input to the second group of transfer elements operating in response to the activation of the signal. The method of claim 3, wherein The driver leg And a plurality of transistors connected to a power supply terminal and a plurality of resistors connected between the plurality of transistors and an output terminal, wherein the output signal of the code selector is input to a gate of the plurality of transistors. . The method of claim 2, And a second on die termination circuit configured to implement a third termination resistance value using the code signal in response to activation of a second enable signal. The method of claim 10, And the second termination resistor value is set to be the largest among the first to third termination resistor values. Receiving circuit; And An on die configured to set a termination resistor of the receive circuit to a first termination resistor value in response to an activation of an enable signal and to set a termination resistor of the receive circuit to a second termination resistor value in response to deactivation of the enable signal A receiving device of a semiconductor integrated circuit having a termination circuit. The method of claim 12, The on die termination circuit is A code shifter for outputting a code signal in response to activation of the enable signal, and shifting and outputting the code signal in response to deactivation of the enable signal; And a driver leg for implementing the first termination resistance value or the second termination resistance value according to the output signal of the code shifter. The method of claim 13, The code shifter The code signal is input to a first group of transmission elements including a plurality of transmission elements and operating in response to deactivation of the enable signal among the plurality of transmission elements, and the enable signal among the plurality of transmission elements. And a code signal corresponding to the shift of the code signal by a predetermined bit is input to the second group of transfer elements operating in response to activation of the semiconductor integrated circuit. The method of claim 13, The driver leg And a plurality of transistors connected to a power supply terminal and a plurality of resistors connected between the plurality of transistors and an output terminal, wherein the output signal of the code shifter is input to the gates of the plurality of transistors. . The method of claim 13, And a second on die termination circuit configured to implement a third termination resistance value using the code signal in response to activation of a second enable signal. The method of claim 16, And the second termination resistor value is set to be the largest among the first to third termination resistor values.
KR1020080015211A 2008-02-20 2008-02-20 Receiver of semiconductor integrated circuit KR20090090004A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11302384B2 (en) 2019-12-05 2022-04-12 Samsung Electronics Co., Ltd. Method of controlling on-die termination and memory system performing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11302384B2 (en) 2019-12-05 2022-04-12 Samsung Electronics Co., Ltd. Method of controlling on-die termination and memory system performing the same

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