KR20090086730A - Method of interleaving in wireless communication system - Google Patents

Abstract

An interleaving method in a wireless communication system is provided to secure flexibility in designing a turbo encoder by excluding a separate table for parameters for interleaving. A turbo encoder(300) includes a first constituent encoder(310), a second constituent encoder(320), and an internal interleaver(330). The first constituent encoder receives information bits, and outputs first parity bits. The internal interleaver interleaves the information bits. The second constituent encoder receives bits outputted in the internal interleaver, and outputs second parity bits. The internal interleaver interleaves the information bits by using a fixing parameter and a circulation parameter.

Description

Interleaving method in wireless communication system {Method of interleaving in wireless communication system}

The present invention relates to wireless communication, and more particularly, to an interleaving method in a wireless communication system.

Digital signals are transmitted through various propagation paths in a wireless communication system. One technique for correcting errors due to propagation paths is an error correction technique. The error correction technique adds an extra code to the data so that the corrected data is restored even if the data contains errors.

One of the error correction techniques is the turbo code. The classic turbo code uses a duo-binary recursive systematic convilutional code on one input. In the classic turbo code, a non-binary turbo code is introduced that processes multiple inputs simultaneously, instead of only processing one input at a time.

One of the non-binary turbo codes, convolutional turbo code (CTC), was approved in 2004 by the Institute of Electrical and Electronics Engineers (IEEE) Standard for Local and metropolitan area networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems. Channel codes used in the following (IEEE 802.16-2004) standard. The CTC encoder has a structure in which a double binary recursive systematic convolutional code is connected through an internal interleaver. The performance of a CTC encoder depends on the characteristics of the internal interleaver.

A general interleaver is expressed as

Where N is an interleaving depth, i is an index of an interleaving sequence, and j is an index of an interleaved sequence. An interleaving sequence u ₁ (i) having an index i is mapped to an interleaved sequence u ₂ (j) having an index j by π (·). That is, u ₂ (j) = u ₁ (i) can be represented.

In general, the internal interleaver of the CTC encoder uses ARP (Almost Regular Permutation).

Here, P and N are relatively prime with each other, and D (j) is a constant added periodically according to the index j. '%' Represents a modulo operation. If the period of D (j) is C, then C must be a divisor of N. In general, period C is selected from 4, 8 or 12 depending on the size of N.

According to the IEEE 802.16-2004 standard section 8.4.9.2.3.2, the internal interleaver of the CTC encoder uses the following ARP.

Here, j = 0, ..., N-1, D (j) has a period C of 4, and four parameters P ₀ , P ₁ , P ₂ , and P ₃ depend on the interleaving length N. The values of parameters P ₀ , P ₁ , P ₂ , and P ₃ shown in the IEEE 802.16-2004 standard section 8.4.9.2.3.1 are shown in the following table.

The values of parameters P ₀ , P ₁ , P ₂ , and P ₃ must be stored in memory in table form according to the interleaving length N. That is, a CTC encoder using ARP as an internal interleaver should have four parameters optimized according to the possible data block size to ensure performance. However, as the number of possible data block sizes increases, the total number of parameters increases and thus the required memory usage increases. In addition, since the parameter is determined according to the data block size, it is difficult to change the size of the data block except the predefined data block size after the parameter is determined.

An object of the present invention is to provide an interleaving method and apparatus for reducing memory usage.

An interleaving method according to an aspect of the present invention includes obtaining a fixed parameter P that is interleaved with an interleaving length N, and using the interleaving length N, the cyclic parameters P ₀ , P having the number of periods C which is a divisor of the interleaving length N. Obtaining ₁ , ..., P _{C -1} , and using the fixed parameter P, the interleaving length N and the cyclic parameters P ₀ , P ₁ , ..., P _{C -1} for information bits Interleaving.

According to another aspect of the present invention, a turbo encoder may include a first component encoder that receives information bits and outputs first parity bits, an internal interleaver that interleaves the information bits, and a second parity bit that receives the bits output from the internal interleaver. And a second component encoder for outputting them. The internal interleaver interleaves using the interleaving length N and the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} having a fixed parameter P swept from each other and a number of periods C which is a divisor of the interleaving length N.

All parameters needed to perform ARP are calculated directly from the interleaving length. There is no need for a separate table for parameters, which can reduce memory usage. In addition, the interleaving length is not limited, thereby providing flexibility in turbo encoder design.

The following techniques may be used for downlink or uplink. Downlink means communication from a base station to a user equipment, and uplink means communication from a terminal to a base station. A base station generally refers to a fixed station for communicating with a terminal, and may be referred to as other terminology such as a node-B, a base transceiver system (BTS), or an access point. . The terminal may be fixed or mobile and may be referred to in other terms such as mobile station (MS), user terminal (UT), subscriber station (SS), wireless device (wireless device), and the like.

1 is a block diagram illustrating a transmitter and a receiver according to an embodiment of the present invention. In downlink, the transmitter 100 may be part of a base station, and the receiver 200 may be part of a terminal. In uplink, the transmitter 100 may be part of a terminal, and the receiver 200 may be part of a base station. The base station may include a plurality of receivers and a plurality of transmitters. The terminal may include a plurality of receivers and a plurality of transmitters.

Referring to FIG. 1, the transmitter 100 includes a channel encoder 120 and a transmit circuitry 150. The channel encoder 120 encodes the input information bits according to a coding scheme to form coded bits. The channel encoder 120 may be a turbo encoder or a convolutional turbo code (CTC) encoder. The transmission circuit 150 modulates the encoded data into a radio signal and transmits it to one or more receivers 200 through the antenna 190.

The receiver 200 includes a channel decoder 220 and a receive circuitry 250. The receiving circuit 250 converts the radio signal received from the antenna 290 into a digital signal. The channel decoder 220 decodes the demodulated digital signal according to a predetermined decoding scheme.

2 is a block diagram illustrating a turbo encoder according to an embodiment of the present invention.

Referring to FIG. 2, the turbo encoder 300 includes a first constituent encoder 310, a second constituent encoder 320, and an internal interleaver 330. The first component encoder 310 generates first parity bits from the information bits. The second component encoder 320 generates second parity bits from the pair of bits output to the internal interleaver 330. The first constituent encoder 310 and the second constituent encoder 320 may be a duo-binary recursive systematic convolution code having the same structure. The internal interleaver 330 interleaves the input information bits using Almost Regular Permutation (ARP).

A general interleaver is expressed as

Where N is the interleaving depth, i is the index of the interleaving sequence, and j is the index of the interleaved sequence. An interleaving sequence u ₁ (i) having an index i is mapped to an interleaved sequence u ₂ (j) having an index j by π (·). That is, u ₂ (j) = u ₁ (i = Π (j)). For example, when a pair of bits (A, B) are input to the interleaver, the interleaving sequence u ₁ = [u ₁ (0), u ₁ (1), ... u ₁ (N-1)] Let's define When j is n, the element of the interleaving sequence with the corresponding index i _n is u ₁ (i _n ; j = n), u ₂ = [u ₁ (Π (0)), u ₁ (Π (1 )), ..., u ₁ (Π (N-1))].

The internal interleaver 330 uses ARP expressed as follows.

Here, the fixed parameter P and the interleaving length N are relatively prime with each other, and D (j) is a constant that is periodically added according to the index j. '%' Represents a modulo operation. If the period of D (j) is C, then C must be a divisor of N. In general, period C is selected from 4, 8 or 12 depending on the size of N.

First, the interleaving length N (or data block size) required for turbo encoding is selected, and two prime numbers p ₁ and p ₂ are selected. The set of possible a turbo encoding interleaving length, there is only the p ₂ p _1, and each drain, is a multiple of both p ₁ and p ₂ does not exist, select p ₁ and p _2.

The fixed parameter P, which is a relatively prime number, is chosen as follows.

Since interleaving length N generally takes one of multiples of 4, 8 and 12, N / 2 + p and N are always relatively prime to each other, unless N is a multiple of prime p. For example, let N = 264, consider p ₁ = 11 as a divisor of N and a prime number. Therefore, N% p ₁ = 264% 11 = 0. Since p ₂ must not be a divisor of N, we take p ₂ = 13. At this time, N = 264 and N / 2 + p ₂ = 264/2 + 13 are small to each other.

[theorem]

If A and B are cows of each other, then A ± B and B are cows of each other.

n)이 되어, A도 B와 마찬가지로 p의 배수가 되어야 한다. 이는 A와 B가 서로 소라는 조건에 모순되므로, A±B와 B는 서로 소이다.The theorem can be proved as follows. If A and B are small to each other, but A ± B and B are not small to each other, there are integers m, n and p with A ± B = pm and B = pn. Since A ± B = A ± pn = pm, A = p (m

n), and A must be a multiple of p like B. This contradicts the condition that A and B are each other, so A ± B and B are each other.

Using this theorem, N- (N / 2 + p) = N / 2-p must also be primed with N / 2 + p so that N and N / 2 + p are primed with each other. In addition, N / 2-p- (N / 2 + p) =-2p must also be small with N / 2 + p. When N is a multiple of four, N / 2 + p is always odd. N / 2 + p must be a multiple of p to be non-small to -2p. Therefore, if N is not a multiple of 2p, N and N / 2 + p are always small with each other. Therefore, if N is a multiple of p ₁ in Equation 6, P = N / 2 + p ₂ is selected.

In one embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} of ARP may be obtained as follows.

Here, T is an arbitrary integer, and m (j% C) is a function of mapping C zero to T-1 integers according to the result of j% C. floor (x) means an integer smaller than x. The second term on the right side of the equation ensures that P _{j % C} is always a multiple of C.

In another embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C -1} of ARP can be obtained as follows.

Here, ceil (x) means an integer greater than x.

In another embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} of ARP may be obtained as follows.

Here, round (x) means the integer which rounded x.

In another embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} of ARP may be obtained as follows.

Where K is any integer.

In another embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} of ARP may be obtained as follows.

In another embodiment, the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} of ARP may be obtained as follows.

All parameters necessary for performing ARP in various ways as described above can be obtained from the interleaving length N. Interleaving is performed through Equation 5 by using the fixed parameter P and the cyclic parameters P ₀ , P ₁ ,..., P _{C - 1} obtained above.

For example, suppose p ₁ = 11 and p ₂ = 13, and let C = 4, T = 4, and K = 0. m (j% 4) = {0, 3, 1, 2}. At this time, the relative prime number P is P = N / 2 + 11 if N% 11 is not 0, and P = N / 2 + 13 if 0. When using Equation 7, P ₀ , P ₁ , P ₂ , and P ₃ are as follows. P ₀ = 0, P ₁ = N × 3 / 4- (N × 3/4)% 4, P ₂ = N / 4-(N × 1/4)% 4, P ₃ = N / 2-(N 2/4)% 4. Interleaving is performed as follows from the obtained parameters.

Here, j = 0, ..., N-1.

From the interleaving length N, a parameter to be used for ARP is obtained through a certain rule. Therefore, a separate table for parameters is not necessary, thereby reducing memory usage. In addition, there is no restriction on the interleaving length N, thereby providing flexibility in turbo encoder design.

3 is a block diagram illustrating a CTC encoder according to an embodiment of the present invention.

Referring to FIG. 3, the CTC encoder 400 includes a first component encoder 410, a second component encoder 420, and an internal interleaver 430. The internal interleaver 430 interleaves the information bits inputted one by one using Almost Regular Permutation (ARP). The first configuration encoder 410 generates the first parity bits Y ₁ , W ₁ from the information bits A, B. The polynomial of bit string Y ₁ is 1 + D ² + D ³ , and the polynomial of bit string W ₁ is 1 + D ³ . The second component encoder 420 generates second parity bits Y ₂ and W ₂ from the pair of bits output to the internal interleaver 330. The polynomial of bit string Y ₂ is 1 + D ² + D ³ and the polynomial of bit string W ₂ is 1 + D ³ . The first component encoder 310 and the second component encoder 320 are double binary recursive organizational convolutional codes having the same structure. The parity bits provided by the first component encoder 410 and the second component encoder 420 are two, respectively, but the number of parity bits provided by the first component encoder 410 or the second component encoder 420 is not limited. .

The internal interleaver 430 performs the following two steps.

In a first step, a pair of information bits input to the internal interleaver 430 are interchanged. That is, the input sequence of interleaving length N input to the internal interleaver 430 u ₀ = [(A ₀ , B ₀ ), (A ₁ , B ₁ ), (A ₂ , B ₂ ), ..., (A _{N -1} , B _{N -1} )]. That is, element u ₀ (i) = (A _j , B _j ) of the input sequence u ₀ for index i. In order to exchange the pair of information bits constituting the elements of the input sequence u0, they are exchanged when the value of i% 2 is 1 and not when the value of i% 2 is 0. This allows for interleaving seqeunce u ₁ = [(A ₀ , B ₀ ), (B ₁ , A ₁ ), (A ₂ , B ₂ ), (B ₃ , A ₃ ), ..., (B _{N -1} , A _{N -1} )].

In the second step, it calculates a value corresponding to the index i of the interleaved sequence u ₁ that is mapped to the index j of the sequence (interleaved sequence) u ₂ interleaving using the equation (13). That is, u ₂ (j) = u ₁ (i = Π (j)) and u ₂ = [(A _{Π (0)} , B _{Π (0)} ), (A _{Π (1)} , B _{Π (1 )} ), (A _{Π (2)} , B _{Π (2)} ), ..., (A _{Π (N-1)} , B _{Π (N-1)} )].

The invention can be implemented in hardware, software or a combination thereof. In hardware implementation, an application specific integrated circuit (ASIC), a digital signal processing (DSP), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, and a microprocessor are designed to perform the above functions. , Other electronic units, or a combination thereof. In the software implementation, the module may be implemented as a module that performs the above-described function. The software may be stored in a memory unit and executed by a processor. The memory unit or processor may employ various means well known to those skilled in the art.

Although the present invention has been described above with reference to the embodiments, it will be apparent to those skilled in the art that the present invention may be modified and changed in various ways without departing from the spirit and scope of the present invention. I can understand. Therefore, the present invention is not limited to the above-described embodiment, and the present invention will include all embodiments within the scope of the following claims.

1 is a block diagram illustrating a transmitter and a receiver according to an embodiment of the present invention.

2 is a block diagram illustrating a turbo encoder according to an embodiment of the present invention.

3 is a block diagram illustrating a CTC encoder according to an embodiment of the present invention.

Claims (5)

Obtaining a fixed parameter P that is interleaved with the interleaving length N; Obtaining cyclic parameters P ₀ , P ₁ ,..., P _{C −1} having the number of periods C, which is a divisor of the interleaving length N, using the interleaving length N; And Interleaving for information bits using the fixed parameter P, the interleaving length N and the cyclic parameters P ₀ , P ₁ ,..., P _{C −1} . The method of claim 1, And the information bits are interleaved in pairs of two. The method of claim 1, The relative prime number P is obtained by the following equation.

Where p ₁ and p ₂ are prime and the interleaving length N is a multiple of p ₁ or p ₂ . The interleaving method of claim 1, wherein the recursive parameters P ₀ , P ₁ ,..., P _{C −1} are obtained as follows.

Here, T is an arbitrary integer, and m (j% C) is a function of mapping C zero to T-1 integers according to the result of j% C. A first component encoder which receives information bits and outputs first parity bits; An internal interleaver for interleaving the information bits; And A second component encoder which receives the bits output from the internal interleaver and outputs second parity bits; The internal interleaver may interleave using the interleaving length N and the cyclic parameters P ₀ , P ₁ ,..., P _C-1 having a fixed parameter P swept from each other and a number of periods C which is a divisor of the interleaving length N. Featuring turbo encoder.

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