KR20090081876A - Layout of NAND flash memory for formation of interconnection pad using self aligned double patterning - Google Patents

Abstract

A layout of a NAND flash memory for forming a connection pad using a self alignment double patterning is provided to simplify a trimming process and to reduce an error of pattern formation. A layout of a NAND flash memory is used for the self alignment double patterning process. The layout of the NAND flash memory includes a cell area, a peripheral circuit area, and a connection area between the cell area and the peripheral circuit area. The connection area includes a connection pattern(40). The connection pattern includes a plurality of first connection patterns(41) and second connection patterns(42). The plurality of first connection patterns progress to a first direction. The second connection pattern is positioned between the first connection patterns by the self alignment. The second connection pattern includes a connection pad(42a) which is arranged in plural rows to the second direction. The connection pad in the same row is arranged in the second connection pattern every other pad. The end of the second connection pattern is extended to the same position to the first direction.

Description

Layout of NAND flash memory for formation of interconnection pad using self aligned double patterning}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a layout of a connection area connecting a cell area and a page buffer area of a NAND flash memory.

NAND flash memory has a relatively high degree of integration due to a structure in which a plurality of memory cells are connected in series. However, recently, it is required to further reduce the design rule of NAND flash memory in order to shrink the chip size. In addition, as the design rule decreases, the minimum pitch of the patterns required to form the NAND flash memory is also greatly reduced. Various pattern forming methods have been applied to implement the fine pattern according to the reduced design rule.

In particular, a double patterning technique has been proposed in order to implement a small pitch cell array structure that is difficult to implement with only the exposure equipment and exposure technology developed so far. In the double patterning technique, after forming the primary pattern, a secondary pattern is formed between the primary patterns. Among the double patterning techniques, a Self Aligned Double Patterning (SADP) technique may be used, in which a secondary pattern is formed by self-alignment by a primary pattern.

In general, the peripheral circuit region is formed of various patterns with a larger pitch than the cell region, and thus is formed by a single exposure technology (SET). The intermediate connection pattern connecting the cell pattern and the peripheral circuit pattern may be formed by a self-aligned double patterning technique similarly to the cell pattern, in which case a trimming process is performed to remove unnecessary patterns among the connection patterns.

As the cell pattern becomes smaller, the connection pattern becomes more fine and complicated. Therefore, when the connection pattern is formed by the self-aligned double patterning process, there are many restrictions on the formation of the secondary pattern, and the trimming layout for removing unnecessary portions of the secondary pattern has a very complicated structure. Complex trimming layouts can make it difficult to remove unnecessary patterns.

FIG. 1 is a layout diagram of a connection pattern 10 and a trimming pattern 20 when a connection pattern connecting a cell bit line pattern and a page buffer pattern is formed by a self-aligned double patterning process. The layout of the connection pattern 10 of FIG. 1 is a layout of a stage in which a trimming process is performed to complete the connection pattern. Here, the connection pattern 12 having the connection pads 12a formed thereon is formed as a secondary pattern. The layout of the trimming pattern 20 is for removing unnecessary portions of the secondary connection pattern 12.

2 is a planar SEM photograph of the connection pattern after the trimming process is performed. The secondary connection pattern 12 having the connection pads 12a connected to the upper cell patterns is not extended to the lower page buffer, but is connected to the connection pads 12a through the upper wiring. Connected to the page buffer.

However, the trimming pattern 20 of FIG. 1 has a complicated layout reflecting the arrangement of the connection pads 12a, which makes the trimming process difficult and may cause an error in pattern formation.

SUMMARY OF THE INVENTION An object of the present invention is to use a layout of a connection pattern and a layout of a connection pattern for easily forming a trimming pattern when a connection pattern including a connection pad is formed between a cell area and a page buffer area by a align double patterning process. It is to provide a method of forming a connection pattern.

One type of layout of a NAND flash memory for achieving the object of the present invention is used in a self-aligned double patterning process, and includes a cell region, a peripheral circuit region and a connection region between the cell region and the peripheral circuit region. The connection region may include a plurality of primary connection patterns traveling in a first direction and secondary connection patterns formed by self-alignment between the primary connection patterns, and connection pads arranged in a plurality of rows in a second direction. . In this case, the connection pads in the same row are disposed every other adjacent second connection pattern. An end of the secondary connection pattern extends to the same position in the first direction.

The connection pattern electrically connects the cell pattern of the cell region and the peripheral circuit pattern of the peripheral circuit region.

The connection pads in adjacent rows of the secondary connection pattern are arranged in a zigzag. The connection pad is formed to contact with the upper connection line.

The plurality of rows may be two rows.

The primary connection pattern may extend to the peripheral circuit region to form part of the peripheral circuit pattern. The peripheral circuit region may further include a pattern between the pattern of the connection region and the primary connection pattern which is disconnected.

The cell pattern may be a bit line pattern, and the peripheral circuit area may be a page buffer area.

The first direction and the second direction may be perpendicular to each other.

Another aspect of the layout of the NAND flash memory for achieving the object of the present invention is a bit line pattern of the cell area; A connection pattern of a connection area connected to the cell area; And a page buffer pattern of a page buffer area connected to the connection area. The connection pattern may include a plurality of primary connection patterns traveling in a first direction and a secondary connection pattern that is self-aligned between the primary connection patterns. The secondary connection pattern includes two connection pads arranged in every other row in the second direction as two rows in a second direction. The end of the secondary connection pattern extends to the same position in the first direction.

Here, the first direction and the second direction may be perpendicular to each other.

The connection pad may have a contact to which a connection line for electrically connecting the secondary connection pattern and a portion of the page buffer pattern is connected.

The bit line pattern may include a primary bit line pattern extending into the primary connection pattern and a secondary bit line pattern self-aligned between the primary bit line pattern and extending into the secondary connection pattern.

The page buffer pattern may include a primary connection page buffer pattern extending from the primary connection pattern and a primary disconnected page buffer pattern disposed between the primary page buffer pattern and disconnected from the secondary connection pattern.

The layout of the NAND flash memory according to the present invention, in which a connection pattern of a connection region connecting a cell region and a peripheral circuit region is generated by a aligning double patterning process, is formed by arranging connection pads positioned in a secondary pattern in a zigzag form. As a result, the trimming pattern for removing unnecessary portions of the secondary pattern can be simplified, simplifying the trimming process, reducing errors in pattern formation, and increasing productivity.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

3 is a layout diagram of a connection area between a cell area and a page buffer area according to the present invention. In the layout diagram of FIG. 3, a part of the cell area is visible above the connection area, and a part of the page buffer area is visible below the connection area.

The connection patterns 40 of the connection region include a primary connection pattern 41 and a secondary connection pattern 42 formed by self-alignment based on the primary connection pattern 41. Although not shown in the layout diagram of FIG. 3 due to the fine pitch, the cell patterns 30 also include a secondary cell pattern formed by self-alignment based on the primary cell pattern and the primary cell patterns. The primary and secondary cell patterns extend to the primary connection pattern 41 and the secondary connection pattern 42 of the connection region, respectively.

In the secondary connection pattern 42 of the connection region, the connection pads 42a are formed in a zigzag form in two rows in the extending direction and the vertical direction of the connection pattern 40. That is, the connection pads 42a are formed in the first row one by one in the secondary connection pattern 42, and the connection pads 42a are alternately formed with the connection pads 42a in the first row in the second row below the first row. ) Is formed. The secondary connection patterns 42 on which the connection pads 42a are formed are all terminated at the same position and at the end of the connection area.

The primary connection pattern 41 of the connection region extends to the first page buffer pattern 51 of the page buffer region. A second page buffer pattern 52 is disposed between the first page buffer patterns 51 and the patterns of the connection area. Patterns of the cell region and the connection region having a high density of patterns are formed in a primary pattern and a secondary pattern by a self-aligned double patterning process (SADP). However, patterns of the page buffer region having a relatively low density and having various shapes are formed by a single exposure technique (SET). The secondary patterns of the cell region extend to the secondary patterns of the junction region, but the secondary patterns of the junction region terminate without extending to the page buffer region. Thus, the secondary connection patterns terminated in the connection area are connected to the patterns of the page buffer area by the upper wiring through the contact. The contact connecting to the upper wiring is formed at the connection pad 42a in the secondary connection pattern 42.

In the layout according to the present invention, since the connection pads 42a of the secondary connection pattern 42 are arranged in a row in a direction perpendicular to the traveling direction of the connection pattern 40, the secondary connection patterns 42 are all located at the same position. Can be terminated. Therefore, the layout of the trimming pattern for removing unnecessary portions of the secondary connection pattern can be simplified into a plate shape as shown in FIG. 3. The simplified trimming layout simplifies the trimming process, reduces errors in pattern formation, and increases productivity.

4A through 4J are cross-sectional views illustrating a method of forming a connection pattern by self-aligned double patterning (SADP) using a layout according to the present invention in a process order. In the cross-sectional views of FIGS. 4A to 4J, the connection area and the page buffer area are shown side by side.

First, referring to FIG. 4A, the interlayer insulating film 100, the conductive film 122, the first hard mask stacked film 125, the first polysilicon film 132, and the second hard mask stacked film 145 are in order. The photoresist pattern 152 is formed on the semiconductor substrate thus formed. The conductive film 122 may be formed of tungsten (W), for example, for bit lines. The first hard mask laminated film 125 may be formed as a laminated film of the MTO oxide film 124 and the PE oxide film 126. The first hard mask layer 125 serves as a hard mask when forming the bit line tungsten pattern. The first polysilicon film 132 constitutes a mask film for forming a primary pattern. The second hard mask layered film 145 forms a hard mask film for forming a pattern of the first polysilicon film 132. The photoresist pattern 152 is a mask pattern for forming a primary pattern.

Referring to FIG. 4B, the second hard mask layer 145 and the first polysilicon layer 132 are etched using the photoresist pattern 152 as a mask. At this time, the second hard mask layer 145 is first etched and then the first polysilicon layer 132 is etched using the pattern of the second hard mask layer 145 as a mask, or the second hard mask layer 145 is etched. ) And the first polysilicon film 132 may be etched at once.

FIG. 4C is a cross-sectional view illustrating a step in which the first polysilicon layer patterns 132a and 132b are formed by removing the second hard mask layer 145. The first polysilicon layer pattern 132a of the connection region constitutes a mask pattern (hereinafter, referred to as a primary connection mask pattern) of the primary connection pattern, and the first polysilicon layer pattern 132b of the page buffer region is a page buffer mask pattern. Configure

Referring to FIG. 4D, a thin interlayer 134 is formed on the first polysilicon layer patterns 132a and 132b. The interlayer film 134 is a film interposed between the first polysilicon film patterns 132a and 132b to form a secondary polysilicon film pattern. The interlayer film 134 may include a film having an etching selectivity with polysilicon, for example, a silicon oxide film. It can be formed by the ALD method.

Referring to FIG. 4E, the second polysilicon layer 136 is formed to fill all the spaces between the first polysilicon layer patterns 132a and 132b covered by the interlayer 134.

Referring to FIG. 4F, the second polysilicon layer 136 formed on the intermediate layer 134 is removed to leave the second polysilicon layer 136 only between the first polysilicon layer patterns 132a and 132b. CMP or etch back may be used to remove the second polysilicon layer 136, and the intermediate layer 134 may serve as a CMP stop layer or an etch stop layer.

Referring to FIG. 4G, a photoresist pattern 154 for trimming is formed in the connection region.

Referring to FIG. 4H, the second polysilicon layer 136 of the portion exposed by the photoresist pattern 154 is removed. In the page buffer region, all of the second polysilicon layers 136 exposed on the interlayer 134 are removed, leaving only the first polysilicon layer pattern 132 covered by the interlayer 134. In the connection region, as illustrated in FIG. 4H, the second polysilicon layer 136 is not removed in the portion covered by the photoresist pattern 154. A portion not shown in FIG. 4H but not covered by the photoresist pattern 154 is trimmed by removing the second polysilicon film 136.

FIG. 4I is a cross-sectional view illustrating the first hard mask stacked layer pattern 125 after the photoresist pattern 154 and the intermediate layer 134 are removed. In the connection region, a first connection mask pattern formed of the first polysilicon layer pattern 132a and a second connection mask pattern formed of the second polysilicon layer 136 are formed. A connection pad mask pattern (not shown) is formed on the secondary connection mask pattern. A page buffer mask pattern made of only the first polysilicon layer pattern 132b is formed in the page buffer area.

Referring to FIG. 4J, the tungsten layer 122 is etched using the mask patterns of FIG. 4I to form a connection pattern 122a and a page buffer pattern 122b.

Although the embodiments of the present invention have been described in detail above, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes without departing from the technical spirit of the present invention are made. It will be apparent to one of ordinary skill in the art that this is possible.

1 is a layout diagram of a connection pattern and a trimming pattern according to the related art.

2 is a planar SEM photograph of a connection pattern after a trimming process is performed by a layout of a conventional connection pattern.

3 is a layout diagram of a connection area between a cell area and a page buffer area according to the present invention.

4A through 4J are cross-sectional views sequentially illustrating a method of forming a connection pattern by self-aligned double patterning (SADP) using the layout of FIG. 3.

Claims (15)

In a self-aligned double patterning process, the NAND flash memory includes a cell region, a peripheral circuit region, and a connection region between the cell region and the peripheral circuit region. A plurality of primary connection patterns traveling in a first direction; And A second connection pattern formed by self-alignment between the first connection patterns, wherein the connection pads are arranged in a plurality of rows in a second direction, and the connection pads in the same row are disposed every other adjacent second connection pattern And a connection pattern including a second connection pattern having an end portion extending to the same position in the first direction. The NAND flash memory layout of claim 1, wherein the connection pattern electrically connects a cell pattern of the cell region and a peripheral circuit pattern of the peripheral circuit region. The layout of claim 1, wherein the connection pads in adjacent rows are arranged in a zigzag. The layout of claim 1, wherein the plurality of columns are two columns. The NAND flash memory layout of claim 1, wherein a contact pad is formed to contact the upper connection line. The NAND flash memory layout of claim 1, wherein the first connection pattern extends into the peripheral circuit region to form a part of the peripheral circuit pattern. The NAND flash memory layout of claim 6, wherein the peripheral circuit area further comprises a pattern between the pattern of the connection area and the primary connection pattern that is disconnected. The NAND flash memory layout of claim 2, wherein the cell pattern is a bit line pattern. The NAND flash memory layout of claim 2, wherein the peripheral circuit area is a page buffer area. The layout of claim 1, wherein the first direction and the second direction are perpendicular to each other. A bit line pattern of the cell region; A connection pattern of a connection area connected to the cell area; And A page buffer pattern of a page buffer area connected to the connection area; The connection pattern includes a plurality of primary connection patterns traveling in a first direction and a secondary connection pattern self-aligned between the primary connection patterns, The secondary connection pattern includes two connection pads arranged in every other row in the second direction adjacent to each other in two rows in the second direction, and ends of the second connection pattern are the same in the first direction. The NAND flash memory layout characterized by extending to. The NAND flash memory layout of claim 11, wherein the first direction and the second direction are perpendicular to each other. The NAND flash memory layout of claim 11, wherein the connection pad has a contact formed by a connection line for electrically connecting the second connection pattern and a portion of the page buffer pattern. The method of claim 11, wherein the bit line pattern comprises a secondary bit line pattern self-aligned between the primary bit line pattern extending to the primary connection pattern and the primary bit line pattern and extending to the secondary connection pattern. Layout of NAND flash memory to include. 12. The method of claim 11, wherein the page buffer pattern is disposed between the primary connection page buffer pattern extending from the primary connection pattern and the primary page buffer pattern and the primary disconnected page buffer pattern disconnected from the secondary connection pattern. Layout of NAND flash memory to include.

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