KR20090080663A - Source driver for decresing slew rate of output signal and display device comprising the source driver - Google Patents

Abstract

A source driver for decreasing the slew rate of output signal and a display device comprising a source driver are provided to reduce the slew rate deviation of data signal according to the location of an plurality of source drivers included in data driver. In a source driver for decreasing the slew rate of output signal and a display device comprising a source driver, an output buffer(143) and a power supply circuits(141, 142) are included the in the source driver. The output buffer is formed as a group composed of a plurality of output buffers outputs data signal. A power voltage supply circuit supplies a plurality of power voltages from the output buffer at the center to the output buffer at the edge.

Description

SOURCE DRIVER FOR DECRESING SLEW RATE OF OUTPUT SIGNAL AND DISPLAY DEVICE COMPRISING THE SOURCE DRIVER}

The present invention relates to a source driver and a display apparatus, and more particularly, to a source driver capable of improving the quality of a displayed image by reducing variation in the slew rate of a data signal output to a plurality of pixels of a display panel. A display device comprising a source drive.

Instead of heavy and large cathode ray tubes (CRTs), organic electroluminescent displays (OELDs) devices, plasma display panels (PDPs) devices, liquid crystal displays Research on flat panel display devices such as liquid crystal display (LCD) devices is being actively conducted.

The OELD device displays an image by using an electroluminescent effect of a specific organic material or polymer, the PDP device displays an image by using a plasma generated by gas discharge, and the LCD device is a liquid crystal layer positioned between two glass substrates. The image is displayed by controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the applied electric field.

Among them, the OELD device and the LCD device receive a gate driver for turning on / off a switching element of a plurality of pixels, a gray voltage, and output a data signal corresponding to an image signal among the gray voltages to the plurality of pixels. A data driver, and a timing controller for controlling them.

In general, the gate driver, the data driver, the timing controller, and a power supply voltage generator and a power supply voltage supply circuit for supplying a power supply voltage thereto are mounted on a printed circuit board (PCB).

Recently, the data driver including a plurality of source drivers is mounted on a glass substrate in an ACOG (Advanced Chip On Glass) method, and power wiring for supplying a driving voltage to the plurality of source drivers is also formed on the glass substrate. .

However, since the resistance of the power wiring (generally made of metal) mounted on the glass substrate is large, a difference in driving voltage supplied depending on the positions of the plurality of source drivers occurs. In addition, a difference in driving voltage may occur depending on positions of a plurality of output buffers included in one source driver.

The wiring for supplying the power supply voltages is divided into a glass wiring formed on a glass substrate and an on chip wiring inside the source driver. Glass wiring and on-chip wiring are connected to each other through the short side, not the long side of the source driver, which causes increased slew rate variation between multiple channels due to the left and right voltage difference inside the source driver. do.

In addition, as the power supply voltages pass through the source driver having a predetermined internal resistance, the voltage is dropped and supplied to the adjacent source driver, thereby increasing the slew rate deviation between the source drivers.

The driving voltage generator for generating the power supply voltages may be implemented as a regulator. The driving voltage generator may include regulator amplifiers positioned in the center of an integrated circuit and regulator drivers positioned in the center and left and right of the IC. drivers).

Because of this structure, the supply voltage is smoothly supplied to the center and left and right channels of the source driver, but the voltage drop is generated by the resistance of the power wiring to the channel of the intermediate point where the regulator drivers are arranged, so that the slew rate of these channels is increased. Slows down

FIG. 1 is a graph illustrating a change in rising time of a data signal output from a data driver according to positions of regulator drivers of a driving voltage generator of a general display apparatus. In FIG. 2, the minimum point represents a channel in which regulator drivers exist and the maximum point represents a midpoint of a channel in which the regulator driver exists.

Referring to FIG. 1, the average value of the rising time of the source driver SD2 disposed at a long distance from the power supply voltage generating circuit is the average value of the rising time of the source driver SD1 disposed at a close distance from the power supply voltage generating circuit. It can be seen that the larger, the maximum rise time is 1.6 u sec.

FIG. 2 is a graph illustrating a variation in the slew rate of the data output signal according to the position of the source driver when the source drivers SD1 and SD2 of the general display apparatus simultaneously output the data signal. Referring to FIG. 2, after the charge sharing, the rising speed of the data signal output from the source driver SD1 disposed at a close distance from the power supply voltage generator circuit is from the source driver SD2 disposed at a long distance from the power supply voltage generator circuit. Since it is faster than the rising speed of the output data signal, it can be seen that a slew rate deviation occurs between the two source drivers SD1 and SD2.

As described above, a difference in driving voltages according to positions of the plurality of output buffers and the plurality of source drivers may cause a variation in the slew rate of the data signal output to each channel. There is a problem that the characteristics of the image displayed on the basis of the deterioration.

Therefore, the technical problem to be achieved by the present invention is the location of the source driver and the source driver that can reduce the slew rate deviation of the data signal according to the position of the plurality of output buffers included in the source driver To provide a display device that can reduce the slew rate deviation of the data signal according to.

In order to achieve the above technical problem, a plurality of output buffers and a power supply voltage supply circuit may be included. The plurality of output buffers output a data signal, and the power supply voltage supply circuit supplies a plurality of power supply voltages from a centrally located output buffer toward an edged output buffer.

The plurality of power supply voltage supply circuits include a plurality of lead wires, a plurality of power distribution wires, and a plurality of driving voltage generators. The plurality of incoming wires each receive a corresponding power supply voltage among the plurality of power supply voltages. Each of the plurality of power distribution wires is connected to a corresponding lead wire among the lead wires, and has a left-right symmetry structure around the corresponding lead wire.

Each of the plurality of driving voltage generators receives the corresponding power supply voltage and supplies a driving voltage of a constant voltage level to the plurality of output buffers based on the corresponding power supply voltage. Each of the plurality of lead wires may be connected to a power wire formed on a glass substrate to supply a corresponding power voltage among the plurality of power voltages.

Each of the plurality of driving voltage generators includes a control unit and a plurality of regulator drivers. The at least one control unit generates a control signal for generating the drive voltage. The plurality of regulator drivers each generate the drive voltage in response to the corresponding power supply voltage and the control signal, and have different current drive capabilities depending on the position of the output buffer to which it is coupled.

The plurality of regulator drivers may have greater current driving capability as the connected output buffer is disposed farther from the corresponding incoming wiring.

The source driver further includes a plurality of switching elements connected between output terminals of the plurality of output buffers and corresponding pixels among the plurality of pixels, and outputting data signals at different points of time according to positions of the output buffers. can do.

The data signal output time point of the plurality of switching elements may be faster as the output buffer is disposed farther from the corresponding incoming wiring.

A display device for solving the above technical problem includes a plurality of pixels, a power supply voltage generation circuit, and a data driver. The plurality of pixels are arranged in a matrix form, and the power supply voltage generation circuit generates a plurality of power supply voltages.

The data driver includes a plurality of source drivers each of which outputs a data signal to a corresponding plurality of pixels among the plurality of pixels in response to a first control signal output from a timing controller. The output time point of the data signal of the plurality of source drivers may be faster as it is disposed farther from the power supply voltage generation circuit, and may be determined based on a charge sharing code for each source driver.

Each of the plurality of source drivers receives a plurality of output buffers for outputting the data signal and the plurality of power supply voltages, and the received plurality of power supply voltages are located at an edge from an output buffer located at the center of the source driver. A power supply voltage supply circuit for supplying the output buffer direction.

The power supply voltage supply circuit includes a plurality of incoming wirings, a plurality of power distribution wirings, and a driving voltage generating unit. Each of the plurality of lead wires receives a corresponding power voltage among a plurality of power voltages. Each of the plurality of power distribution wires is connected to a corresponding lead wire among the lead wires, and has a left-right symmetry structure around the corresponding lead wire.

Each of the plurality of driving voltage generation units receives the corresponding power supply voltage and supplies a driving voltage of a constant voltage level to the plurality of output buffers based on the corresponding power supply voltage.

Each of the plurality of lead wires may be connected to a power wire formed on a glass substrate to supply a corresponding power voltage among the plurality of power voltages. Each of the plurality of driving voltage generators generates the driving voltage in response to the at least one control unit generating the control signal for generating the driving voltage and the corresponding power supply voltage and the control signal, and connected to the output buffer. Depending on the location, it can include multiple regulator drivers with different current driving capabilities.

The plurality of regulator drivers may have greater current driving capability as the connected output buffer is disposed farther from the corresponding incoming wiring.

The source driver further includes a plurality of switching elements connected between output terminals of the plurality of output buffers and corresponding pixels among the plurality of pixels, and outputting data signals at different points of time according to positions of the output buffers. can do. The data signal output time point of the plurality of switching elements may be faster as the output buffer is disposed farther from the corresponding incoming wiring.

As described above, the source driver and the display apparatus according to the present invention reduce the slew rate deviation of the data signal according to the position of the plurality of output buffers included in the source driver, and according to the position of the plurality of source drivers included in the data driver. By reducing the slew rate variation of the data signal, there is an effect that can prevent deterioration of the characteristics of the displayed image.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

In the present specification, when one component 'transmits' data or a signal to another component, the component may directly transmit the data or signal to the other component, and at least one other component. Through this means that the data or signal can be transmitted to the other component.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a display apparatus 100 according to an exemplary embodiment of the present invention. Referring to FIG. 3, the display apparatus 100 includes a panel 110 including a plurality of pixels (not shown) arranged in a matrix form, a timing controller 120, a gate driver 130, and a data driver ( 140). The display apparatus 100 may further include a power supply voltage generation circuit for generating a plurality of power supply voltages, and may be disposed on the PCB together with the timing controller 120 and the gate driver 130.

The timing controller 120 generates a plurality of control signals CS1 and CS2 for controlling the gate driver 130 and the data driver 140, and transmits the digital data signal DATA to the data driver 140. ) The gate driver 130 outputs signals G1, G2,..., Gm for turning on / off the switching elements of the plurality of pixels in response to a first control signal CS1. .

The data driver 140 may include a plurality of source drivers. The plurality of source drivers are driven based on the plurality of power supply voltages, and the plurality of pixels in response to the second control signal CS2 and the digital data signal DATA output from the timing controller 120. The data signals D1, D2,..., Dn are output to the corresponding plurality of pixels.

The faster the output time point of the data signals of the plurality of source drivers than the source voltage generation circuit, the shorter the slew rate deviation between the source drivers. The details of this are deferred later.

4 is a block diagram illustrating an example embodiment of a data driver 140 of the display apparatus of FIG. 3. Referring to FIG. 4, the data driver 140 includes a glass wiring formed on a glass substrate and a plurality of source drivers SD1 and SD2. In FIG. 4, only two source drivers are shown for convenience of description.

Each of the plurality of source drivers SD1 and SD2 includes power supply voltage supply circuits 141 and 142, and a plurality of output buffers 143. The plurality of output buffers 143 output data signals.

The power supply voltage supply circuits 141 and 142 receive the plurality of power supply voltages VDD2 and VSS2, and transmit the received plurality of power supply voltages VDD2 and VSS2 to source drivers SD1 and SD2, respectively. Feeds from the centrally located output buffer toward the output buffer located at the edge.

In FIG. 4, the power supply voltages VDD2 and VSS2 may be recognized as being supplied from the timing controller 120, but a power supply voltage generation circuit (not shown) disposed on the same PCB as the timing controller 120 may be substantially provided. It is supplied from.

The power supply voltage supply circuits 141 and 142 include a plurality of lead wires 141, a plurality of power distribution wires 142, and driving voltage generation units (not shown). Each of the plurality of lead wires 141 receives a corresponding power voltage among the plurality of power voltages VDD2 and VSS2 through a glass wire.

Each of the plurality of power distribution wires is connected to a corresponding lead wire among the lead wires, and has a left-right symmetry structure around the corresponding lead wire. That is, the plurality of power supply voltages VDD2 and VSS2 are supplied to output buffers symmetrically about the lead wire. Therefore, the left and right slew rate deviations between the output signals of the respective output buffers in the source driver SD1 or SD2 can be reduced.

However, the slew rate deviation between the source drivers SD1 and SD2 may occur due to the plurality of power supply voltages VDD2 and VSS2 supplied to the other source driver SD2 through the source driver SD1.

Each of the plurality of driving voltage generation units receives the corresponding power supply voltage VDD2 or VSS2 and is constant at the voltage level into the plurality of output buffers 143 based on the corresponding power supply voltage VDD2 or VSS2. Supply the driving voltage.

5 is a block diagram conceptually illustrating a data driver 140a according to another exemplary embodiment of the present invention. Since the difference between the data driver 140 of FIG. 4 and the data driver 140a of FIG. 5 is only in the structure of the lead-in wiring 141, only this will be described.

The lead wire 141 of the data driver 140a of FIG. 5 directly connects the glass wire and the power distribution wire 142, and the plurality of power supply voltages VDD2 and VSS2 are not connected to the lead wire 141. It is not supplied to other source drivers. Therefore, the slew rate deviation between the source drivers of the data driver 140a of FIG. 5 is less than the slew rate deviation between the source drivers of the data driver 140 of FIG. 4.

FIG. 6 illustrates a positional arrangement of power wires and pads of the data driver 140a of FIG. 5. Referring to FIG. 6, it can be seen that the data driver 140a of FIG. 6 has a difference in the arrangement of the glass wiring and the arrangement of the lead wiring 141 compared to the data driver 140a of FIG. 5.

In an enlarged dotted line of FIG. 6, the glass wires supplying the supply voltages VDD2 and VSS2 include the lead wires 141 and the pad PAD positioned at one long side of the source driver SD1 and SD2. It can be seen that they are connected to each other by). The lead wires 141 corresponding to the power supply voltages VDD2 and VSS2 may be metal wires M1 and M2, respectively.

FIG. 7 is a diagram illustrating a driving voltage generator 144 of the source driver SD1 or SD2 of FIG. 6. FIG. 8 is a circuit diagram illustrating the driving voltage generator 144 of FIG. 7. The driving voltage generator 144 receives the power supply voltages VDD2 and VSS2 and generates driving voltages VDDR and VSSR. The driving voltage generator 144 may be implemented as a regulator.

Referring to FIG. 7, the driving voltage generator 144 includes at least one regulator amp and a plurality of regulator drivers. The control unit generates a control signal for generating the drive voltage VDDR or VSSR. The regulator drivers generate the driving voltage VDDR or VSSR in response to the power supply voltage VDD2 or VSS2 and the control signal.

Compared with a general driving voltage generator, the driving voltage generator 144 not only includes regulator drivers at the center and the edge of the source driver but also includes a plurality of regulator drivers (in a dotted circle). Regulator drivers). This reduces the slew rate variation with the position of the output buffer.

The regulator drivers may have different current driving capabilities (drive size) depending on the position of the output buffer to be connected. In FIG. 7, it can be seen that the size of the regulator driver gradually increases from 2x (x2), 3x (x3), and 4x (x4) from the center to the edge of the source driver. This is because the voltage drop of the power supply voltage VDD2 or VSS2 increases as the edge is positioned, so that the slew rate deviation of the data signal according to the position of the output buffer of the source driver is reduced.

Referring to FIG. 8, the driving voltage generator 144 includes a first regulator 144a and a second regulator 144b. Each of the first regulator 144a and the second regulator 144b is driven in response to an output signal of one regulator amplifier and the regulator amplifier, and is driven based on the power supply voltage VDD2 or VSS2. Or a plurality of regulator drivers generating a VSSR.

Regulator drivers that generate the driving voltage (VDDR or VSSR) are larger in size (ie, current driving capability) at the edge of the source driver. Each of the output buffers 143 outputs a data signal in response to the driving voltages VDDR and VSSR. The slew rate variation of the data signal according to the position of the output buffer may be reduced by adjusting the size of the regulator drivers. .

FIG. 9 is a graph illustrating a rising time of a data signal according to positions of output buffers when the sizes of the regulator drivers of FIG. 8 are changed. Referring to FIG. 9, when the size of the regulator drivers is constant, the rising maximum random deviation of the data signal is 400 n sec, while the maximum deviation of the rising time of the data signal when the size of the regulator drivers is adjusted is 200 n. It can be seen that it is reduced to sec.

10 is a graph illustrating a rising time of a data signal output from a general data driver and a data signal output from the data driver 140 according to an exemplary embodiment of the present invention.

Referring to FIG. 10, the rising time of the data signal output from the data driver 140 according to the exemplary embodiment of the present invention is reduced overall, and the variation of the rising time of the data signal according to the source driver and the position of the output driver in the source driver. It can be seen that the variation of the rising time of the data signal according to the present invention is greatly reduced.

FIG. 11 is a graph illustrating a deviation of a slew rate of a data output signal according to a position of the source driver when source drivers included in the data driver of FIG. 3 control an output time point of a data signal.

Controlling the output timing of the data signals of the source drivers refers to outputting a data signal from the source driver SD2 disposed at a position far from the power supply voltage generating circuit in order to compensate for the drop caused by the power supply wiring of the power supply voltage.

The source driver SD2 disposed at a position far from the power supply voltage generator circuit outputs the data signal first, and then the source driver SD1 disposed at a position close to the power supply voltage generator circuit outputs the data signal. This is because the higher the data signal is located, the slower the data signal is due to the drop in the power supply voltage depending on the position of the source driver.

2 and 11, it can be seen that the slew rate deviation of the data signal output from the source drivers SD1 and SD2 of the data driver 140 according to the present invention is reduced.

Although the invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a graph illustrating a change in a rising time of a data signal output from a data driver according to positions of drivers of a driving voltage generator of a general display apparatus.

2 is a graph illustrating a deviation of a slew rate of a data output signal according to a position of a source driver of a general display device.

3 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating an example embodiment of a data driver of the display apparatus of FIG. 3.

5 is a block diagram conceptually illustrating another embodiment of a data driver of the display apparatus of FIG. 3.

FIG. 6 illustrates actual positions of power wires and pads of the data driver of FIG. 5.

FIG. 7 is a configuration diagram illustrating a driving voltage generator of the source driver of FIG. 6.

8 is a circuit diagram illustrating the driving voltage generator of FIG. 7.

FIG. 9 is a graph illustrating a rising time of a data signal according to positions of output buffers when the sizes of the regulator drivers of FIG. 8 are changed.

10 is a graph illustrating a rising time of a data signal output from a general data driver and a data signal output from a data driver according to an exemplary embodiment of the present invention.

FIG. 11 is a graph illustrating a deviation of a slew rate of a data output signal according to a position of the source driver when source drivers included in the data driver of FIG. 3 control an output time point of a data signal.

Claims (14)

A plurality of output buffers for outputting a data signal; And And a power supply voltage supply circuit for supplying a plurality of power supply voltages from an output buffer located at a center to an output buffer located at an edge of the plurality of output buffers. The method of claim 1, wherein the power supply voltage supply circuit, A plurality of incoming wires, each receiving a corresponding power supply voltage among the plurality of power supply voltages; A plurality of power distribution wires each connected to a corresponding lead wire among the lead wires and having a left-right symmetrical structure with respect to the corresponding lead wire; And A plurality of driving voltage generators each receiving the corresponding power supply voltage and supplying a driving voltage of a constant voltage level to the plurality of output buffers based on the corresponding power supply voltage, Each of the plurality of incoming wires, And a source driver connected to a power line formed on a glass substrate to supply a corresponding power voltage among the plurality of power voltages. The method of claim 1, wherein each of the plurality of driving voltage generators, At least one control unit for generating a control signal for generating the drive voltage; And And a plurality of regulator drivers each of which generates the driving voltage in response to the corresponding power supply voltage and the control signal, the regulator drivers having different current driving capabilities depending on the position of the output buffer to be connected. The method of claim 3, wherein the plurality of regulator drivers, Source driver having a greater current driving capability as the connected output buffer is disposed farther from the corresponding incoming wiring. The method of claim 1, wherein the source driver, And a plurality of switching elements connected between output terminals of the plurality of output buffers and corresponding pixels among the plurality of pixels, and outputting data signals at different points of time according to positions of the output buffers. The method of claim 5, wherein the data signal output time of the plurality of switching elements, The faster the output buffer is located away from the corresponding incoming wiring. A plurality of pixels arranged in a matrix form; A power supply voltage generation circuit for generating a plurality of power supply voltages; A data driver including a plurality of source drivers each of which receives the plurality of power voltages and outputs a data signal to a corresponding plurality of pixels among the plurality of pixels in response to a first control signal output from a timing controller Include, An output time point of the data signal of the plurality of source drivers is The faster the display device is disposed away from the power supply voltage generation circuit. The method of claim 7, wherein the output time of the data signal of the plurality of source drivers, Display device determined based on charge sharing code for each source driver. The method of claim 7, wherein each of the plurality of source drivers, A plurality of output buffers for outputting the data signal; A power supply voltage supply circuit for receiving the plurality of supply voltages and supplying the received plurality of supply voltages from an output buffer located at the center of the source driver to the output buffer located at an edge of the plurality of output buffers; , The power supply voltage supply circuit, A plurality of incoming wires, each receiving a corresponding power supply voltage among the plurality of power supply voltages; A plurality of power distribution wires each connected to a corresponding lead wire among the lead wires and having a left-right symmetrical structure with respect to the corresponding lead wire; And And a plurality of driving voltage generating units each receiving the corresponding power supply voltage and supplying a driving voltage of a constant voltage level to the plurality of output buffers based on the corresponding power supply voltage. The method of claim 9, wherein each of the plurality of incoming wires, And a power line formed on a glass substrate to supply a corresponding power voltage among the plurality of power voltages. The method of claim 9, wherein each of the plurality of driving voltage generators, At least one control unit for generating a control signal for generating the drive voltage; And And a plurality of regulator drivers generating the driving voltage in response to the corresponding power supply voltage and the control signal and having different current driving capabilities depending on the position of the output buffer to be connected. The method of claim 11, wherein the plurality of regulator drivers, Display device having a greater current driving capability as the connected output buffer is disposed farther from the corresponding incoming wiring. The method of claim 9, wherein the source driver, And a plurality of switching elements connected between output terminals of the plurality of output buffers and corresponding pixels among the plurality of pixels, and outputting data signals at different points of time according to positions of the output buffers. The data signal output time point of the plurality of switching elements is: And the faster the output buffer is disposed away from the corresponding incoming wiring.

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