KR20090077198A - Method for manufacturing of isolation layer of semiconductor device - Google Patents
Method for manufacturing of isolation layer of semiconductor device Download PDFInfo
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- KR20090077198A KR20090077198A KR1020080003012A KR20080003012A KR20090077198A KR 20090077198 A KR20090077198 A KR 20090077198A KR 1020080003012 A KR1020080003012 A KR 1020080003012A KR 20080003012 A KR20080003012 A KR 20080003012A KR 20090077198 A KR20090077198 A KR 20090077198A
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- insulating film
- insulating material
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 title description 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000007789 gas Substances 0.000 claims abstract description 25
- 229920001709 polysilazane Polymers 0.000 claims abstract description 20
- 239000011810 insulating material Substances 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000004528 spin coating Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 9
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 2
- 230000008602 contraction Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 54
- 238000001723 curing Methods 0.000 description 21
- 238000007254 oxidation reaction Methods 0.000 description 9
- 239000010409 thin film Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/0231—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to electromagnetic radiation, e.g. UV light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 반도체 소자의 절연막 형성 방법에 관한 것으로서, 보다 상세하게는, 스핀 코팅 공정으로 형성되는 갭필용 절연막의 밀도를 향상시킬 수 있는 반도체 소자의 절연막 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating film of a semiconductor device, and more particularly, to a method for forming an insulating film for a semiconductor device capable of improving the density of the gap fill insulating film formed by a spin coating process.
모든 반도체 소자에는 금속 배선이 다층으로 형성되고 상기 다층의 금속 배선을 전기적으로 절연시키기 위하여 상기 금속 배선 사이에는 층간절연막이 형성된다. 그리고, 상기 층간절연막 이외에 반도체 기판에 형성되는 소자들을 전기적으로 격리시키기 위하여 소자분리막용으로 절연막이 형성된다.In all semiconductor devices, metal wirings are formed in multiple layers, and an interlayer insulating film is formed between the metal wirings to electrically insulate the multilayer metal wirings. An insulating film is formed for the device isolation film to electrically isolate the devices formed on the semiconductor substrate in addition to the interlayer insulating film.
일반적으로, 반도체 소자의 소자분리막을 포함하여 각종 층간절연막은 SOD(Spin on dielectric)막, HDP(High density plasma)막, BPSG(Boro phospo silicate glass)막, TEOS(Tetraethylorthosilicate)막, SiO2막 및 저유전막 등과 같이 다양한 산화막 및 화합물막으로 형성된다.In general, various interlayer insulating films, including device isolation layers of semiconductor devices, include spin on dielectric (SOD) films, high density plasma (HDP) films, boro phospo silicate glass (BPSG) films, tetraethylorthosilicate (TEOS) films, SiO 2 films, and the like. It is formed of various oxide films and compound films, such as a low dielectric film.
한편, 최근에는 반도체 기술의 진보와 더불어 디자인 룰이 점점 작아짐에 따 라 반도체 소자의 고집적화가 급속하게 진행되고 있다. 이에 수반하여, 종래 CVD(Chemical vapor deposition) 방법으로 형성되는 TEOS막 또는 HDP막과 같은 절연막은 400℃ 이상의 높은 온도에서 공정이 수행되기 때문에 갭―필(Gap fill) 측면에서 한계가 있다.On the other hand, in recent years, with the progress of semiconductor technology and the design rules are getting smaller, high integration of semiconductor devices is rapidly progressing. In connection with this, an insulating film such as a TEOS film or an HDP film formed by a conventional chemical vapor deposition (CVD) method is limited in terms of gap fill because the process is performed at a high temperature of 400 ° C. or higher.
따라서, 최근에는 상기 절연막의 형성시 발생하는 갭―필 문제를 극복하기 위하여, 액체와 같은 유동성을 가진 물질을 이용한 스핀―코팅(Spin―coating) 방법으로 각종 절연막을 형성하는 방법이 이용되고 있다. Therefore, recently, in order to overcome the gap-fill problem generated during the formation of the insulating film, a method of forming various insulating films by a spin-coating method using a material having fluidity such as liquid has been used.
그러나, 상기 스핀―코팅 방식으로 형성된 절연막은 종래의 CVD 방식으로 형성된 산화막과 같은 절연막에 비하여 매립 특성이 우수한 반면, 절연막의 밀도가 매우 낮고 패턴상에서 박막의 밀도가 균일하지 못하다. However, the insulating film formed by the spin-coating method is superior to the insulating film such as the oxide film formed by the conventional CVD method, while the density of the insulating film is very low and the density of the thin film is not uniform on the pattern.
또한, 탄성계수, 크랙 저항성 등과 같은 기계적 강도가 약하여 크랙과 같은 공정 이슈가 발생하고 있다. In addition, the mechanical strength such as elastic modulus, crack resistance, etc. is weak, causing process issues such as cracks.
따라서, 우수한 갭―필 능력을 가지면서 박막 밀도가 우수한 절연막을 형성하기 위한 새로운 공정이 필요하게 되었다.Thus, there is a need for a new process for forming an insulating film having excellent gap-fill capability and excellent thin film density.
본 발명은 스핀 코팅 공정으로 형성되는 갭필용 절연막의 밀도를 향상시킬 수 있는 반도체 소자의 절연막 형성 방법을 제공한다.The present invention provides a method for forming an insulating film of a semiconductor device capable of improving the density of the gap fill insulating film formed by a spin coating process.
본 발명에 따른 반도체 소자의 절연막 형성 방법은, 반도체 기판에 패턴들을 형성하는 단계; 상기 각 패턴들 사이 영역이 매립되도록 상기 반도체 기판 상에 절연물질을 도포하는 단계; 및 상기 절연물질을 산소분위기에서 자외선을 조사하여 경화시키는 단계를 포함한다. An insulating film forming method of a semiconductor device according to the present invention comprises the steps of forming patterns on a semiconductor substrate; Applying an insulating material on the semiconductor substrate to fill the region between the patterns; And curing the insulating material by irradiating ultraviolet rays in an oxygen atmosphere.
상기 경화시키는 단계는 오존(O3) 가스와 산소(O2) 가스를 주입하여 수행한다.The curing step is performed by injecting ozone (O 3 ) gas and oxygen (O 2 ) gas.
상기 오존(O3) 가스와 산소(O2) 가스는 1 : 10 ∼ 5 : 5의 비율로 주입한다.The ozone (O 3 ) gas and the oxygen (O 2 ) gas are injected at a ratio of 1:10 to 5: 5.
상기 경화시키는 단계는 200 ∼ 400℃의 온도에서 수행한다.The curing step is carried out at a temperature of 200 ~ 400 ℃.
상기 경화시키는 단계는 180 ∼ 280nm 영역의 파장을 갖는 자외선을 이용하여 수행한다.The curing step is performed using ultraviolet light having a wavelength in the region of 180 to 280 nm.
상기 경화시키는 단계는 단일 파장 또는 멀티 파장의 자외선을 이용하여 수행한다.The curing step is performed using a single wavelength or multi wavelength ultraviolet light.
상기 절연물질은 스핀―코팅 방법으로 도포한다.The insulating material is applied by a spin-coating method.
상기 절연물질은 폴리실라잔(Polysilazane)이다.The insulating material is polysilazane.
상기 패턴은 게이트, 비트라인, 트랜치 및 금속배선을 포함한다.The pattern includes gates, bit lines, trenches and metallizations.
상기 절연물질을 도포하는 단계 후, 그리고, 상기 절연물질을 경화시키는 단계 전, 상기 절연물질을 베이킹하는 단계를 더 포함한다.Baking the insulating material after applying the insulating material and before curing the insulating material.
본 발명은 오존 가스와 산소 가스가 주입되고 저온 상태에서 자외선을 이용하여 반도체 기판 상에 스핀―코팅된 절연막 형성 물질을 경화시킴으로서 수축 및 스트레스의 발생을 방지하고 고밀도화되어 기계적 강도가 향상된 절연막을 형성할 수 있다. The present invention is to prevent the occurrence of shrinkage and stress by curing the spin-coated insulating film forming material on the semiconductor substrate using an ultraviolet light in the ozone gas and oxygen gas is injected at a low temperature state to form an insulating film with improved mechanical strength Can be.
본 발명은 오존(O3) 가스와 산소(O2)를 함께 주입하고 저온 상태에서 절연막 형성 물질을 자외선으로 경화시켜 수축률이 낮고, 저온에서도 고밀도화되어 기계적 물성이 우수한 절연막을 형성한다. In the present invention, ozone (O 3 ) gas and oxygen (O 2 ) are injected together and the insulating film forming material is cured by ultraviolet rays at a low temperature to form an insulating film having a low shrinkage rate and a high density at low temperatures, thereby providing excellent mechanical properties.
자세하게, 종래 반도체 소자의 절연막은 폴리실라잔(Polysilazane)과 같은 절연막 형성 물질을 스핀―코팅 방법을 이용하여 반도체 기판 상에 도포한 후, 건식 또는 습식 분위기에서 열에너지를 이용한 경화공정을 수행하여 상기 폴리실라잔을 실리콘산화막으로 변형하는 방법으로 형성하였다.In detail, an insulating film of a conventional semiconductor device is applied to an insulating film forming material such as polysilazane (Polysilazane) on a semiconductor substrate using a spin-coating method, and then performing a curing process using thermal energy in a dry or wet atmosphere to perform the poly Silazane was formed by transforming the silicon oxide film.
상기 열에너지를 이용한 경화 공정은 건식 또는 습식 분위기에서의 경화 공정은 700℃ 이상의 고온에서 수행하거나 또는 400℃ 이하의 저온에서 수행하였으며, 일반적으로 건식 분위기 보다는 산화과정에서 수분이 촉매로 작용하기 때문에 절연막의 고밀도화 측면에서 더 유리한 습식 분위기에서 수행하였다. The curing process using the thermal energy was performed in a dry or wet atmosphere at a high temperature of 700 ° C. or higher or at a low temperature of 400 ° C. or lower. Generally, moisture acts as a catalyst in the oxidation process rather than in a dry atmosphere. It was performed in a wet atmosphere, which is more advantageous in terms of densification.
그러나, 상기 건식 또는 습식 분위기에서의 경화 공정 중 700℃ 이상의 고온에서 수행하는 경화 공정은 형성되는 절연막의 기계적 강도를 증가시키는 반면 기공 발생, 절연막의 수축 및 스트레스를 야기시키는 문제가 있다. However, the curing process performed at a high temperature of 700 ° C. or higher during the curing process in a dry or wet atmosphere increases the mechanical strength of the insulating film to be formed, while causing porosity, shrinkage and stress of the insulating film.
또한, 상기 건식 또는 습식 분위기에서의 경화 공정 중 400℃ 이하의 저온에서 수행하는 경화 공정은 절연막의 수축 및 스트레스 문제는 방지할 수 있으나, 형 성되는 절연막의 기계적 강도가 매우 취약해져 경화 온도를 낮추는데 한계가 있다.In addition, the curing process performed at a low temperature of less than 400 ℃ of the curing process in the dry or wet atmosphere can prevent the shrinkage and stress problems of the insulating film, but the mechanical strength of the insulating film to be formed is very fragile to lower the curing temperature There is a limit.
따라서, 본 발명은 종래 열에너지만을 이용하는 경화방법을 대신하여 저온의 열과 자외선을 동시에 이용하고, 상기 절연막을 형성하기 위한 폴리실라잔의 산화반응을 최적화시키기 위하여 오존(O3) 가스와 산소(O2)가스를 함께 주입하여 절연막을 형성함으로써 수축 및 스트레스의 발생을 방지하고 밀도가 증가되어 기계적 강도가 향상된 절연막을 형성할 수 있다. Accordingly, the present invention uses ozone (O 3 ) gas and oxygen (O 2 ) in order to optimize the oxidation reaction of polysilazane to form the insulating film at the same time using a low temperature heat and ultraviolet light instead of the curing method using only conventional thermal energy. By injecting the gas together to form an insulating film, it is possible to prevent the occurrence of shrinkage and stress and to increase the density to form an insulating film having improved mechanical strength.
이하에서는, 본 발명의 실시예에 따른 반도체 소자의 절연막 형성 방법을 상세히 설명하도록 한다. Hereinafter, a method of forming an insulating film of a semiconductor device according to an embodiment of the present invention will be described in detail.
도 1은 본 발명의 실시예에 따른 절연막 형성 물질로 사용되는 폴리실라잔의 구조를 도시한 도면이며, 도 2a 내지 도 2b는 본 발명의 실시예에 따른 반도체 소자의 절연막 형성 방법을 도시한 도면이다.1 is a view showing a structure of a polysilazane used as an insulating film forming material according to an embodiment of the present invention, Figures 2a to 2b is a view showing a method of forming an insulating film of a semiconductor device according to an embodiment of the present invention to be.
도 2a을 참조하면, 다수의 패턴(110)이 형성된 반도체 기판(100) 상에 절연막 형성 물질(120), 바람직하게, 도 1에 도시된 바와 같은 구조를 갖는 폴리실라잔을 스핀―코팅 방법으로 도포한다. 상기 패턴(110)은 게이트, 비트라인, 트랜치 및 금속배선을 포함한다.Referring to FIG. 2A, an insulating
그런 다음, 상기 폴리실라잔(120)이 도포된 상기 반도체 기판(100)에 베이킹(Baking) 공정을 수행하여 상기 폴리실리잔(120)으로 이루어진 박막을 형성한다.Then, a baking process is performed on the
도 2b를 참조하면, 상기 폴리실라잔(120) 박막이 형성된 반도체 기판(100)에 산소분위기 하에서 자외선을 조사하는 경화 공정을 수행하여 상기 패턴(110)들을 감싸는 실리콘산화막(130)을 형성하여 반도체 소자의 절연막 형성을 완료한다. Referring to FIG. 2B, a
상기 자외선을 이용한 경화 공정은 오존(O3) 가스와 산소(O2) 가스가 1 : 10 ∼ 5 : 5의 비율로 혼합된 상태로 함께 주입된 상태에서 200 ∼ 400℃의 온도에서 수행한다. The curing process using the ultraviolet rays is carried out at a temperature of 200 ~ 400 ℃ in a state in which the ozone (O 3 ) gas and oxygen (O 2 ) gas is injected together in a mixed state at a ratio of 1:10 to 5: 5.
상기 경화 공정은 180 ∼ 280nm 범위의 파장을 갖는 자외선을 이용하며, 단일 파장 (Single frequency) 또는 멀티(Multi) 파장의 형태로 조사된다. The curing process uses ultraviolet rays having a wavelength in the range of 180 to 280 nm, and is irradiated in the form of a single frequency or a multi wavelength.
상기 자외선을 이용한 경화 공정시, 상기 산소(O2) 가스와 오존(O3) 가스의 양을 조절하는 이유는 상기 폴리실라잔을 산화시키기 위한 산화 방식 측면에 기인한 것이다. In the curing process using the ultraviolet rays, the reason for controlling the amount of the oxygen (O 2 ) gas and the ozone (O 3 ) gas is due to the aspect of the oxidation method for oxidizing the polysilazane.
즉, 상기 산소(O2) 가스는 상기 자외선 경화 공정에서 자외선에 의해 상기 폴리실라잔을 산화시키도록 상기 폴리실라잔의 산화 반응에 적극 참여하는 산소 라디칼(Radical)을 형성한다. That is, the oxygen (O 2 ) gas forms oxygen radicals actively participating in the oxidation reaction of the polysilazane to oxidize the polysilazane by ultraviolet rays in the ultraviolet curing process.
그리고, 상기 오존(O3)는 상기 자외선에 의해 오존 라디칼 및 산소 라디칼을 형성하며, 상기 오존 라디칼은 상기 폴리실라잔의 산화 반응에서 촉매의 역할을 수행하기 때문에 산화 방식의 측면에서 상기 오존(O3) 가스로부터 생성된 오존 라디칼의 양이 많을수록 상기 폴리실라잔의 산화 반응은 용이해진다. The ozone (O 3 ) forms ozone radicals and oxygen radicals by the ultraviolet rays, and since the ozone radicals play a role of a catalyst in the oxidation reaction of the polysilazane, the ozone (O 3 ) is used in terms of oxidation. 3 ) The greater the amount of ozone radicals generated from the gas, the easier the oxidation reaction of the polysilazane.
따라서, 상기 폴리실라잔의 산화 반응을 최적화시키기 위해서는 일정 부분의 오존 라디칼이 필요하며, 상기 폴리실라잔의 산화 반응을 최적화시키기 위해서는 주입되는 산소(O2) 가스 및 오존(O3) 가스로부터 생성되는 산소 라디칼 및 오존 라디칼 양의 조절이 필요하기 때문에 상기 주입되는 산소(O2) 가스와 오존(O3) 가스의 양은 조절되어야 한다. Therefore, a portion of ozone radicals are required to optimize the oxidation reaction of the polysilazane, and generated from oxygen (O 2 ) gas and ozone (O 3 ) gas injected to optimize the oxidation reaction of the polysilazane. The amount of oxygen (O 2 ) gas and ozone (O 3 ) gas to be injected must be controlled because the amount of oxygen radicals and ozone radicals to be adjusted is necessary.
이상에서와 같이, 본 발명은 오존(O3) 가스와 산소(O2) 가스가 주입되고 저온 상태에서 자외선을 이용하여 반도체 기판 상에 스핀―코팅된 절연막 형성 물질을 경화시킴으로서 종래 절연막에 비하여 수축률이 낮고, 저온에서도 고밀도화되어 기계적 물성이 우수한 절연막을 형성할 수 있다.As described above, the present invention shrinks compared to the conventional insulating film by injecting ozone (O 3 ) gas and oxygen (O 2 ) gas and curing the spin-coated insulating film forming material on the semiconductor substrate using ultraviolet light in a low temperature state. It is possible to form an insulating film having low density and excellent mechanical properties even at low temperatures.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
도 1은 본 발명의 실시예에 따른 절연막 형성 물질로 사용되는 폴리실라잔의 구조를 도시한 도면.1 is a view showing the structure of polysilazane used as an insulating film forming material according to an embodiment of the present invention.
도 2a 내지 도 2b는 본 발명의 실시예에 따른 반도체 소자의 절연막 형성 방법을 도시한 도면.2A to 2B illustrate a method of forming an insulating film of a semiconductor device in accordance with an embodiment of the present invention.
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