KR20090075335A - The technology and method to improve on encoding rates for high complexity coding algorithm which based on hardware acceleration - Google Patents

Abstract

An H.264 codec coding rate advanced technology through a hardware acceleration base high complexity coding algorithm and a method for implementing the high quality/high efficiency H.264 encoding is provided to implement H264 encoding solution by processing H264 encoding solution. A bit rate is reduced by being searched through a common part. An SAD computational complexity is reduced and ESA(Exhaustive Search Algorithm) has accuracy by using SEA(Successive Elimination Algorithm). The quality s sacrificed but parallelism is enhanced and the encoding rate is improved through the trade-off strategy. A best speed strategy is a mode which a bit sacrifices the quality and takes precedence speed. The best speed strategy applies the fast search algorithm which is suitable.

Description

H.264 Codec Encoding Rates for High Complexity Coding Algorithm which based on Hardware Acceleration}

The present invention relates to a technique and method for improving H.264 Codec coding rate through High Complexity Coding Algorithm based on Hardware Acceleration, and more particularly, to analyze the time share of each encoding submodule through profiling analysis of H.264 encoder. Simple, high-computation H.264 encoding using a board or co-processor that provides a high degree of parallel processing independent of CPU resources, using a strategy to speed up the GPU from the most critical of time. To efficiently process H.264 encoding solutions.

Video compression technology has achieved performance improvement from MPEG-1, MPEG2, H.263, MPEG4, and H.264 based on basic technologies such as Motion Estimation, Transform, Quantization, and Entropy Coding established from H.261. Interoperability with stream processing has been ensured.

However, H.264, which is the best video compression technology in the world, has a slow encoding speed. Therefore, there is a limitation in using it for a real time broadcasting system or a server-based transcoding system that is very sensitive to the encoding speed. Therefore, the existing H.264 encoder tried to improve the speed by improving algorithms for complex calculations, but there are some limitations to improve the actual operability by using the method of improving the speed by slightly damaging the image quality. In addition, a wireless video service provided by a mobile communication company provides a video service having a small screen size of QCIF (176x144) or QVGA (320x240) due to the size limitation of the mobile phone screen. In such a small screen, image quality is more and more required, and the existing H.264 encoders are limited in improving the quality of service because the encoding speed is improved through the loss of image quality.

The present invention utilizes a board or a co-processor that provides a high degree of parallel processing separately from CPU resources to efficiently process a simple but computational H.264 encoding portion to provide a high quality and high efficiency H, 264 encoding solution. The goal is to make it.

As a co-processor that will help the CPU to execute high speed parallel processing, we chose a GPU (Graphic Processing Unit) .The GPU is a processing unit built into the graphics card.The GPU has a number of Vertex Processors and Fragment Processors for 3D rendering. It is a highly parallel processing unit. GPUs have the ability to handle many 3D objects up to 30-50fps per second, like real-time first-person games. GPUs lean against the huge game market, and their technology advances very rapidly. The GPU is a unit that eliminates complex control and cache and maximizes parallel computing. It is well suited for handling the infinite repetitive tasks of simple computation of multimedia data. In addition, GPUs are very inexpensive, very easy to obtain, and offer many benefits, including a Scalable Link Interface (SLI) that allows multiple GPUs to double the processing power.

The present invention analyzes the time share of each encoding submodule through profiling analysis of the H.264 encoder, uses a strategy of speeding up using the GPU from the most time critical part, and also the portion of the submodules that can be easily processed in parallel. I made it an object.

Routines made through the present invention are all developed according to the type and name to be integrated with the x264 code to be integrated in the future, porting with x264 can be carried out without great difficulty, solutions of many transcoders, encoders, etc. that work in conjunction with x264 Can be combined with Through this, it can be applied to various fields such as development of encoding server solution using SLI, application to VC-1 codec, application to H.263 codec, and real time encoding solution of HDTV.

In the case of H.263, the algorithm is simple and there is much room for parallelism. Currently, H.263 is used as a Mandatory codec for video telephony, and since the automated answering service and video call center using video telephony will be activated in the future, H.263 encoders are urgently needed for high speed. In addition, the encoding server solution using SLI enables the development of a server platform that can perform encoding smoothly even if multiple encoding requests are simultaneously received on the Tesla Platform equipped with four GPUs using SLI.

The VC-1 codec, along with H.264, is currently the most promising video compression technology, both of which have been selected as the standard for HD DVD and used as the video codec for IPTV. When the GPU is applied to the VC-1 codec, it can serve as an important backend in the new media market including Silverlight, which can be extended to various fields. In addition, it is possible to devise an ultra-fast algorithm for processing HDTV-class images in real time, and to study parallelism of graphic card level using SLI.

The present invention relates to a technique and method for improving H.264 Codec coding rate through Hardware Complexity-based High Complexity Coding Algorithm. The present invention is carried out in four parts: Common Part, Best Quality Strategy, Trade-Off Strategy, and Best Speed Strategy.

First, in case of Common Part, H.264 performs 1/4 pixel unit of motion estimation to find more accurate motion vector and reduces bit rate, compared to conventional video codec that performs motion estimation of unit of 1/2 pixel. Can be. When encoding of one frame is completed, the frame is decoded into the decoded picture buffer (DPB) of the reference frame. At this time, 1 / 4-resolution frame is generated through Interpolation for Sub-pel Motion Estimation. The Sub-pel Reference Frame Building is a typical parallel processing problem, and the GPU implementation allows it to be 10 times faster than SIMD code. In addition, H.264 basically supports Variable Block Size Motion Estimation, and each block is subdivided into 16x16, 8x16, 16x8, 8x8, 4x8, 8x4, 4x4, etc. Since SAD is a sub-optimal value part of the overall optimal, if you obtain SAD in units of 4x4 in advance, you can combine it and calculate SAD of larger blocks such as 8x4, 4x8 while reducing the calculation amount. This approach is called SAD Reuse. In the 4x4 SAD Surface, threads are arranged to target a 16x16 target area as shown in FIG. 2, and a 40x40 area is copied from the texture in consideration of padding in the shared memory of the block. Threads are in charge of each 16x16 position, and the threads go through a 4x4 area to find the sum of SADs. The SAD surface thus obtained is stored in Global Memory and recycled to obtain a larger block SAD in the same manner as in FIG.

Next, in case of Best Quality Strategy, in order to guarantee the best image quality in H.264 encoding, the accuracy of Motion Estimation and Mode Decision through Rate-Distortion Optimization must be ensured. Motion Estimation must be accurate for the best image quality. Most commercial H.264 encoders use a fast search algorithm to find a sub-optimal solution in a short time rather than applying an optimal solution. In order to find the optimal solution, ESA (Exhaustive Search Algorithm) should be used, which is not practical because the encoding speed is slow even if the exact motion vector is obtained due to too much computation. However, using SEA (Successive Elimination Algorithm), while having the same accuracy as the ESA can reduce the amount of SAD calculation as much as 90% or more.

In addition, to realize optimal quality, the cost of Macroblock's Motion Vector must be calculated accurately, which starts with accurate Motion Vector Prediction. In order to correctly perform Motion Vector Prediction, the neighboring Macroblocks on the top, top right, and left sides must all be determined. However, as shown in FIG. 4, when two macroblocks are spaced apart, parallel processing may be performed in units of rows. This approach is called Staggered Approach, and if you implement it this way, you can expect some performance gains with a little more parallelism.

The trade-off strategy is an approach to speed up encoding by sacrificing some quality and increasing parallelism. To this end, TLP Motion Vector Prediction ensures parallelism on a row basis, and applies Intra-Prediction to all frames simultaneously by applying Modified Intra-Prediction. TLP (Thread Level Parallelism) Motion Vector Prediction should take Median of left, top, and right top neighbor Macroblock for original estimation, but in order to improve parallelism, select the top left neighbor Macroblock instead of left as shown in Fig. 5 to estimate the motion vector. That's how it is. In addition, the above principle should be applied to the estimated motion vector in the sub-block unit inside the macroblock. However, in the TLP approach, the algorithm is simplified by using the same estimate for all the sub-blocks of the current macroblock. In the case of the TLP approach, it can perform parallel processing perfectly line by line, which is much faster than Best Quality Mode. Intra Prediction is a method to select the optimal mode by comparing various patterns made with certain rules in the current reconstructed frame. Intra Prediction is dependent on four neighboring Macroblocks: Reconstruction Left, Top Left, Top, and Right Top, so parallel processing is very difficult like Inter Prediction. However, Error Term is known to have little error even if Intra Prediction is performed with current frame instead of reconstructed frame. When using this method, the dependency on Intra Prediction on all Macroblocks is eliminated, and parallel processing for the entire frame is possible as shown in FIG.

Best Speed Strategy is a speed-priority mode that sacrifices some quality and applies devices such as applying Fast Search Algorithm suitable for parallelism and simply performing Rate-Distortion Optimization. It is mainly suitable for encoding HDTV-quality high resolution video in real time. Unlike SEA or ESA, Fast Search Algorithm is a strategy to find a sub-optimal motion vector by fast stepping forward and moving. Among the Fast Search Algorithms, a model suitable for parallel processing has many points to be examined at the same time, and it is appropriate to proceed to a fixed step without divergent. In this respect, Extended Hexagonal Search Algorithm is suitable for parallel processing. In addition, the Motion Vector Prediction is not obtained separately, but refers to the Motion Vector of the previous frame or refers to the origin (0, 0). In case of rate-distortion optimization, the error is not larger than expected because the best motion vector tends to be concentrated at (0, 0). Intra-Prediction uses the Modified Intra Prediction used in the Trade-off Strategy, allowing both Inter / Intra to encode entire frames at once.

1 is a view showing the overall structure of the H.264 ENCODER.

2 is a view showing a process of obtaining 4X4 SAD SPACE.

Figure 3 shows how to recycle the 4X4 SAD to get a larger block SAD.

4 shows a STAGGERED APPROACH.

5 is a drawing of THREAD LEVEL PARALELLISM PATTERN MOTION PREDICT ION.

6 is a 4X4 LUMA INTRA PREDICTION diagram.

7 is a FAST SEARCH ALGORITHMS diagram.

Claims (1)

H.264 Codec Code Rate Enhancement Technique and Method Using High Complexity Coding Algorithm Based on Hardware Acceleration

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