KR20090071735A - Method of opc by using wafer pattern measure data - Google Patents

Abstract

An optical proximity effect correction method using wafer pattern metering data is provided to massively collect pattern measurement data about the wafer pattern and analyze the collected wafer pattern metering data. A pattern layout to be transferred on a wafer is designed(101). The pattern layout is transferred on the wafer(102). The image contour of the wafer patterns to be transferred on the wafer is calculated(103). The constant area of the pattern layout is matched to the corresponding area of the image contour(104). The measurement line width(CD) values of wafer patterns and the edge difference bias values of the pattern layout are measured(105). The target line widths and the duty data positioned at the location corresponding to the measurement coordinates on the pattern layout of the design patterns are extracted, and are listed in order to calculate the measuring result data(106).

Description

Method of OPC by using wafer pattern measure data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method for optical proximity correction (OPC) on a pattern layout using wafer pattern measurement data.

In order to integrate a semiconductor device such as a DRAM memory device on a wafer, a process of designing a layout of a circuit pattern to be integrated on the wafer is performed. A target pattern layout designed to be implemented on a wafer is formed on a photomask in a mask pattern such as a light shielding pattern or a phase inversion pattern, and an exposure light source is incident on the formed photomask to form an image of the mask pattern. An exposure process is performed to transfer the image onto the wafer. A photoresist layer is selectively exposed on the wafer along the pattern image transferred by the exposure process, and the exposed photoresist layer is developed to form a photoresist pattern. An actual circuit pattern is formed on the wafer by selectively etching the etching target layer on the wafer using the photoresist pattern as an etching mask.

After a wafer pattern such as a photoresist pattern or an actual circuit pattern is formed, a process of measuring whether or not the shape of the wafer pattern matches the pattern shape on the designed target pattern layout is performed. This wafer pattern measurement process is performed to verify the designed target pattern layout, and to reflect the verification result in the design layout to plan a more accurate pattern layout. The characteristics of the semiconductor device integrated on the wafer can be implemented better when the designed target pattern shape is more precisely realized in the actual wafer pattern. The more the amount of wafer pattern measurement data is secured, the more accurately the secured data can represent actual wafer patterns. Accordingly, in order to more accurately verify the designed pattern layout, a larger amount of wafer pattern measurement data is required.

The wafer pattern measurement process may include extracting a design rule or duty data of a corresponding pattern, for example, a gate pattern layout of a transistor, from a total layout data at a specific position of a target pattern layout. Is being performed. In this case, since the gate pattern is repeated in the form of a line and a space, the duty data for the corresponding gate pattern may be given in the form of a line and a space or a ratio thereof.

Subsequently, after extracting the coordinates of the representative duty applied to the gate pattern, the wafer pattern line width (CD) corresponding to the extracted coordinates is measured on the actual wafer. From the measurement result data, the degree of pattern error, for example, the degree of difference of the actual CD of the wafer pattern from the target CD, is grasped, and the layout of the corresponding gate pattern in the target pattern layout is compensated for the pattern error. OPC operation to calibrate is performed.

Numerous different duty transistors are required to construct the circuit of the memory semiconductor device, and thus, the target pattern layout includes gate patterns having different duty, for example, target CD. However, since the duty of the pattern to be measured and the coordinates on the layout of the pattern to be measured are extracted and the measurement is performed on the wafer pattern corresponding to the coordinates, the wafer pattern measurement for more inspection points is difficult. Due to the practical measurement limits for the wafer pattern, the coordinates of the representative duty for the gate pattern of the transistor are selected, and the line width data of the corresponding position is measured only for the gate pattern of the selected transistor.

Since the verification of the target pattern layout and the OPC process require more accurate measurement data, a larger amount of pattern measurement data is required. Therefore, this pattern measurement data is collected in large quantities, and the collected pattern measurement data is analyzed and reflected in the OPC process. Development of a method is required.

The present invention is to propose a method of collecting a large amount of pattern measurement data for the wafer pattern, and analyzing the collected wafer pattern measurement data to correct the optical proximity effect.

One aspect of the invention, the step of designing a pattern layout to be transferred on the wafer; Transferring the pattern layout onto the wafer; Obtaining an image contour of wafer patterns transferred on the wafer; Matching a region of the pattern layout to a region of the image contour; A pattern measurement step of obtaining a pattern measurement value including measurement line width (CD) values of the wafer patterns and edge difference bias values with the pattern layout at a plurality of measurement coordinates on the matched image contour; Target line widths and duty data of design patterns located at positions corresponding to the measurement coordinates on the pattern layout are extracted, and the measurement result data is listed by matching the pattern measurement values with the same coordinates. Obtaining; Analyzing the measurement result data for each target line width and duty of the design pattern to obtain correction offset values for correcting the pattern layout; And applying the correction offset values to the pattern layout to provide an optical proximity effect correction method using wafer pattern measurement data.

The matching area may be set as a chip die area.

The duty data extracts left and right space values, which are distances from other design patterns located on the left and right sides of the design pattern located at the positions corresponding to the measurement coordinates, and is separated from the target line width of the design pattern. It can be obtained by obtaining the ratio.

The analysis of the measurement result data may include obtaining a distribution of average values of the measurement line width values for each duty for each target line width size of the design pattern from the measurement result data and analyzing the distribution of the duty for each target line width size from the distribution diagram. can do.

The analysis of the measurement result data may include a process of analyzing the distribution of the average values of the measurement line width values by obtaining average values of the measurement line width values according to the target line width and the duty of the design pattern from the measurement result data.

The analysis of the measurement result data may include analyzing the distribution of the three sigma values by obtaining three sigma values for each duty based on the target line width size of the design pattern from the measurement result data.

The correction offset values may be obtained as values to compensate for the difference bias values for each duty for each target line width of the design pattern.

An embodiment of the present invention may provide a method for optical pattern effect correction (OPC) of a pattern layout by collecting a large amount of pattern measurement data for a wafer pattern and analyzing the collected wafer pattern measurement data.

1 to 7 are diagrams for explaining the optical proximity effect correction (OPC) method using the wafer pattern measurement data according to an embodiment of the present invention.

Referring to FIG. 1, a pattern measurement process of identifying a wafer pattern implemented on a wafer is performed by a lithography process or a pattern transfer process for implementing a semiconductor device on a wafer. At this time, the shape of the patterns constituting the semiconductor device to be implemented on the wafer is designed as a target pattern layout (101 in FIG. 1). The target pattern layout may be modified through an OPC process in consideration of an optical proximity effect (OPE) or an etching bias accompanying an etching process after exposure, if necessary.

This target pattern layout is transferred onto a wafer through an exposure process or the like to form a wafer pattern (102 in FIG. 1). In this case, the wafer pattern may be a photoresist pattern formed by performing an exposure process on the wafer, and may also be a pattern of an insulating layer or a conductive layer formed by a selective etching process using the photoresist pattern as an etching mask. . A pattern measurement process for the wafer pattern is performed to confirm whether the formed wafer pattern has a shape or size that exactly matches the target pattern layout. At this time, the pattern measurement process is performed in a manner that can be inspected in the measurement equipment or measurement method that can secure a large amount of mass data, for example, in the die area on the wafer corresponding to the pattern layout data. Can be.

1 and 2, the data of the target pattern layout (210 of FIG. 2) is secured, and an image contour (230) of a wafer pattern of a region corresponding thereto is obtained (103 of FIG. 1). Such wafer measurement may be performed using a device capable of obtaining an image of a pattern, such as a scanning electron microscope (SEM).

The data of the target pattern layout 210 may include a line and space pattern for a gate pattern of a transistor, and gate patterns of various sizes and lengths for configuring a circuit of a memory semiconductor device. Can include them. At this time, the target first pattern 211 for the gate pattern of any one type of transistor has a target line width T, a first space S1 with a neighboring target second pattern 212 on the left side, and a neighbor on the right side. The second space S2 with the target third pattern 213 is disposed, and the third space D is disposed with the target fourth pattern 215 on the upper side (or the lower side). The spaces S1, S2, and D between the target patterns 211, 212, 213, and 215 may be extracted by distance calculation from the data of the target pattern layout 210.

The target pattern layout 210 and the data of the image contour 230 of the wafer pattern are image matched (104 in FIG. 1). At this time, the data of the target pattern layout 210 of the region to be pattern-measured is extracted and image-matched to the region of the image contour 230 of the wafer pattern of the region. This area is an area to be pattern-measured and may be set as a chip die area. By this image matching, the target first pattern 211 corresponding to the wafer pattern 231 is image matched, and by the image matching, the edge of the image contour of the wafer pattern 231 and the target first pattern ( The edges of 211 can be compared. Other patterns are also image matched such that the edges are compared.

This image matching is performed and metrology coordinates 270 are set in the image contour 230 region of the wafer pattern. In this case, the measurement coordinates 270 may be set at a large number of points, and the coordinates 270 may be set for hundreds of thousands to millions of points so that all gates of various sizes of the various transistors constituting the memory semiconductor device may be identified. In this case, since the target pattern layout 210 and the measured image contour 230 are image matched, the measurement coordinates 270 are positioned at the same point on the target pattern layout 210, that is, the matching coordinates 271. Done.

In addition, the measurement of the measurement line width M of the wafer pattern 231 is performed by performing pattern measurement at the measurement coordinates 270 of the image contour 230. In this case, the measurement of the measurement line width M is performed by using the difference between the edge of the target first pattern 211 and the edge of the wafer pattern 231 by image matching with the line width T of the target first pattern 211. Can be obtained from the difference of. Together with the measurement data of the measurement line width M, an edge difference bias value, which is a difference between edges, can be obtained (105 in FIG. 1).

On the other hand, since the measurement coordinates 270 are located at the same point on the target pattern layout 210, that is, the matching coordinates 271, the line widths of the target first patterns 211 in the matching coordinates 271 ( T), left and right first and second spaces (S1, S2) and the upper (lower) third space (D) is extracted from the data of the target pattern layout 210 to separate storage unit (250 in FIG. 2) Store in In this case, for example, data about a design rule or duty, such as a ratio of the target line width T and the first (or second) spaces S1 and S2, may be extracted from the data of the target pattern layout 210 to separate the data. It is stored in the storage unit (250 of FIG. 2).

The extracted and measured result data may be listed as a table of measurement result data as shown in FIG. 3. FIG. 3 lists the measurement line width CD measured at the measurement coordinates GdsX and Gds Y and the measured edge difference biases, and also the corresponding coordinates extracted from the data of the target pattern layout 210 of FIG. 2. Length in is listed, the first space (Space 1) and the second space (Space 2), their average (AveSpace), the duty (Duty1, Duty2) and the duty average (AveDuty) obtained from them are listed Shows the measurement result data. This measurement result data is used as raw data used in a subsequent error analysis process.

The measurement result data is analyzed for each target line width and duty of the design pattern to extract correction offset values for correcting the pattern layout (210 in FIG. 2) (107 in FIG. 1), and the obtained correction offset values are used for pattern layout. Feedback 210 to optical proximity effect correction (OPC) (108 in FIG. 1). Accordingly, it is possible to form a wafer pattern more precisely matching the target pattern layout 210.

As such, the process of extracting correction offset values to correct the target pattern layout may be performed by error analyzing the measurement result data of FIG. 3 to extract patterns to be corrected and correction offset values to be applied thereto. . This error analysis process may first require a process of identifying which duty distribution exists in target patterns of a specific size. To this end, a distribution diagram of the histogram of FIG. 4 may be obtained using the measurement result data of FIG. 3. The histogram of FIG. 4 obtains a distribution of average values of line width values for each target line width size of the design pattern from the measurement result data, and shows a distribution of duty applied to each target line width. At this time, the histogram bar of the cumulative line widths shows the line widths to which the target line widths are applied. These histograms allow the analysis of the distribution of the duty in a specific pattern line width.

Also, the pattern error analysis process may include checking average values of the measurement line widths at a specific duty with respect to target patterns of a specific size. To this end, the measurement result data of FIG. 3 is used, and the histogram distribution diagram of FIG. 4 is checked, and the average values of the measurement line width values according to the target line width and duty of the design pattern are shown in nm as shown in the table shown in FIG. 5. You can check with In the table of FIG. 5, it can be seen how many pattern line width average values the duty of a specific target pattern (or gate pattern) for a specific transistor has.

In addition, the pattern error analysis process may include determining how many sigma values are displayed at a specific duty of a specific target pattern (or gate pattern) for a specific transistor. To this end, using the measurement result data of FIG. 3, as shown in FIG. 6, three sigma values according to the target line width and the duty of the design pattern may be checked. By analyzing these three sigma values can be analyzed for the three sigma values that are relatively larger than the standard.

Through this pattern error analysis process, at a specific duty of a specific target pattern (or gate pattern) for a positive transistor, offset correction values for which correction is required may be expressed in graphs as shown in FIG. 7. Can be. These graphs are analyzed to select a target pattern and duty to which the offset correction values are applied, and to perform OPC correction on the target pattern layout 210 of FIG. 2 to apply the offset correction values to the selected target pattern and duty. Since the offset correction values can be substantially obtained as values to compensate for the difference bias values for each duty for each target line width of the design pattern, which can be seen in the data of FIG. 3, by using the OPC correction using the offset correction values, the target pattern layout ( It is possible to implement a wafer pattern that more closely matches 210.

As such, while obtaining wafer pattern measurement values for hundreds of thousands or more of the transistors present in the chip of the semiconductor device, the corresponding duty data of the target pattern layout is extracted, and the pattern error component due to the duty difference is derived from the data. It is possible to extract In addition, various distributions of the measurement data can be represented, thereby enabling layout correction or OPC that can represent more precisely formed wafer patterns.

1 is a flowchart illustrating a method for correcting optical proximity effects using wafer pattern measurement data according to an exemplary embodiment of the present invention.

2 is a diagram schematically illustrating a wafer pattern measurement method according to an exemplary embodiment of the present invention.

3 is a diagram schematically illustrating wafer pattern measurement data according to an exemplary embodiment of the present invention.

4 is a diagram showing an example of a distribution line of measurement line widths using wafer pattern measurement data according to an embodiment of the present invention.

5 is a diagram showing an example of average values of measurement line widths obtained by using wafer pattern measurement data according to an embodiment of the present invention.

FIG. 6 illustrates an example of three sigma values obtained using wafer pattern measurement data according to an embodiment of the present invention.

7 is a diagram showing an example of offset correction values obtained using wafer pattern measurement data according to an embodiment of the present invention.

Claims (7)

Designing a pattern layout to be transferred onto the wafer; Transferring the pattern layout onto the wafer; Obtaining an image contour of wafer patterns transferred on the wafer; Matching a region of the pattern layout to a region of the image contour; A pattern measurement step of obtaining a pattern measurement value including measurement line width (CD) values of the wafer patterns and edge difference bias values with the pattern layout at a plurality of measurement coordinates on the matched image contour; Target line widths and duty data of design patterns located at positions corresponding to the measurement coordinates on the pattern layout are extracted, and the measurement result data is listed by matching the pattern measurement values with the same coordinates. Obtaining; Analyzing the measurement result data for each target line width and duty of the design pattern to obtain correction offset values for correcting the pattern layout; And And applying the correction offset values to the pattern layout to perform optical proximity effect correction (OPC) on the pattern layout. The method of claim 1, The matching region is optical proximity effect correction method using the wafer pattern measurement data is set to the chip die (chip die) area. The method of claim 1, The duty data extracts left and right space values, which are distances from other design patterns located on the left and right sides of the design pattern located at the positions corresponding to the measurement coordinates, and is separated from the target line width of the design pattern. Optical proximity effect correction method using wafer pattern measurement data obtained by obtaining ratio. The method of claim 1, The analysis of the measurement result data Optical proximity effect correction using wafer pattern measurement data which obtains a distribution of average values of the measured linewidth values for each duty by the target linewidth size of the design pattern from the measurement result data and analyzes the distribution of the duty for each target linewidth size from the distribution diagram Way. The method of claim 1, The analysis of the measurement result data And obtaining average values of the measurement line width values according to the target line width and the duty of the design pattern from the measurement result data, and analyzing the distribution of the average values of the measurement line width values. The method of claim 1, The analysis of the measurement result data The optical proximity effect correction method using wafer pattern measurement data for analyzing the distribution of the three sigma values by obtaining the three sigma values for each duty by the target line width size of the design pattern from the measurement result data. The method of claim 1, The correction offset values And an optical proximity effect correction method using wafer pattern measurement data obtained as values for compensating the difference bias values for each duty for each target line width of the design pattern.

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