KR20090070607A - Method of erasing a non volatile memory device - Google Patents

Abstract

An erasing method of a nonvolatile memory device is provided to improve an erasing speed by applying an erasing voltage to a memory block with an abnormal rising hunting pulse shape. A voltage pulse(310) of an abnormal rising hunting pulse shape is applied to a memory block. An abnormal rising hunting pulse includes a rising hunting section and a no down rising section. A voltage level of the abnormal rising hunting pulse drops after instantaneously rising in the rising hunting section. The voltage level of the abnormal rising hunting pulse gradually rises in the no down rising section. An erasing verification is performed after applying the abnormal rising hunting pulse.

Description

Method of erasing a non volatile memory device

The present invention relates to an operation of a nonvolatile memory device, and more particularly, to a method of erasing a nonvolatile memory device that can perform a more efficient and faster speed when performing an erase operation.

A flash memory device, which is one in a nonvolatile memory device, is generally configured to include a plurality of strings in which a plurality of memory cells are connected in series. Such flash memory devices are widely used in various semiconductor devices such as notebooks, personal digital assistants (PDAs), mobile electronic devices such as mobile phones, computer bios, printers, and universal serial bus (USB) drivers.

A memory cell array of a typical flash memory device has a structure in which memory cells are serially connected between a bit line (BL) and a cell source line (CSL). In addition, the NAND flash memory device may be referred to as a drain select line (DSL) and a source selective line (SSL) to electrically connect the memory cell to the bit line BL and the cell source line CSL. Two transistors are connected.

The memory cell of the NAND flash memory device generates Fowler-Nordheim tunneling (FN) through a tunnel oxide layer between floating gates according to a voltage applied to a control gate or a substrate (or bulk, PWELL). An erase operation is performed.

Program and erase operations of the flash device are repeatedly performed under constant voltage conditions. The repetitive program and erase operations deteriorate the tunnel oxide layer, causing a shift in the program and erase threshold voltages. In addition, since the erase operation is performed in units of memory blocks, an error of a specific memory block may occur due to a difference in the speed of erasing the memory blocks belonging to the same memory cell array. To avoid this, the erase voltage and time are determined based on the memory block having the slowest speed during erasing.

As such, the erase time, the erase voltage are determined, and the surface of the silicon constituting the bulk of the memory cell deteriorates during program erasing and programming to the memory cell array, resulting in rapid device distribution and program fail. Is generated.

Accordingly, an aspect of the present invention is to provide a method of erasing a nonvolatile memory device in which an erase voltage is not applied constantly to increase the erase effect and speed when performing an erase operation of the nonvolatile memory device. .

According to an aspect of the present invention, a method of erasing a nonvolatile memory device includes:

After the voltage level is instantaneously raised and lowered for erasing the selected memory block, a randomly rising irregular voltage pulse is applied one or more times.

After the erase operation is performed using the erase voltage in the form of the irregular voltage pulse, an erase verification is performed. When the erase pass does not occur, the erase voltage is increased by a predetermined step voltage to perform the erase verification. It features.

The irregular voltage pulse is applied at a voltage higher by the set step voltage than the irregular voltage pulse applied before.

The random voltage pulse is a hunting rising period that is instantaneously increased to the first voltage level, and lowered to the second voltage level; And an undown rising section gradually rising at the second voltage level.

The voltage is increased stepwise in the undown rising section.

In the undown rising period, the voltage is increased from the second voltage level to the first voltage level.

Erasing method of a nonvolatile memory device according to another aspect of the present invention,

A first erase step of applying an erase voltage as a start voltage to the selected memory block to perform an erase operation; And a second erase that performs an erase operation by applying an irregular voltage pulse that is gradually raised and lowered to a voltage level higher than the start voltage and then lowered when the erase pass is not performed by verifying the first erase performance result. Steps.

The random voltage pulse may include a hunting rising period that is instantaneously increased to a first voltage level higher by a step voltage than the start voltage and then lowered to a second voltage level; And an undown rising section gradually rising at the second voltage level.

The voltage is increased stepwise in the undown rising period.

In the undown rising period, the voltage is increased from the second voltage level to the first voltage level.

And a third erasing step of verifying the result of performing the second erasing and performing an erasing by applying a voltage higher than the maximum voltage level of the second erasing voltage by a set step voltage. do.

Erasing method of a nonvolatile memory device according to another aspect of the present invention,

First erase is performed by applying an irregular voltage pulse that is instantaneously applied to the selected memory block to the first voltage level and then falls to the second voltage level, and slowly rises from the second voltage level to the first voltage level. step; And a second erase step of performing an erase by applying an erase voltage to a third voltage higher than the first voltage level when the erase pass is not verified by verifying the first erase result.

The random voltage pulse may include a hunting rising period that is instantaneously increased to a first voltage level higher by a step voltage than the start voltage and then lowered to a second voltage level; And an undown rising section gradually rising at the second voltage level.

The voltage is increased stepwise in the undown rising period.

In the undown rising period, the voltage is increased from the second voltage level to the first voltage level.

As described above, the erase method of the nonvolatile memory device according to the present invention can increase the erase speed by temporarily applying and then raising the erase voltage during the erase operation of the nonvolatile memory device.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a diagram illustrating energy band banding during an erase operation of a memory cell.

Referring to FIG. 1, a memory cell of a nonvolatile memory device includes a substrate, a floating gate (FG), and a control gate (CG).

In more detail, a tunnel oxide (TO) is formed on a silicon-based substrate. The tunnel oxide TO is a tunnel insulating film. After the floating gate FG is formed on the tunnel oxide TO, an oxide-nitride-oxide (ONO) is formed thereon. Thereafter, a control gate CG of a metal component is formed to form a memory cell. In the above description, only the structure of FIG. 1 for forming an energy band structure of the memory cell is described.

In the above-described structure, the memory cell is programmed to have a high voltage applied to the control gate CG such that electrons of the substrate Bulk pass through the tunnel oxide to the floating gate FG and are trapped.

In the erase operation, a high voltage is applied to the substrate bulk to draw out the electrons trapped in the floating gate FG back to the bulk. 1 shows an energy band at this time. In general, the erase operation is performed in units of memory blocks.

As described above, the erase voltage applied to the substrate in the erase operation for extracting the electrons trapped in the floating gate FG of the memory cell toward the substrate Bulk may be provided as follows.

2A is a diagram illustrating an erase voltage level during an erase operation of a general nonvolatile memory device.

Referring to FIG. 2A, an erase voltage provided to a substrate of a memory block to erase data stored in a memory cell may be provided in the form of one pulse in which a high voltage is applied for a predetermined time.

There is also a method of providing an erase voltage as follows.

FIG. 2B is a diagram illustrating an erase voltage level during an erase operation different from that of FIG. 2A.

Referring to FIG. 2B, instead of providing an erase voltage in a single pulse form at a constant voltage level, a method of applying a plurality of times by increasing the voltage level in the form of a step pulse may be used. A verify pulse is added between each erase voltage pulse to confirm the erase state.

The erase voltage scheme of FIGS. 2A and 2B may be in the form of an erase voltage level that is currently generally used. However, the method of erasing a memory block using the erase voltage as described above also requires an erase operation to be performed according to the memory block having the slowest speed since the erase speed is different for each memory block. As a result, problems continue to arise.

Therefore, a method of increasing the erase speed of a memory block is presented as follows.

3A illustrates an erase voltage level applied to an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, in the first embodiment of the present invention, an erase voltage Verase is first applied with an upnormal rising hunting pulse, and thereafter, a voltage pulse 310 that is increased by a set step voltage is applied. do.

The upnormalizing hunting pulse refers to a pulse having an irregular voltage level in the form of increasing and decreasing the voltage momentarily and then gradually increasing the voltage level again.

FIG. 3B is an enlarged view of the upnormalizing hunting pulse of FIG. 3A.

Referring to FIG. 3B, the shape of the upnormal rising hunting pulse is a rising hunting section A that increases and decreases the voltage level momentarily, and a no down rising section B that gradually increases the voltage level. Can be divided into

In the section A, a voltage is instantaneously applied to a desired voltage level, and then the voltage level is lowered to a predetermined level again. When the erase voltage is instantaneously applied to the substrate Bulk as in the section A, electrons trapped in the floating gate FG are suddenly expelled toward the substrate Bulk.

Thereafter, in the section (B), to gradually increase the voltage level, as shown in FIG. 3B, a method of gradually raising may be used. Of course, it is also possible to gradually increase the voltage with a gentle slope.

Among the electrons trapped in the floating gate FG, electrons which do not escape from the section A gradually exit toward the substrate Bulk in the section B.

After applying the upnormalizing hunting pulse, verification is performed, and if it is not passed for verification, general voltage pulse is applied again to proceed with the erasing. At this time, the pulse voltage is applied as a voltage higher by the set step voltage than the voltage level of the upnormalizing hunting pulse.

In addition, the erase voltage can be provided in the following manner.

4 is a diagram illustrating an erase voltage level applied to an erase operation of a nonvolatile memory device according to a second embodiment of the present invention.

Referring to FIG. 4, according to the second exemplary embodiment of the present disclosure, after erasing the initial voltage of the erase voltage Verase applied to the bulk to erase data stored in the memory cells, the erase verification is performed. And then apply an upnormalizing hunting pulse. At this time, the highest voltage level of the upnormalizing hunting pulse is applied by the set step voltage higher than the initially applied pulse voltage.

In addition, the upnormalizing hunting pulse may be continuously applied to the erase voltage.

5 is a diagram illustrating an erase voltage level applied to an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in the third embodiment of the present invention, all pulse shapes of the erase voltage Verase are applied in the form of upnormalizing hunting pulses, and after the erase voltages of the respective upnormalizing pulse types are provided, verification is performed. A method of applying an erase voltage Verase may be used.

When the erase voltage is applied as in the first to third embodiments, the voltage is instantaneously applied in the form of one or more erase voltage pulses, and then floats instantly by applying an upnormalizing hunting pulse that gradually raises the voltage level. The erase speed can be increased by causing electrons in the gate to escape to the substrate.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram illustrating energy band bending during an erase operation of a nonvolatile memory device.

2A is a diagram illustrating an erase voltage level during an erase operation of a general nonvolatile memory device.

FIG. 2B is a diagram illustrating an erase voltage level during an erase operation different from that of FIG. 2A.

3A illustrates an erase voltage level applied to an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 3B is an enlarged view of the upnormalizing hunting pulse of FIG. 3A.

4 is a diagram illustrating an erase voltage level applied to an erase operation of a nonvolatile memory device according to a second embodiment of the present invention.

5 is a diagram illustrating an erase voltage level applied to an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims (15)

A method of erasing a nonvolatile memory device, comprising applying a randomly rising irregular voltage pulse to the selected memory block after the voltage level is temporarily raised and lowered for erase. The method of claim 1, After the erase is performed using the erase voltage in the form of the irregular voltage pulse, erase verification is performed. If the erase pass is not verified, erase the nonvolatile memory device by applying the irregular voltage pulse by increasing the set step voltage. The method of claim 1, And wherein the irregular voltage pulse is applied at a voltage higher than the previously applied irregular voltage pulse by a set step voltage. The method of claim 1, The irregular voltage pulse, A hunting rising period that is instantaneously increased to a first voltage level and then lowered to a second voltage level; And an undown rising period gradually rising at the second voltage level. The method of claim 4, wherein And a voltage is increased stepwise in the undown rising period. The method of claim 4, wherein In the undown rising period, a voltage is increased from the second voltage level to the first voltage level. A first erase step of applying an erase voltage as a start voltage to the selected memory block to perform an erase operation; And A second erasing step of verifying the first erasing result and performing an erase operation by applying an irregular voltage pulse that is gradually raised and lowered to a voltage level higher than the start voltage and then lowered when the erase pass is not performed. Erasing method of a nonvolatile memory device comprising a. The method of claim 7, wherein The irregular voltage pulse, A hunting rising period which is temporarily increased to a first voltage level higher by a step voltage than the start voltage and then lowered to a second voltage level; And an undown rising period gradually rising at the second voltage level. The method of claim 8, And a voltage is increased stepwise in the undown rising period. The method of claim 8, In the undown rising period, a voltage is increased from the second voltage level to the first voltage level. The method of claim 7, wherein And a third erasing step of verifying the result of performing the second erasing and performing an erasing by applying a voltage higher than the maximum voltage level of the second erasing voltage by a set step voltage. An erase method for a nonvolatile memory device. First erase is performed by applying an irregular voltage pulse that is instantaneously applied to the selected memory block to the first voltage level and then falls to the second voltage level, and slowly rises from the second voltage level to the first voltage level. step; And A second erase step of performing an erase by applying an erase voltage to a third voltage higher than the first voltage level when the erase pass is not verified by verifying the first erase result; Erasing method of a nonvolatile memory device comprising a. The method of claim 12, The irregular voltage pulse, A hunting rising period which is temporarily increased to a first voltage level higher by a step voltage than the start voltage and then lowered to a second voltage level; And an undown rising period gradually rising at the second voltage level. The method of claim 13, And a voltage is increased stepwise in the undown rising period. The method of claim 13, In the undown rising period, a voltage is increased from the second voltage level to the first voltage level.

Images