KR20090070021A - Liquid crystal display device - Google Patents

Abstract

AN LCD(Liquid Crystal Display) for reducing the number of the data-lines is provided to reduce the number of data lines by arranging RGB pixel areas in a horizontal stripe structure. A thin film transistor(26) of a first pixel region is connected to a first gate line and one data line among first/second data lines. A first pixel electrode(32) is connected to the thin film transistor. A second thin film transistor of the second pixel region is connected to the second gate line and the data line of the other one among first/second data lines. A second pixel electrode is connected to the second thin film transistor.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

Due to the development of the information society, display devices capable of displaying information have been actively developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Among these, the liquid crystal display device has advantages such as light weight, small size, low power consumption, and full color video, and is widely applied to mobile phones, navigation, monitors, and televisions.

The LCD displays an image corresponding to a video signal by adjusting the light transmittance of the liquid crystal cells on the liquid crystal panel.

The liquid crystal display device includes a first substrate, a second substrate, and a liquid crystal layer.

The first substrate is arranged by crossing a plurality of gate lines and a plurality of data lines. A plurality of pixel regions are defined by each gate line and each data line.

Each pixel region includes a thin film transistor connected to a gate line and a data line, and a pixel electrode connected to the thin film transistor.

A common line is arranged across each pixel area. The common line overlaps the pixel electrode to form a storage capacitance.

The second substrate corresponds to each pixel region defined in the first substrate, and a color filter layer including a red color filter, a green color filter, and a blue color filter is formed, a black matrix is formed between each color filter, and the color filter layer The common electrode is formed on the black matrix.

The liquid crystal layer includes a plurality of liquid crystal molecules.

An electric field is generated between the first and second substrates by the data voltage applied to the pixel electrode and the common voltage applied to the common electrode, and the liquid crystal molecules of the liquid crystal layer are displaced by the electric field. It transmits / transmits the light provided by, so that the image is displayed.

In the conventional liquid crystal display, data voltages are applied to each pixel electrode on the gate line for each gate line.

In this case, a coupling occurs in which the data voltage applied to each pixel region on the previous gate line affects the data voltage applied to each pixel region on the gate line, and then the data voltage applied to each pixel region on the gate line. This fluctuates, and the desired image is not displayed and the image quality deteriorates.

In the conventional liquid crystal display, each pixel area on the gate line is arranged in the order of the red pixel area, the green pixel area, and the blue pixel area. Each pixel area on the next gate line is also arranged in the order of the red pixel area, the green pixel area, and the blue pixel area. The pixel regions arranged in this manner are arranged to have pixel regions of the same color in the vertical direction, and thus have a vertical stripe structure.

In such a vertical stripe structure, a data line is provided for each pixel area on the gate line.

When the number of data lines increases, a data voltage to be supplied to each data line needs to be generated, and the circuit of the data driver generating the data voltage becomes complicated. When the circuit of the data driver is complicated in this manner, the size of the data driver is increased and the cost is increased.

An object of the present invention is to provide a liquid crystal display device which can reduce the number of data lines to facilitate data driving, reduce cost, and simplify a circuit of a data driver for data driving.

Another object of the present invention is to provide a liquid crystal display device which can improve image quality by minimizing coupling by changing the structure of a common line.

According to the present invention, a liquid crystal display device includes a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines, wherein the pixel regions include a first pixel region, a second pixel region, and a third pixel region. A pixel region, wherein the first to third pixel regions are defined along a length direction of the data lines, and the first and second pixel regions are parallel to the first and second gate lines in a first direction. Defined by first and second data lines crossing the first and second gate lines and parallel to a second direction, wherein the first pixel area includes the first gate line and the first and second gate lines. A first thin film transistor connected to any one of the data lines; And a first pixel electrode connected to the first thin film transistor, wherein the second pixel region is a first thin film transistor connected to the second gate line and another data line among the first and second data lines. ; And a second pixel electrode connected to the second thin film transistor.

According to the present invention, by arranging the red pixel area, the green pixel area, and the blue pixel area in a horizontal stripe structure, the number of data lines can be reduced to reduce costs.

The present invention can improve image quality by preventing coupling of data voltages applied to pixel electrodes by disposing common lines between neighboring pixel electrodes.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 1, in the liquid crystal display, a plurality of gate lines G1 to G (3m / 2) and a plurality of data lines S1 to S (2n) are arranged to cross each other.

In the present exemplary embodiment, two pixel areas may be defined by two gate lines G1 and G2 and two data lines S1 and S2. For example, the first and second pixel regions G11 and B11 may be defined by the first and second gate lines G1 and G2 and the first and second data lines S1 and S2. have.

As illustrated in FIG. 1, the first thin film transistor may be connected to the first gate line G1 and the second data line S2 and disposed in the first pixel region (green pixel region G11). The second thin film transistor may be connected to the second gate line G2 and the first data line S1 and disposed in the second pixel area (blue pixel area B11). The green pixel area G11 is an area capable of displaying green color, and the blue pixel area B11 is an area capable of displaying blue color.

On the contrary, the first and second thin film transistors may be disposed. That is, although not shown in FIG. 1, the first thin film transistor may be connected to the first gate line G1 and the first data line S1 and disposed in the first pixel region G11. The second thin film transistor may be connected to the second gate line G2 and the second data line S2 and disposed in the second pixel region B11.

In the present embodiment, a description will be given of the electron thin film transistor structure shown in FIG. 1.

The first pixel electrode may be connected to the first thin film transistor and disposed in the first pixel region G11. The second pixel electrode may be connected to the second thin film transistor and disposed in the second pixel region B11.

As such, in the present exemplary embodiment, the first and second pixel regions G11 and B11 are formed by the first and second gate lines G1 and G2 and the first and second data lines S1 and S2. The first thin film transistor and the first pixel electrode may be disposed in the first pixel region G11, and the second thin film transistor and the second pixel electrode may be disposed in the second pixel region B11.

In addition, third and fourth pixel regions R12 and G12 may be defined by the second gate line G2, the third gate line G3, and the first and second data lines S1 and S2. Can be.

As illustrated in FIG. 1, the third thin film transistor may be connected to the second gate line G2 and the second data line S2 and disposed in the third pixel region (red pixel region R12). The fourth thin film transistor may be connected to the third gate line G3 and the first data line S1 and disposed in the fourth pixel area (green pixel area G12). The red pixel area R12 is an area capable of displaying red color, and the green pixel area G12 is an area capable of displaying green color.

On the contrary, the third and fourth thin film transistors may be disposed. That is, although not shown in FIG. 1, the third thin film transistor may be connected to the second gate line G2 and the first data line S1 and disposed in the third pixel region R12. The fourth thin film transistor may be connected to the third gate line G3 and the second data line S2 and disposed in the fourth pixel region G12.

In the present embodiment, a description will be given of the electron thin film transistor structure shown in FIG. 1.

The third pixel electrode may be connected to the third thin film transistor and disposed in the third pixel region R12. The fourth pixel electrode may be connected to the fourth thin film transistor and disposed in the fourth pixel region G12.

As described above, in the present exemplary embodiment, the third and fourth pixel regions R12 and G12 are formed by the second and third gate lines G2 and G3 and the first and second data lines S1 and S2. The third thin film transistor and the third pixel electrode may be disposed in the third pixel region R12, and the fourth thin film transistor and the fourth pixel electrode may be disposed in the fourth pixel region G12.

As described above, the exemplary embodiment of the present invention is a pixel in the order of the green pixel area, the blue pixel area, the red pixel area, and the green pixel area in the vertical direction along the vertical direction. The electrodes are arranged.

The arrangement is the same for the pixel areas arranged by the third data line S3, the fourth data line S4, and the fifth and sixth data lines S5 and S6.

Therefore, as shown in FIG. 1, in the present exemplary embodiment, pixel regions capable of displaying the same color in the horizontal direction may be arranged, and thus may have a horizontal stripe structure.

In the present exemplary embodiment, the second gate line G2 is shared between the second pixel region B11 and the third pixel region R12. That is, the second thin film transistor of the second pixel region B11 and the third thin film transistor of the third pixel region R12 may be simultaneously turned on by the scan signal supplied to the second gate line G2.

In the present exemplary embodiment, the red pixel region R11, the green pixel region G11, and the like are arranged in the order of the red pixel region, the green pixel region, and the blue pixel region in the horizontal direction (vertical stripe structure) in the vertical direction. According to the arrangement in the order of the blue pixel areas B11 (horizontal stripe structure), the number of data lines S1 to S (2n) may be reduced by about one third as compared with the related art.

2 is a plan view illustrating two pixel areas defined in a vertical direction in the liquid crystal display according to the present invention.

In FIG. 2, two pixel areas are typically defined in the vertical direction. However, in the liquid crystal display of the present exemplary embodiment, the two pixel areas may be repeatedly defined and arranged.

Referring to FIG. 2, first and second gate lines 12 and 42 are disposed in parallel in a first direction. The first and second data lines 57 and 27 are disposed in parallel in the second direction. First and second pixel areas (green pixel area and blue pixel area) are defined by the first and second gate lines 12 and 42 and the first and second data lines 57 and 27. Can be.

A first thin film transistor 26 is electrically connected to the first gate line 12 and the second data line 27 to be disposed in the first pixel area, and the second gate line 42 and the second gate line are disposed in the first pixel area. The second thin film transistor 56 is electrically connected to the first data line 57 and disposed in the second pixel area.

A first pixel electrode 32 is electrically connected to the first thin film transistor 26 through a first contact hole 30 to be disposed in the first pixel area, and a second to the second thin film transistor 56. The second pixel electrode 62 is electrically connected to the second pixel region through the contact hole 60.

The first common line 18 is overlapped along the edge area of the first pixel electrode 32. A first storage capacitance may be formed by overlapping the first pixel electrode 32 and the first common line 18.

The second common line 48 is overlapped along the edge area of the second pixel electrode 62. A second storage capacitance may be formed by overlapping the second pixel electrode 62 and the second common line 48.

Both ends of the first common line 18 and the second common line 48 may be electrically connected to both ends thereof. That is, one end of the first common line 18 and one end of the second common line 48 are electrically connected to the first connection part 33, and the other end of the first common line 18 and the second end of the first common line 18. The other end of the common line 48 may be electrically connected to the second connection part 35.

Since the first pixel electrode 32 and the second pixel electrode 62 should be separated by the first pixel region and the second pixel region, the first and second pixel electrodes 32 and 62 may be used. May be spaced apart from each other.

In this case, an auxiliary common line (third common line 34) electrically connected to the first connection part 33 and the second connection part 35 between the first and second pixel electrodes 32 and 62 may be formed. Can be arranged.

The auxiliary common line 34 may be disposed to be spaced apart from the first pixel electrode 32 and the second pixel electrode 62 at the same interval. The influence of the data voltage supplied to the first pixel electrode 32 by the common voltage supplied to the auxiliary common line 34 may affect the data voltage supplied to the second pixel electrode 62. .

The electric field generated between the data voltage previously supplied to the first pixel electrode and the data voltage supplied to the second pixel electrode is the data supplied to the first pixel electrode 32 by the auxiliary common line 34 of the present embodiment. Since the voltage is used to generate an electric field with the common voltage supplied to the auxiliary common line 34, the data voltage supplied to the second pixel electrode 62 is the data voltage supplied to the first pixel electrode 32. The electric field is not generated by this. Accordingly, the data voltage supplied to the second pixel electrode 62 is not affected by the data voltage supplied to the first pixel electrode 32, so that a coupling phenomenon does not occur. Therefore, image quality can be improved.

The same common voltage may be supplied to the first and second common lines 18 and 48 and the auxiliary common line 34.

Although not shown in FIG. 2, the third thin film transistor and the third pixel electrode may be disposed in the third pixel area (red pixel area) in common with the second gate line 42. The third thin film transistor may be electrically connected to the second gate line 42 and the second data line 27, and the third pixel electrode may be electrically connected to the third thin film transistor.

A third gate line may be disposed parallel to the second gate line 42.

The third pixel area and the fourth pixel area may be defined by the second gate line 42, the third gate line, and the first and second data lines 57 and 27.

A fourth thin film transistor and a fourth pixel electrode may be disposed in the fourth pixel area (green pixel area). The fourth thin film transistor may be electrically connected to the third gate line and the first data line 57 and disposed in the fourth pixel area. The fourth pixel electrode may be electrically connected to the fourth thin film transistor and disposed in the fourth pixel area.

The second thin film transistor 56 and the third thin film transistor may be simultaneously turned on by the gate signal supplied to the second gate line 42. The data voltage supplied to the first data line 57 is applied to the second pixel electrode 62 via the second thin film transistor 56. The data voltage supplied to the second data line 27 is applied to the third pixel electrode via the third thin film transistor.

Accordingly, the second gate line 42 may be simultaneously displayed in the second and third pixel areas by activating the second gate line 42.

3 is a cross-sectional view illustrating two pixel areas defined in a vertical direction in the liquid crystal display according to the present invention.

2 and 3, each of the first and second gate lines 12 and 42 and the first and second gate lines 12 and 42 on the substrate 10 in parallel in a first direction. First and second gate electrodes 14 and 44 connected to the first and second common lines 18 and 48 having a closed loop in the first and second pixel areas, and the first and second gate electrodes 14 and 44. First and second connectors 33 and 35 connecting the common lines 18 and 48 and the first and second connectors 33 and 35 between the first and second pixel regions. The auxiliary common line 34 is formed. A first auxiliary gate electrode 16 may be formed to be spaced apart from the first gate electrode 14, and a second auxiliary gate electrode 46 may be formed to be spaced apart from the second gate electrode 44. The first and second auxiliary gate electrodes 16 and 46 have a first source / drain electrodes 24a and 24b and a second source / drain electrodes 54a and 54b which will be described later. The parasitic capacitance between the gate electrodes 14 and 44 and the source electrodes 24a and 54a generated when shifted by misalignment may be disposed to prevent a change in parasitic capacitance.

A gate insulating layer 20 is formed on the substrate 10 including the first and second gate lines 12 and 42.

First and second electrodes including active layers 22a and 52a and ohmic contact layers 22b and 52b on the gate insulating layer 20 corresponding to the first and second gate electrodes 12 and 42. The semiconductor layers 22 and 52 are formed.

First source / drain electrodes 24a and 24b and second source / drain electrodes 54a and 54b on the substrate 10 including the first and second semiconductor layers 22 and 52; The first and second data lines 57 and 27 are formed parallel to the second direction. The first source / drain electrodes 24a and 24b are spaced apart from each other, and the second source / drain electrodes 54a and 54b are spaced apart from each other. The first data line 57 is connected to the first source electrode 54a, and the second data line 27 is connected to the second source electrode 24a.

A first thin film transistor 26 is formed by the first gate electrode 14, the first semiconductor layer 22, and the first source / drain electrodes 24a and 24b, and the second gate electrode ( 44, a second thin film transistor 56 may be formed by the second semiconductor layer 52 and the second source / drain electrodes 54a and 54b.

A passivation layer 28 is formed on the substrate 10 including the first and second data lines 57 and 27. A first contact hole 30 is formed to penetrate the passivation layer 28 to expose or penetrate the first drain electrode 24b, and expose the second drain electrode 54b to penetrate the passivation layer 28. The second contact hole 60 may be formed to penetrate or penetrate.

A first pixel electrode 32 is formed in the first pixel region on the passivation layer 28 so as to be electrically connected to the first drain electrode 24b, and is electrically connected to the second drain electrode 54b in the second pixel region. The second pixel electrode 62 may be formed to be connected to each other.

An edge region of the first pixel electrode 32 may overlap the first common line 18, and an edge region of the second pixel electrode 32 may overlap the second common line 48. A gate insulating layer 20 and a passivation layer 28 may be formed between the first pixel electrode 32 and the first common line 18 and between the second pixel electrode 32 and the second common line 48. Can be formed. Therefore, a first storage capacitance is formed by the first common line 18, the gate insulating layer 20, the passivation layer 28, and the first pixel electrode 32, and the second common line 48 and the gate insulating layer are formed. The second storage capacitance may be formed by the protective layer 28 and the second pixel electrode 62.

The auxiliary common line 34 connected to the first and second connection parts 33 and 35 may be formed between the first and second pixel electrodes 32 and 62. The auxiliary common line 34 may be formed to be spaced apart from the first pixel electrode 32 and the second pixel electrode 62 at equal intervals.

1 is a view showing a liquid crystal display device according to the present invention.

2 is a plan view illustrating two pixel regions defined in a vertical direction in a liquid crystal display according to the present invention;

3 is a cross-sectional view illustrating two pixel areas defined in a vertical direction in a liquid crystal display according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: substrate 12, 42: gate line

14, 44: gate electrode 16, 46: auxiliary gate electrode

18, 34, 48: common line 20: gate insulating layer

22: semiconductor layers 24a and 54a: source electrode

24b, 54b: drain electrode 28: protective film

30, 60: contact hole 32, 62: pixel electrode

33, 35: connection

Claims (9)

A plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines, The pixel regions include a first pixel region, a second pixel region, and a third pixel region, The first to third pixel areas are defined along the length direction of the data lines. The first and second pixel areas cross first and second gate lines parallel to a first direction and first and second data lines to cross the first and second gate lines and parallel to a second direction. Is defined by The first pixel area is, A first thin film transistor connected to the first gate line and one of the first and second data lines; And A first pixel electrode connected to the first thin film transistor, The second pixel area is A first thin film transistor connected to the second gate line and the other one of the first and second data lines; And And a second pixel electrode connected to the second thin film transistor. The liquid crystal display of claim 1, wherein the first to third pixel areas are a green pixel area, a blue pixel area, and a red pixel area. The display device of claim 1, further comprising: a first common line disposed along an edge area of the first pixel electrode; A second common line disposed along an edge region of the second pixel electrode; And first and second connection parts electrically connecting both ends of the first and second common lines. The liquid crystal display of claim 3, further comprising a third common line electrically connected to the first and second connectors and disposed between the first and second pixel electrodes. The liquid crystal display of claim 4, wherein the third common line is disposed at equal intervals from each of the first and second pixel electrodes. The display device of claim 1, wherein the pixel areas further include a fourth pixel area, wherein the fourth pixel area is a green pixel area, The third and fourth pixel regions may cross the second and third gate lines and the second and third gate lines that are parallel to the first direction and are parallel to the second direction. And second data lines, The third pixel area is, A third thin film transistor connected to the second gate line and one of the first and second data lines; And A third pixel electrode connected to the third thin film transistor, The fourth pixel area is, A fourth thin film transistor connected to the third gate line and the other one of the first and second data lines; And And a fourth pixel electrode connected to the fourth thin film transistor. The display device of claim 6, further comprising: a fourth common line disposed along an edge region of the third pixel electrode; A fifth common line disposed along an edge area of the fourth pixel electrode; And third and fourth connectors electrically connecting both end regions of the fourth and fifth common lines. The liquid crystal display of claim 7, further comprising a sixth common line electrically connected to the third and fourth connectors and disposed between the third and fourth pixel electrodes. The liquid crystal display of claim 8, wherein the sixth common line is disposed at equal intervals from each of the third and fourth pixel electrodes.

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