KR20090068618A - Method of operating a non volatile memory device - Google Patents

Abstract

An operation method of the non-volatile memory device is provided, which heightens the reliability of the program verification by performing the program verification while comparing data between the redundancy page buffer and the page buffer. The data to be programmed are inputted to the latch of the page buffer(S201). If the input of data is completed, the program is performed(S203). The program verification is performed. The program path is confirmed(S207). If the program path is performed, the program is completed(S217) and the program operation is terminated. In case of non-pass of the program, data of the page buffers is loaded(S209). According to data of the first page buffer connected to the bit line which is fail-processed, the program is proceeded(S211) or state of data of the second page buffer except for the first page buffer is judged(S213).

Description

Method of operating a non volatile memory device

The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a method of operating a nonvolatile memory device such that an error does not occur in a verification operation performed after a program operation.

The semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes a dynamic RAM (DRAM) and a static RAM (SRAM). ROM is non-volatile memory that does not lose its stored data even when its power is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory. Among nonvolatile memories, flash memory is widely used in computers and memory cards because it has a function of electrically erasing data of cells.

Flash memory is divided into NOR type and NAND type according to the connection state of cells and bit lines. NOR flash memory is a type in which two or more cell transistors are connected in parallel to one bit line. The NOR flash memory stores data using a channel hot electron method and uses the Fowler-Nordheim tunneling method. Clear the data. In the NAND flash memory, two or more cell transistors are connected in series to one bit line, and data is stored and erased using an F-N tunneling scheme. Generally, NOR flash memory is disadvantageous for high integration because of high current consumption, but it has an advantage that it can easily cope with high speed, and NAND flash memory uses less cell current than NOR flash memory, which is advantageous for high integration. There is this.

The flash memory device improves the use efficiency by applying a repair technology that replaces a column including a memory cell in which a fail occurs among memory cells for storing data with a redundancy column. Because of the repair technology, the page buffer of the flash memory device is also connected to a page buffer (hereinafter referred to as a normal page buffer) to a normal column, a page buffer (failed page buffer) to a failed column, and a redundancy column. It can be divided into a page buffer (redundancy page buffer). At this time, the column address information is stored through fuse cutting to distinguish a failed page buffer or a page buffer connected to a redundancy column.

In the page buffer, operation control may be applied differently depending on the connected columns, and program verification is one of them.

After an operation of programming data into a memory cell, the flash memory device necessarily follows a verify operation that determines whether the program is normally programmed. Memory cells that are not passed in the verify operation are reattempted to be programmed. However, if the program does not pass repeatedly a predetermined number of times, a post-processing process is required. If the number of failed memory cells is greater than or equal to the set number, the corresponding memory block may not be used for bad block processing.

The process of verifying the verification uses a verification signal output from the verification means included in the page buffer, and the next program can be performed only when the verification result passes in all the page buffers.

To this end, a flash memory device typically checks a failed page buffer using fuse cutting information and executes a program pass signal by setting a '1' data value to a latch of the corresponding page buffer before executing a program. The latches of the normal page buffer and the redundancy page buffer latch data for programming. When the program proceeds through the above process, the normal page buffer and the redundancy page buffer output the program pass signal according to the degree to which they are programmed in the memory cell, and the failed page buffer outputs the program pass signal in a fixed manner and does not affect the operation. Do not.

However, in the process of inputting data from some of the vulnerable page buffers, there is a problem that the latched '1' data value is changed to '0' data value due to the capacitor component of the line. If the buffer is a failed page buffer, it can't pass continuously while the program is in progress, causing a malfunction.

Accordingly, an object of the present invention is to provide a method of operating a nonvolatile memory device in which verification can be performed normally by preventing malfunction of a page buffer connected to a failed memory cell when performing program verification of the nonvolatile memory device. It is.

Method of operating a nonvolatile memory device according to a feature of the present invention,

A method of operating a nonvolatile memory device, the method comprising: performing a program and performing program verification; Loading data of page buffers if the program is not passed as a result of the verification; Among the loaded data, executing a program according to data of a first page buffer connected to a failed bit line, or determining a state of data of a second page buffer except the first page buffer; And determining the data state of the second page buffer to proceed with the program or to terminate the program.

The second page buffer may include a fourth page buffer connected to a bit line that operates normally with a third page buffer connected to the redundant bit line repaired with respect to the failed bit line.

Prior to executing the program, setting the first page buffer to a first data state using a column address; And dividing the second page buffer by using the column address, and setting the second page buffer to a first or second data state according to input data.

If the data state of the first page buffer is a first data state, executing a program; And in the case of the second data state, checking the data state of the second page buffer.

When the state of the first page buffer is the first data state, the first page buffer is set as a program pass.

When the data state of the second page buffer is the first data state, it is determined that the program is completed, and the program is terminated. When the second data state is the second page buffer, the program is performed.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

A method of operating a nonvolatile memory device, the method comprising: performing a program and performing program verification; Loading data of page buffers if the program is not passed as a result of the verification; Among the loaded data, the program is executed according to the data of the first page buffer connected to the failed bit line, or the data state of the second page buffer which is a redundancy page buffer replaced by the failed bit line is determined. step; Performing a program according to a data state of the second page buffer or determining a state of data of a third page buffer connected to a bit line including a normally operating memory cell; And determining the data state of the third page buffer to proceed with the program or to terminate the program.

Prior to executing the program, setting the first page buffer to a first data state using a column address; And dividing the second page buffer from the third page buffer by using the column address, and setting the second and third page buffers to a first or second data state according to input data.

When the data state of the first page buffer is the first data state, the program is performed. When the data state of the first page buffer is the second data state, the data state of the second page buffer is checked.

When the state of the first page buffer is the first data state, the first page buffer is set as a program pass.

When the data state of the second page buffer is the first data state, the data state of the third page buffer is determined. When the data state of the second page buffer is the second data state, the program is performed.

When the data state of the third page buffer is the first data state, it is determined that the program is completed, the program is terminated, and when the second data state is the second data state, the program is performed.

As described above, in the method of operating a nonvolatile memory device according to the present invention, program verification may be performed by comparing data between a page buffer connected to a fail-nan memory cell and a redundancy page buffer, thereby increasing reliability of program verification.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1A is a block diagram illustrating the structure of a flash memory device.

Referring to FIG. 1A, a flash memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an input / output controller 140, an X decoder 150, and a controller. 160.

In the memory cell array 110, memory cells for data storage are connected to a word line WL and a bit line BL, and a main cell unit 111 in which data is stored and a fail-memory in the main cell unit 111. A redundancy cell section 112 including redundancy cells for operating in place of the column line including the cell is included.

The page buffer unit 120 is composed of page buffers connected to a pair of bit lines of the memory cell array 110. In an embodiment of the present invention, the page buffer unit 120 is connected to a bit line including a fail-nan memory cell of the main cell unit 110. The first page buffer 121 and a second page buffer 122 connected to a bit line including a normal memory cell and a third page buffer 123 connected to a column of the redundancy unit 112 are representatively shown. It was.

The Y decoder 130 provides a data input / output path between the page buffer unit 120 and the input / output control unit 140 according to a control signal of the control unit 160, and the input / output control unit 140 is provided by the Y decoder 130. Input / output data input from outside through data input / output path. The X decoder 150 selects a word line of the memory cell array 110 according to a control signal of the controller 160.

In addition, the controller 160 controls the memory cell array 110, the page buffer unit 120, the Y decoder 130, the input / output control unit 140, and the X decoder 150.

FIG. 1B is a partial circuit diagram of the page buffer of FIG. 1A.

Referring to FIG. 1B, a first page buffer 121 connected to a bit line including a fail-nan memory cell and a third page buffer connected to a redundancy bit line replacing a bit line including the fail-nan memory cell. Only 123 is shown.

The first page buffer 121 includes first and second inverters IN1 and IN2, a first PMOS transistor P1, and first and second NMOS transistors N1 and N2. The third page buffer 123 includes third and fourth inverters IN3 and IN4, a second PMOS transistor P2, and third and fourth NMOS transistors N3 and N4.

The first and second inverters IN1 and IN2 are configured by the first latch L1 and are connected to the node MSB1 and the node MSB1_N. The third and fourth inverters IN3 and IN4 are configured by the third latch L3 and are connected between the node MSB3 and the node MSB3_N.

The gate of the first PMOS transistor P1 is connected to the node MSB1_N, and outputs a power supply voltage as the first program verification signal MSB1VER_N according to the voltage level of the node MSB1_N. The first program verify signal MSB1VER_N is output at a high level while the program is in progress, and when the program is completed, the high level signal is not output to the floating state. When the program verify signals output by all the page buffers are in the floating state at the high level, the controller 160 determines that the program is passed to all the memory cells.

The first NMOS transistor N1 is connected between the node MSB1_N and the node K1, and the second data input signal DATALOAD_N is input to the gate of the first NMOS transistor N1. The second NMOS transistor N2 is connected between the node MSB1 and the node K1, and the first data input signal DATALOAD is input to the gate of the second NMOS transistor N2. The first data input signal DATALOAD and the second data input signal DATALOAD_N are inverted.

The gate of the second PMOS transistor P2 is connected to the node MSB3_N and outputs a power supply voltage as the third program verification signal MSB3VER_N according to the voltage level of the node MSB3_N. The third program verification signal MSB3VER_N is output at a high level when the program is in progress, and when the program is completed, the high level signal is not output to the floating state.

The third NMOS transistor N3 is connected between the node MSB3_N and the node K2, and the second data input signal DATALOAD_N is input to the gate of the third NMOS transistor N3. The fourth NMOS transistor N4 is connected between the node MSB3 and the node K2, and the first data input signal DATALOAD is input to the gate of the fourth NMOS transistor N4.

The nodes MSB1_N and MSB3_N may be referred to as verification nodes capable of confirming program verification. That is, if the nodes MSB1_N and MSB3_N are '1' data values, this indicates a program pass, and if the nodes MSB1_N and MSB3_N are '0' data values, a program is not passed.

The node K1 and the node K2 are both connected to the input / output unit 140 through the data output path of the Y decoder 130.

The page buffer circuit according to the embodiment of the present invention as described above performs program verification as follows.

2 is a flowchart illustrating a method of operating a flash memory device according to an exemplary embodiment of the present invention.

2, the description of the operation of the second page buffer 122 connected to the bit line including the normal memory cell is omitted, and the third page buffer redundant with the failed first page buffer 121 ( The operation of 123 will be described.

Referring to FIG. 2, first, in order to program data in a flash memory device, data to be programmed is input to a latch of a page buffer (S201). Data entry is performed as follows.

First, '1' data is input to the node MSB1_N of the first latch L1 of the failed first page buffer 121 using the column address. Data to be programmed is stored in the third page buffer 123.

In order to store the data to be programmed, the Y decoder 130 provides a path with the input / output controller 140, and the first data input signal DATALOAD or the second data input signal DATALOAD_N is input to the node MSB3_N of the latch. Enter the data to be programmed in).

When data input is completed, the program operation of the flash memory device is executed (S203), and the page buffers perform program verification (S205).

After the program is performed, program verification is performed (S205), and it is checked whether the program passes (S207). If the program passes, the program is completed (S217), and the program operation ends.

However, if not a program pass, data is loaded into the verification nodes of all page buffers (S209). In the data loading, the controller 150 reads the data of the node MSB1_N of the first latch L1 and the node MSB3_N of the third latch L3 through the Y decoder 130. Of course, data of a normal page buffer circuit also reads data of the same verification node.

The controller 150 compares the data of the first page buffer 121 and the third page buffer 123 with the data of the normal page buffer circuit. It is checked whether the data of the node MSB1_N of the first latch L1 is '0' (S211). If the data of the node MSB1_N of the first latch L1 is '1' instead of '0', '1' is normally input to the latch of the failed page buffer. Therefore, since the cause of failure in the path is a redundant page buffer or a normal page buffer, the program is executed once more (S203). When the flash memory device executes a program, the program is executed by a predetermined number of times while increasing the program voltage by an ISPP (Incremental Step Pulse Programming) method.

Therefore, if the data of the first page buffer 121 is '1' as a result of the determination in step S211, the program voltage is increased and the program is executed again according to the normal program procedure.

However, if the data of the first page buffer 121 in step S211 is '0', it is determined whether the data of the node MSB3_N of the third latch L3 of the third page buffer 123, which is the redundancy page buffer, is '0'. (S213).

If the data of the third page buffer 123 is '0', it is determined that the program is not completed yet, and the program is executed again (S203). However, if the data of the third page buffer 123 is '1' instead of '0', it is determined whether the data of the normal page buffer is '0' (S215).

If the normal page buffer data is '0', the program is executed again (S203). If the normal page buffer data is '1', the program is determined to be complete (S217), and the program is terminated. Steps S213 and S215 may be performed in a reverse order. Alternatively, the step S213 and step S215 may be performed without distinguishing between the redundancy page buffer and the normal page buffer.

In other words, data can be compared by dividing into a failed page buffer and a normal page buffer (including a redundant page buffer).

When the above steps S211 to S215 are performed, the failed page buffer, the redundancy page buffer, and the normal page buffer can be identified using the column address.

If the program verification is performed through the above process, even if wrong data is latched in the page buffer connected to the bit line including the failed memory cell, the program verification may be normally performed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a block diagram illustrating the structure of a flash memory device.

FIG. 1B is a partial circuit diagram of the page buffer of FIG. 1A.

2 is a flowchart illustrating a method of operating a flash memory device according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

100 flash memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: input and output control unit 150: X decoder

160: control unit

Claims (12)

In a method of operating a nonvolatile memory device, Performing a program and performing program verification; Loading data of page buffers if the program is not passed as a result of the verification; Among the loaded data, executing a program according to data of a first page buffer connected to a failed bit line, or determining a state of data of a second page buffer except the first page buffer; And Determining a data state of the second page buffer, and executing a program or terminating the program Method of operating a nonvolatile memory device comprising a. The method of claim 1, The second page buffer, And a third page buffer connected to the redundant bit line repaired for the failed bit line, and a fourth page buffer connected to a bit line that normally operates. The method of claim 1, Before running the above program, Setting the first page buffer to a first data state using a column address; And Dividing the second page buffer by using the column address, and setting the second page buffer to a first or second data state according to input data Method of operating a nonvolatile memory device comprising a. The method of claim 1, The data state of the first page buffer is If in the first data state, running a program; And Checking a data state of the second page buffer in a second data state Operating method of a nonvolatile memory device comprising a. The method of claim 4, wherein And when the state of the first page buffer is the first data state, the first page buffer is set to a program pass. The method of claim 4, wherein The data state of the second page buffer is In the case of the first data state, the program is determined to be completed and the program is terminated. And, in a second data state, executing a program. In a method of operating a nonvolatile memory device, Performing a program and performing program verification; Loading data of page buffers if the program is not passed as a result of the verification; Among the loaded data, the program is executed according to the data of the first page buffer connected to the failed bit line, or the data state of the second page buffer which is a redundancy page buffer replaced by the failed bit line is determined. step; Performing a program according to a data state of the second page buffer or determining a state of data of a third page buffer connected to a bit line including a normally operating memory cell; And Determining a data state of the third page buffer, and executing a program or terminating the program Method of operating a nonvolatile memory device comprising a. The method of claim 7, wherein Before running the above program, Setting the first page buffer to a first data state using a column address; And Distinguishing the second page buffer from the third page buffer by using the column address, and setting the second and third page buffers to a first or second data state according to input data. Method of operating a nonvolatile memory device comprising a. The method of claim 7, wherein The data state of the first page buffer is The program operation is performed in the first data state and the data state of the second page buffer is checked in the second data state. The method of claim 9, And when the state of the first page buffer is the first data state, the first page buffer is set to a program pass. The method of claim 7, wherein The data state of the second page buffer is In the case of the first data state, the data state of the third page buffer is determined, And, in the second data state, executing the program. The method of claim 11, The data state of the third page buffer is In the case of the first data state, the program is determined to be completed and the program is terminated. And, in a second data state, executing a program.

Images