KR20090067996A - Non-volatile memory device having charge trapping layer and method for programming the same - Google Patents

Abstract

A non-volatile memory device and a programming method thereof are provided to increase data storage capacity while not increasing physical size of a memory cell. A plurality of cell strings are arranged in a non-volatile memory device. Each of the cell strings has a drain selection transistor(DSL) and a source selection transistor, and a plurality of memory cells connected in series between the drain selection transistor and the source selection transistor. A memory cell transistor has a tunneling layer(310), an electric charge trapping layer(320), a shielding layer(330) and a control gate electrode(340) sequentially formed on a semiconductor substrate. At least one of the drain selection transistor and the source selection transistor has the same cell structure as the memory cell so as to program data.

Description

Non-volatile memory device having charge trapping layer and method for programming the same

The present invention relates to a nonvolatile memory device and a driving method thereof, and more particularly to a nonvolatile memory device having a charge trap layer and a program method thereof.

NAND type non-volatile memory (NAND type non-volatile memory) is a nonvolatile memory device that can be electrically programmed and erased, MP3 player, digital camera, camcorder, notebook computer, PDA, It is widely used in portable electronics such as cellular phones, computer bios, printers, and USB drives.

Most NAND type nonvolatile memory devices have a floating gate structure in which a polysilicon film is capped with an inter-poly oxide (IPO). Floating gate type nonvolatile memory devices are excellent in extensibility, and thus, the development of multi-level chips has recently been performed. However, recently, as the integration of nonvolatile memory devices using floating gates is rapidly integrated, interference or coupling problems, in which threshold voltages are rapidly changed according to charge states of adjacent cells, have become serious. . Accordingly, attempts have been made to a new cell structure to overcome such interference between adjacent cells. Recently, interest in nonvolatile memory devices having a charge trap layer having less interference between cells even though the degree of integration of memory devices is increased has increased. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), a nonvolatile memory device having a charge trapping layer, has a silicon substrate, a tunneling layer, and a charge trapping layer having a channel region therein. A blocking layer and a control gate electrode are sequentially stacked.

In a SONOS device having such a structure, when the control gate electrode is positively charged and an appropriate bias is applied to the source / drain, hot electrons are transferred from the channel region of the semiconductor substrate to the trap site in the charge trap layer. Trapped. This is the operation of writing to or programming a memory cell. On the other hand, when the control gate electrode is negatively charged and an appropriate bias is applied to the source / drain, holes are trapped from the channel region of the semiconductor substrate to the trap site in the charge trap layer. The holes trapped in the charge trap layer recombine with the extra electrons already in the trap site, which is the operation of erasing the programmed memory cell.

A NAND type nonvolatile memory including a charge trap element generally includes a plurality of memory cells connected in series between a source line and a bit line, a source select transistor on the source line side, and a drain select transistor on the bit line side. Consists of a cell string. In such a charge trap device, the selection transistor performs an on / off operation for selecting a cell string required when programming data into a memory cell or verifying a program or erase state of the memory cell. It plays a role. That is, it is common to use on / off characteristics of general transistors, such as to perform an operation of transferring a bias for programming or verifying a cell, or to operate a current to flow or a switching operation to block a current.

In response to the high integration of semiconductor memory devices, there is a demand for a memory device capable of performing a highly efficient program operation with a higher storage capacity even in a nonvolatile memory device. Thus, if the selection transistor can be utilized for data storage, the storage capacity can be increased without increasing the physical size of the memory cell.

The present invention provides a nonvolatile memory device having a charge trap layer capable of increasing data storage capacity without increasing the size of a memory cell, and a program method thereof.

A nonvolatile memory device having a charge trap layer according to the present invention is a nonvolatile memory device including a drain and a source select transistor, and a plurality of cell strings including a plurality of memory cells connected in series between the drain select transistor and the source select transistor. The at least one of the drain select transistor and the source select transistor may have the same cell structure as that of the memory cell so that data can be programmed.

The memory cell may include a channel region formed on a substrate, and a tunneling layer, a charge trap layer, a shielding layer, and a control gate electrode sequentially stacked on the substrate.

A method of programming a nonvolatile memory device having a charge trap layer according to the present invention includes a nonvolatile memory device in which a plurality of memory strings and a plurality of cell strings including drain and source select transistors having the same structure as the memory cell are arranged. A method of programming, the method comprising: boosting a channel of a cell string to which a selection transistor to be programmed is connected to a predetermined level, and applying a turn-on voltage to a gate of the selection transistor by hot electron injection. And causing the selection transistor to be programmed.

The selection transistor may include a channel region formed on a substrate, and a tunneling layer, a charge trap layer, a shielding layer, and a control gate electrode sequentially stacked on the substrate.

The boosting of the channel of the cell string to which the select transistor to be programmed is performed may include turning on the drain select transistor, turning off the source select transistor, and a bit line connected to the select transistor to be programmed. A voltage of Vcc) or more may be applied, and a ground voltage may be applied to another bit line.

The turn-on voltage applied to the gate of the selection transistor may be 1.0 to 4.0V.

In the step of allowing the selection transistor to be programmed, either the drain selection transistor or the source selection transistor may be programmed, or the drain selection transistor and the source selection transistor may be programmed.

According to the present invention, a method of using a select transistor having the same structure as a memory cell transistor and using a select transistor that normally performs only an on / off operation for selecting a cell string as a memory cell capable of storing data is provided. By presenting, the data storage capacity of the memory element can be greatly increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as limited by the embodiments described below.

The present invention provides a method of using a select transistor having the same structure as a memory cell transistor and using the select transistor, which normally performs only on / off operations for selecting a cell string, as a memory cell capable of storing data. In addition, the data storage capacity of the memory device can be greatly increased.

1 illustrates a cell string array of a NAND nonvolatile memory device.

The memory cell array, which is a data storage region of the NAND type nonvolatile memory device, includes a plurality of cell strings 110 and 120 connected to corresponding bit lines BLe and BLo, respectively. Although only two cell strings are shown in the drawing, a plurality of cell strings may be arranged in the memory cell array. One cell string 110/120 includes a drain select transistor 111/121 connected to a bit line BLe / BLo, a source select transistor 112/122 connected to a common source line CSL, and a drain. A plurality of memory cell transistors 113, 114/123, 124 are disposed in series between the select transistor 111/121 and the source select transistor 112/122. The even bit line BLe and the odd bit line BLO are connected to one page buffer 200.

To program data in the memory cell 113, first, the drain select transistor 111 is turned on, the source select transistor 112 is turned off, and the ground is common to the common source line CSL. Apply voltage GND or power supply voltage Vcc. In this state, when the power supply voltage is applied to the bit line BLe to which the memory cell 113 is connected, the channel of the memory cell 113 is supplied with the charge through the drain select transistor 111 to generate the power supply voltage Vcc. It is precharged to the value Vcc-Vt minus the threshold voltage Vt of the drain select transistor. When a program voltage Vpgm of about 18V is applied to the word line of the memory cell to be programmed, the memory cell is programmed by tunneling of charge from the channel. At this time, an appropriate bias (typically Vcc) is applied to a bit line to which an unselected memory cell is connected, thereby boosting a channel by boosting a channel to maintain a constant potential so as not to be selected in a word line to which a program voltage is applied. This should not be programmed.

2 is a cross-sectional view of a nonvolatile memory device having a charge trap layer according to the present invention.

Referring to FIG. 2, a plurality of memory cell transistors are arranged on the semiconductor substrate 300, and a source select transistor SSL and a drain select transistor DSL are disposed on both sides of the memory cell. Memory cell transistors and select transistors share a source / drain region. A source contact 350 is disposed on the left side of the source select transistor to apply an appropriate bias to the source line, and a drain contact 360 is disposed on the right side of the drain select transistor DSL to apply an appropriate bias to the drain select line. do.

The memory cell transistors may include an impurity region 302 disposed on a semiconductor substrate 300 such as a silicon substrate and spaced apart from each other by a predetermined interval, and a tunneling layer 310 and a charge trap layer sequentially stacked on the semiconductor substrate 300. And a control layer 320, a shielding layer 330, and a control gate electrode 340.

The semiconductor substrate 300 may be a conventional silicon (Si) substrate, or in some cases, may be another substrate such as a silicon on insulator (SOI) substrate.

The tunneling layer 310 allows charge carriers such as electrons or holes to be injected into the charge trap layer 320 under a certain bias, and is typically made of an insulating film such as silicon oxide (SiO ₂ ). Since the tunneling layer 310 may be deteriorated by repeated tunneling of charge carriers, the stability of the device may be degraded, and thus, the tunneling layer 310 may have a thickness that can be prevented as much as possible.

The charge trap layer 320 is a layer for trapping electrons or holes injected through the tunneling layer 310 from the channel region of the semiconductor substrate. Since the energy level is uniform and the number of trap sites is high, the charge trap is well formed. Program and erase speeds can be increased. The charge trap layer 320 is usually made of silicon nitride, a stoichiometric silicon nitride (Si ₃ N ₄ ) film, silicon-rich (Si-rich) silicon nitride (Si _x N _y) ), Or a structure in which a stokiometric silicon nitride (Si ₃ N ₄ ) film and a silicon-rich silicon nitride (Si _x N _y ) film are stacked, or a polysilicon film.

The shielding layer 330 is for preventing electrons trapped in the charge trap layer 320 from escaping to the control gate electrode 340. An aluminum oxide (Al ₂ O ₃ ) film, hafnium oxide (HfO 2), or hafnium aluminum It may be a structure including a high-K material such as an oxide (HfAlO) film.

The control gate electrode 340 applies a bias of a predetermined size so that electrons or holes are trapped from the channel region of the substrate 300 to the trap site in the charge trap layer 320. The control gate electrode 340 is made of, for example, a polysilicon film doped with a high concentration of n-type impurities, or a metal having a high work function, such as a tungsten (W) film or a tungsten silicide (WSi) film. , A tungsten nitride (WN) film, a tantalum nitride (TaN) film, a titanium nitride (TiN), a ruthenium (Ru) film, or a stacked film thereof.

A low resistance layer (not shown) may be disposed on the control gate electrode 340 to reduce the resistance of the gate line. The low resistance layer (not shown) is for lowering the resistance of the control gate electrode 340 and may be formed of a polysilicon film / tungsten silicide film structure or a tungsten nitride (WN) film / tungsten (W) film structure. Can be.

In the nonvolatile memory device of the present invention, in particular, the drain select transistor DSL and the source select transistor SSL have the same SONOS structure as that of the memory cell transistor, rather than the general MOS type structure, as shown. That is, in the same manner as the memory cell transistor, the tunneling layers 311 and 312, the charge trap layers 321 and 322, the shielding layers 331 and 332, and the control gate electrodes 341 and 342 are sequentially stacked from the substrate 300. Has a structure. As such, the reason for configuring the select transistors in the same structure as the memory cell transistor is to use the select transistors as memory cells in the same manner as the cell transistors. That is, the select transistors can program data in the same way as the memory cell transistors, and can erase data programmed in the select transistors.

Although the drawing shows an example in which both the source select transistor and the drain select transistor are formed in the same structure as the memory cell, only one of the source select transistor and the drain select transistor may have the same structure as the memory cell.

Next, an operation of programming the selection transistors or erasing the programmed data will be described in detail.

3 is a cross-sectional view illustrating a program mechanism of a nonvolatile memory device having a charge trap layer according to the present invention. The same reference numerals are used for the same parts as in FIG. 2.

The programming method of the present invention is to program data by utilizing select transistors of an unselected string as memory cells when programming a memory cell of a selected string. In order to program the memory cell, the drain select transistor DSL is turned on, the source select transistor SSL is turned off, and the ground voltage or the power supply voltage Vcc is connected to the common source line CSL. ), A predetermined program voltage Vpgm is applied to the word line of the selected memory cell and a ground voltage GND is applied to the bit line of the selected memory cell. The charges from the channel are then trapped in the charge trap layer to program the memory cell. In this case, a bias of the normal power supply voltage Vcc is applied to the bit line to which the unselected cell string is connected, not the ground voltage GND, to prevent the memory cell connected to the same word line as the selected memory cell from being programmed. . When an appropriate bias is applied to the bit line, the channel of the cell string is boosted through the drain contact 360, and the program is not programmed in the string in which the channel boost is maintained. The boosting level can be adjusted according to the condition of the pass voltage applied to the word line. As such, the cell string to which the ground voltage GND is applied to the bit line is programmable since the channel is maintained in the ground state, and channel boosting occurs in the unselected string to which the power voltage Vcc is applied to the bit line. The program is prevented.

An appropriate voltage, such as about 1.4 to 4.0 V, is applied to the control gate 341 of the drain select transistor so that the drain select transistor DSL is turned on while the channel of the unselected string is boosted. When the electrons flow from the bit line to the channel 302 of the cell string, the electrons pass through the tunneling layer 311 of the drain select transistor DSL by hot carrier injection to the charge trap layer 321. Trapped. Accordingly, the drain select transistor is programmed as the threshold voltage of the drain select transistor DSL increases. Reference numeral "331" denotes a shielding layer of the drain select transistor.

As such, the voltage applied to the bit line is adjusted to maintain the channel of the cell string in the ground or channel boosting state, thereby preventing the drain select transistor from being programmed or programmed. That is, when the drain select transistor is not programmed, the bit line should be maintained at ground, and when the drain select transistor is programmed, an appropriate bias may be applied to the bit line to selectively program the drain select transistor so that channel boosting occurs. Can be. In addition, when programming a memory cell, the string of the cell to be programmed maintains the channel to ground, and the channel to be programmed is programmed by boosting the channel to program the drain select transistor in the boosted string, thereby programming the memory cell. The drain select transistor can be programmed at the same time. It is also possible to program the drain select transistors individually by keeping the string under conditions that boost the channel.

On the other hand, the source select transistor can be programmed in a similar manner.

First, when a constant voltage such as a pass voltage Vpass is applied to a word line, when the drain select transistor DSL is turned on and a constant voltage is applied to the bit line, the channel of the cell string maintains a constant potential. When the source line maintains a bias lower than the potential of the channel and then applies an appropriate voltage to the control gate of the source select transistor SSL, electrons move in the direction of the bit line from the common source line. This causes hot carrier injection in the charge trap layer of the source select transistor to program the source select transistor. In addition, when a bias higher than the potential of the string channel is applied to the common source line, electrons move from the bit line to the common source line direction. Similarly, the bit line and the hot carrier injection (HCI) are applied to the string to which the source selection transistor is programmed. Can be programmed.

In addition, in a string that is not programmed, the source select transistor may not be programmed by adjusting an appropriate bit line bias to form a string channel potential that does not differ from a bias applied to the common source line CSL. In addition, the drain select transistor and the source select transistor may be programmed simultaneously, or in some cases, only one of the drain select transistor and the source select transistor may be programmed.

4 is a cross-sectional view illustrating an erase mechanism of a nonvolatile memory device having a charge trap layer according to the present invention. The same reference numerals as in FIG. 3 denote the same parts.

In the erase operation of a NAND type nonvolatile memory device, a erase voltage having a predetermined magnitude is applied to a substrate or a well, and a word line maintains a ground voltage to perform block erase. In this case, when the drain select line or the source select line maintains the ground voltage GND like the word line, the erase operation may be performed on the drain select transistor DLS and the source select transistor SSL like the memory cell. . In addition, the erase speed may be adjusted by appropriately adjusting the voltage applied to the drain select line or the source select line.

Specifically, an appropriate erase voltage, for example, a voltage of 0 V is applied to all of the memory cell transistors, the source select transistor SSL, and the drain select transistor DSL in one block, and a voltage of about 20 V is applied to the semiconductor substrate 300. Is applied. By applying such a voltage, electric charges injected into the charge trap layers 320, 321, and 322 escape to the semiconductor substrate 300, thereby erasing data.

Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.

1 illustrates a cell string array of a NAND nonvolatile memory device.

2 is a cross-sectional view of a nonvolatile memory device having a charge trap layer according to the present invention.

3 is a cross-sectional view illustrating a program mechanism of a nonvolatile memory device having a charge trap layer according to the present invention.

4 is a cross-sectional view illustrating the erase mechanism of the nonvolatile memory device having the charge trap layer according to the present invention.

Claims (7)

A nonvolatile memory device comprising a plurality of drain and source select transistors, and a plurality of cell strings including a plurality of memory cells connected in series between the drain select transistor and the source select transistor. At least one of the drain select transistor and the source select transistor has a same cell structure as that of the memory cell so that data can be programmed. The method of claim 1, The memory cell, A channel region formed on the substrate, and A nonvolatile memory device having a charge trap layer comprising a tunneling layer, a charge trap layer, a shielding layer, and a control gate electrode sequentially stacked on the substrate. A method of programming a nonvolatile memory device in which a plurality of memory strings and at least one of the plurality of cell strings including drain and source select transistors having the same structure as that of the memory cells are arranged, Boosting a channel of the cell string to which the selection transistor to be programmed is connected to a predetermined level; And And applying a turn-on voltage to a gate of the selection transistor to cause the selection transistor to be programmed by hot electron injection. The method of claim 3, Boosting a channel of a cell string to which the selection transistor to be programmed is connected, Turning on the drain select transistor, turning off the source select transistor, and And applying a voltage equal to or greater than a power supply voltage (Vcc) to a bit line connected to the selection transistor to be programmed, and applying a ground voltage to another bit line. The method of claim 3, And a turn-on voltage applied to the gate of the selection transistor is 1.0 to 4.0 volts. The method of claim 3, In the step of causing the selection transistor to be programmed, A program method for a nonvolatile memory device having a charge trap layer, wherein the drain select transistor or the source select transistor is programmed. The method of claim 3, In the step of causing the selection transistor to be programmed, A method of programming a nonvolatile memory device having a charge trap layer, wherein the drain select transistor and the source select transistor are programmed.

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