KR20090067801A - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device of the present invention is formed in a direction crossing the first global I / O lines connected to the bank and the first global I / O lines, the second global I / O lines connected to the data pad, and the first and the first and the second global input / output lines. And a repeater circuit configured to intersect two global input / output lines and perform bidirectional data transmission between the first and second global input / output lines.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a repeater for improving loading of a global input / output line, which is a shared line between banks.

In general, a semiconductor memory device writes data to a cell which is a data storage location and reads the data. Data input / output lines for reading and writing data of cells determined by word lines and column selection signals for such operations, including segment input / output (SIO) lines, local input / output (LIO) lines, and global Use Global Input / Output (GIO) lines.

For example, referring to the role of each input / output line along a read path, after the data of the cell bit line is amplified by the column select signal Yi, the data is loaded on the SIO line. Thereafter, the data loaded on the SIO line is loaded on the LIO line sharing the SIO lines of the cell segment blocks divided for each bit line sense amplifier block of one bank, and thus an input / output sense amplifier (IOSA) provided for each bank (Bank0 to Bank7). Is applied to. The data sensed by the input / output sense amplifier is loaded on the GIO line.

Referring to FIG. 1, a general GIO line is a bank sharing line, and is a signal line that eight banks Bank0 to Bank7 can drive. The data of the GIO line is transferred by the output driver to the desired data pads DQ1, DQ2,... A read operation is performed by outputting through the DQN.

In the case of outputting data to a GIO line having a long line length in a semiconductor memory device having such a structure, for example, data of BANK4 to BANK7 is transferred to data pads DQ1, DQ2,... It has a large delay time to output through DQN.

In this case, when a signal is transmitted through a heavy GIO line by having a long line length, signals at the front end of the driver driving the GIO line and the data pad side have a significant delay time difference. As a result, the operation time of the memory device is slowed down as the transmission time of the signal is delayed.

The present invention provides a semiconductor memory device including a repeater circuit provided on a global input / output line that reduces a signal delay and implements high speed operation by distributing a load by distributing a load of a global input / output line.

In an embodiment, a semiconductor memory device may include first global input / output lines connected to a bank; Second global input / output lines formed in a direction crossing the first global input / output lines and connected to a data pad; And a repeater circuit configured at a position where the first and second global input / output lines cross each other and performing bidirectional data transfer between the first and second global input / output lines.

The repeater circuit may include a controller configured to generate a global input / output line enable signal as a read and write control signal in synchronization with a read and write operation command signal; And a repeater unit configured to transmit the data in one of two directions in response to the read and write control signals.

The repeater unit may include a first repeater unit performing data transmission in a first direction for a write operation and a second repeater unit performing data transmission in a second direction opposite to the first direction for a read operation. desirable.

In addition, the first repeater and the second repeater is composed of an inverting buffer, it is preferable that the operation is controlled in three phases.

The repeater unit may be configured in a one-to-one manner for each global input / output line.

The read / write control signal may be enabled earlier than read data input to the repeater unit.

In addition, the first global input / output lines may be shared in an adjacent pair of banks.

Also, the repeater circuit is preferably shared for four banks.

The repeater circuit may be configured at both ends of the second global input / output line.

According to the present invention, data transmission is distributed by a repeater on a global input / output line, which is a shared line between banks, thereby reducing signal delay and enabling high-speed operation.

The present invention proposes a method for solving the global I / O line loading problem by distributing the loading of the global I / O line driver by adding a repeater of the global I / O line between the memory array and the peripheral circuit.

Referring to FIG. 2, the semiconductor memory device according to an embodiment of the present invention, the global input / output line GIO is shared between the banks BANK0 to BANK7 to transfer data between the data input / output pads DQ1 to DQn and the banks BANK0 to BANK7. Play a role.

According to the arrangement of the banks BANK0 to BANK7, the memory array area adjacent to the bank and the peripheral circuit area passing through the banks are divided, and the global input / output line GIO of the memory array area is defined as the first line GIO1. The line connected to the peripheral circuit area and provided with the data input / output pads DQ1 to DQn will be defined as a second line GIO2.

In addition, the global input / output line GIO may include n first lines GIO1 and n second lines GIO2 corresponding to n bits of the semiconductor memory device.

The repeater circuit 300 is connected between the first line GIO 1 and the second line GIO 2, and according to the read and write operation command signal WTS, the first line GIO 1 or the second line GIO 2. The data of each buffer is transferred to the data pad or the specific bank by buffering the data to the corresponding line.

Specifically, referring to FIG. 3, the repeater circuit 300 according to the present invention may perform global input / output line enable signals YGIOE 0 and YGIOE generated in the banks BANK0 to BANK7 of the memory array in synchronization with read and write operation command signals WTS. It is selectively driven by the control unit 320 that receives the 1 and generates the read / write control signal GIO_RD / WT and the read / write control signal GIO_RD / WT, and is the first line GIO 1 and the second line GIO 2. And a repeater unit 340 including a first repeater unit 344 and a second repeater unit 346 for buffering and transferring data between the two.

The control unit 320 receives the global input / output line enable signals YGIOE0 and YGIOE1 transmitted from the bank of the memory cell array in synchronization with the read / write operation command signal WTS to generate the read / write control signal GIO_RD / WT to generate the repeater unit ( 340).

The controller 320 outputs the inverter IV1 receiving the read / write operation command signal WTS, the NOR1 receiving the global input / output line enable signals YGIOE0 and YGIOE1 from a specific bank, and the NOR1 NOR1. The NAND gate ND1 may combine the inverter IV2 receiving the received signal and the output signal transmitted from the inverters IV1 and IV2.

When the read control signal GIO_RD is applied from the controller 320, the repeater 340 drives the first repeater 344 to buffer the data of the first line GIO1 connected to the bank to the second line GIO2. Transfer to the connected data input / output pad. At this time, the second repeater unit 346 is not driven.

Similarly, when the write command signal GIO_WT is applied, the repeater 340 drives the second repeater 346 to buffer the data of the second line GIO2 connected to the data input / output pad and is connected to the first line GIO1. Pass it to the bank. At this time, the first repeater unit 344 is not driven. That is, the repeater 340 selectively drives only one of the first repeater 344 and the second repeater 346 according to the read / write command signal.

The first repeater 344 buffers the signal GIOBK_RD of the first node GIO1 in synchronization with the read control signal GIO_RD output from the controller 320 and the signal GIO_RDB inverted by the inverter IV3. It may be configured as a three-phase inverter (IV4) for outputting the signal GIOR to the two nodes (GIO2).

The second repeater unit 346 buffers the signal GIOW of the second node GIO2 in synchronization with the write control signal GIO_WT output from the control unit 320 and the signal GIO_WTB inverted by the inverter IV3 to output the signal. The three-phase inverter IV5 outputs the GIOBK_WT to the first node GIO1.

Meanwhile, the first repeater 344 and the second repeater 346 of the repeater 340 may be configured in one-to-one correspondence with banks and data input / output lines, and may be provided in plural numbers corresponding to the number of data input / output lines. .

Next, the driving of the repeater circuit 300 of the present invention during the read operation will be described in detail.

 When the DRAM is in the read operation, the read command signal is applied to the inverter IV1 at a logical high 'H' in the control unit 320 of the repeater circuit 300, and the global input / output line enable signals YGIOE0 and YGIOE1 are both present. It is applied to the NOR gate NOR1 with a logical high 'H', which is output through the inverter IV2 to a logical high 'H', and the output signals 'H' and 'H' of the inverters IV1 and IV2 are The NAND is combined through the NAND gate ND1 to output a logical low 'L' signal.

Subsequently, the logical low 'L' signal output from the controller 320 and the logical high 'H' signal inverted by the inverter IV3 turn on the first repeater unit 344 and thereby turn on the first line GIO. Data of 1) is buffered and transferred to the second line GIO 2. In this case, the second repeater 346 does not operate because the three-phase inverter IV5 is turned off by the logical low 'L' signal and the logical high 'H' signal inverted by the inverter IV3.

Therefore, the data of the bank connected to the first line GIO1 is transferred to the data input / output line connected to the second line GIO2, thereby performing a read operation of the global input / output line GIO.

Next, the driving of the repeater circuit 300 of the present invention during the write operation will be described in detail.

When the DRAM is in the write operation, the write command signal is applied to the inverter IV1 at a logical high 'H' in the control unit 320 of the repeater circuit 300, and the global input / output line enable signals YGIOE0 and YGIOE1 are both present. When applied to the NOR gate NOR1 at a logical high 'H', it is output at a logical high 'H' through the inverter IV2, and the output signals 'L' and 'H' of the inverters IV1 and IV2 are The NAND is combined through the NAND gate ND1 to output a logical high 'H' signal.

Subsequently, the logical high 'H' signal output from the controller 320 and the logical low 'L' signal inverted by the inverter IV3 turn on the second repeater unit 346 and thereby turn on the second line GIO2. ) Is buffered and transferred to the first line GIO 1. At this time, the first repeater 344 does not operate because the three-phase inverter IV4 is turned off by the logical high 'H' signal and the logical low 'L' signal inverted by the inverter IV3.

Therefore, data of the data input / output pad connected to the second line GIO2 is transferred to the bank connected to the first line GIO1, thereby performing a write operation of the global input / output line GIO.

4 is a signal diagram showing the operation of the repeater circuit 300 of the present invention, in which the GIO_BK signal is transferred to the GIOR by the YGIOE0 / 1 signal synchronized with the internal signal controlling the memory cell information of the bank, the GIOBK_RD signal. Since the GIO_BK signal is enabled before the GIO_BK signal, it can be seen that the speed delay factor related to the overall signal transmission of the global input / output line is insufficient.

As described above, the repeater circuit 300 of the present invention may transfer data between a specific bank and a specific data input / output pad that is far from the specific bank during a read / write operation of a DRAM. By being provided in the global input / output line GIO connected between the data input / output pads, the load of the long global input / output line can be reduced by buffering the data to be transmitted.

In addition, the repeater circuit 300 of the present invention enables high-speed operation by reducing the delay of signal transmission on a long global input / output line.

1 is a simplified diagram illustrating a data path between a typical bank and a global input / output line.

2 is a semiconductor memory device having a repeater according to the present invention.

3 is a detailed circuit diagram of a repeater according to the present invention.

4 is a signal flow diagram of a repeater according to the present invention;

Claims (9)

First global input / output lines connected to the bank; Second global input / output lines formed in a direction crossing the first global input / output lines and connected to a data pad; And A repeater circuit configured at a position where the first and second global input / output lines cross each other and performing bidirectional data transmission between the first and second global input / output lines; A semiconductor memory device comprising: a. The method of claim 1, The repeater circuit A controller configured to generate a global input / output line enable signal as a read and write control signal in synchronization with read and write operation command signals; And And a repeater unit configured to transfer the data in one of two directions in response to the read and write control signals. The method of claim 2, The repeater unit And a second repeater unit for performing data transfer in a first direction for a write operation and a second repeater unit for performing data transfer in a second direction opposite to the first direction for a read operation. The method of claim 3, wherein The first repeater portion and the second repeater portion A semiconductor memory device comprising an inverting buffer and controlled in three phases. The method of claim 2, The repeater unit A semiconductor memory device configured in a one-to-one manner for each global input / output line. The method of claim 2, And the read / write control signal is enabled earlier than read data input to the repeater unit. The method of claim 1, The first global input and output lines A semiconductor memory device shared by banks of adjacent pairs. The method of claim 1, The repeater circuit A semiconductor memory device shared for four banks. The method of claim 8, And a repeater circuit is formed at both ends of the second global input / output line.

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