KR20090067800A - Semiconductor memory device and circuit for controlling bank activity of the same - Google Patents

Semiconductor memory device and circuit for controlling bank activity of the same Download PDF

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Publication number
KR20090067800A
KR20090067800A KR1020070135581A KR20070135581A KR20090067800A KR 20090067800 A KR20090067800 A KR 20090067800A KR 1020070135581 A KR1020070135581 A KR 1020070135581A KR 20070135581 A KR20070135581 A KR 20070135581A KR 20090067800 A KR20090067800 A KR 20090067800A
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South Korea
Prior art keywords
bank
signal
command signal
precharge
command
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KR1020070135581A
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Korean (ko)
Inventor
노영규
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주식회사 하이닉스반도체
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Priority to KR1020070135581A priority Critical patent/KR20090067800A/en
Publication of KR20090067800A publication Critical patent/KR20090067800A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

The present invention relates to a semiconductor memory device for controlling the activation of a bank and a bank activation control circuit thereof, comprising: a command decoder for decoding an external command signal and outputting the internal command signal; A plurality of bank selectors for decoding the bank address signals and outputting the bank address signals corresponding to the banks, respectively; And bank activation path portions each controlled by the bank selection signals, and transferring the internal command signal to at least one bank activation path portion selected by the bank selection signals to output bank activation signals. Bank activation control circuit;

Description

Semiconductor memory device and its bank activation control circuit {SEMICONDUCTOR MEMORY DEVICE AND CIRCUIT FOR CONTROLLING BANK ACTIVITY OF THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for controlling the activation of a bank and a bank activation control circuit thereof.

In general, a semiconductor memory device such as a DRAM includes a plurality of banks, and read or write is controlled for each bank. That is, a bank is selected by a combination of an externally applied command and a bank address, and a word line designated by a row address is activated in the selected bank to read or write. After the read or write operation is completed, the activated word line is precharged.

As described above, a series of processes in which a bank is activated and precharged is controlled for each bank. For this purpose, a conventional semiconductor memory device includes a circuit for controlling bank activation for each bank.

That is, as shown in FIG. 1, the conventional semiconductor memory device has a structure including a command decoder 10, a bank selector 12, and a bank activation path unit 14 for each bank.

In operation, when the command signals RASB, CASB, WEB, and CSB are input to the command decoder 10 from the outside, the external command signals RASB, CASB, WEB, and CSB are decoded through the command decoder 10 and the active command signal is decoded. Occurs with ACT or precharge command signal PCG. In addition, the bank address signals BA <0: n> are externally input to the bank selector 12, and the bank address signals BA <0: n> are decoded through the bank selector 12 to generate the bank select signals BS. do.

The active command signal ACT and the bank selection signal BS are input to the bank activation path unit 14 to generate a bank activation signal BA_ACT for controlling whether the bank is activated, and the precharge command signal PCG and the active command signal ACT are low active time. (tRAS) The bank activation signal BA_ACT is disabled by the reset signal RST that occurs due to a delay.

Referring to the operation in which the bank activation signal BA_ACT is generated in the bank activation path unit 14 in detail, when the active command signal ACT and the bank selection signal BS are input at a high level, the PMOS transistor P1 is turned off and the NMOS transistors. (N1, N2) is turned on to pull down node ND1 to a low level.

In response to the pull-down, the low-level signal loaded on the node ND1 is latched through the latch LAT1 and the PMOS transistor P2 is turned on and the node ND2 is turned on by the PMOS transistor P2. ) Is pulled up to a high level.

According to the pull-up, the high level signal loaded on the node ND2 is output as the bank activation signal BA_ACT in the enabled state through the inverter INV1, the latch LAT2, and the inverter INV2.

The bank selected by the bank activation signal BA_ACT in the enabled state is activated to perform a read or write operation, and the NMOS transistor N3 is applied by the precharge command signal PCG or the reset signal RST at the end of the read or write operation. Alternatively, the NMOS transistor N4 is turned on.

As the NMOS transistor N3 or the NMOS transistor N4 is turned on, the node ND2 is pulled down to a low level, whereby the bank activation signal BA_ACT is disabled after the previous state latch of the latch LAT2 is finished.

As described above, the conventional semiconductor memory device includes a circuit having the configuration of FIG. 1 corresponding to the number of banks, and each of the circuits includes an active command signal ACT, a bank selection signal BS, a precharge command signal PCG, and a reset signal RST. Combine to generate bank activation signal BA_ACT.

That is, the command decoder 10, the bank selector 12, and the bank activation path unit 14 are conventionally arranged for each bank, and the command decoder 10, the bank selector 12, and the bank activation path unit ( It is determined whether to activate the bank corresponding to the bank activation signal BA_ACT according to the state of the bank activation signal BA_ACT output from the circuit including the circuit 14).

However, the conventional semiconductor memory device has a problem in that the area occupied by the circuit increases as the circuit is provided corresponding to the number of banks, which may cause the memory chip size to increase.

In addition, in the related art, as circuits for controlling bank activation are disposed corresponding to banks, as the memory capacity increases or the number of banks increases, the number of circuits increases, so that the layout area increases, and a Net Die There is a problem that can be reduced.

The present invention provides a semiconductor memory device capable of improving the net die by reducing the area of a circuit capable of controlling activation for each bank.

The present invention provides a bank activation control circuit in which the layout area is reduced while controlling the activation state for each bank.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a command decoder configured to decode an external command signal and output the internal command signal; A plurality of bank selectors for decoding the bank address signals and outputting the bank address signals corresponding to the banks, respectively; And bank activation path portions each controlled by the bank selection signals, and transferring the internal command signal to at least one bank activation path portion selected by the bank selection signals to output bank activation signals. Bank activation control circuit;

In the above configuration, it is preferable that each bank activation path unit selectively receives the internal command signal according to the state of each bank selection signal and outputs the bank activation signal.

The bank activation path unit may output the bank activation signal having an enable period from an active entry time to a precharge entry time as the internal command signal.

The command decoder decodes the external command signal corresponding to the active signal and outputs the active command signal as the internal command signal, decodes the external command signal corresponding to the precharge, and then uses the precharge command signal as the internal command signal. It is preferable to output to.

In addition to the configuration of the command decoder, each bank activation path unit includes: a transfer unit for selectively transferring the active command signal according to the state of each bank selection signal; An output unit for latching a signal transmitted from the transfer unit and outputting the bank activation signal; And a precharge unit for disabling the bank activation signal as the precharge command signal.

Here, the transfer unit preferably includes a pass gate for selectively transferring the active command signal according to the state of the bank selection signal.

The precharge unit may precharge the output terminal of the transfer unit in response to the precharge command signal.

The bank activation control circuit may include: a delay unit configured to delay the active command signal corresponding to a low active time and output a reset signal; And a combination unit combining the reset signal and the precharge command signal to provide the precharge unit with a control signal enabled when any one of the reset signal and the precharge command signal is enabled. desirable.

In an embodiment, a bank activation control circuit of a semiconductor memory device may include: a plurality of transfer units configured to receive a command signal in common and to selectively transfer the command signal according to bank selection; A plurality of output units connected to output ends of the transfer units, respectively, for latching the command signals and outputting the command signals as bank activation signals when the command signals are transmitted from the transfer units; And a plurality of precharge units connected to each of the transfer units and the output units, respectively disabling a bank activation signal corresponding to the banks when precharging a predetermined bank.

In the above configuration, it is preferable that each transfer unit receives the command signal and a bank selection signal for determining the bank selection, and selectively transfers the command signal according to the state of the bank selection signal.

To this end, each of the transfer unit preferably includes a pass gate for selectively transferring the command signal according to the state of the bank selection signal.

Each of the precharge units may be enabled after a precharge command is externally input or after a low active time has passed from the time of the active command input, thereby disabling the bank activation signals.

The precharge unit may be connected between the transfer unit and the output unit to precharge the output terminal of the transfer unit when the bank is precharged.

The present invention has the configuration of activating a bank by transferring only the command signal output from the command decoder to an activation path of a selected bank using only one command decoder, thereby reducing net area and improving net die.

In addition, the present invention includes a bank activation control circuit including a plurality of bank activation path portions for receiving a command signal in common, wherein each bank activation path portion selectively receives and latches a command signal, and then the latch upon precharging. Since only the configuration for disabling the signal is required, the configuration of the bank activation control circuit can be simplified, and accordingly, the layout area of the bank activation control circuit can be reduced.

According to the present invention, an internal command signal output from one command decoder is commonly input, and a bank activation is performed by activating the selected bank by transferring the commonly input internal command signal only through a path corresponding to the selected bank according to a bank selection. A semiconductor memory device including a control circuit is disclosed.

Specifically, the semiconductor memory device according to the present invention, as shown in FIG. 2, includes a command decoder 20, a plurality of bank selectors 22, and a bank activation control circuit 26.

The command decoder 20 decodes the external command signals RASB, CASB, WEB, and CSB and outputs the internal command signal CMD. Here, the command decoder 20 generates an active command signal as the internal command signal CMD when the external command signals RASB, CASB, WEB, and CSB are commands for performing an active operation, and the external command signals RASB, CASB, WEB. When the CSB is a command to perform the precharge operation, the precharge command signal is generated as the internal command signal CMD.

The plurality of bank selectors 22 receive the bank address signals BA <0: n> in common, decode the bank address signals BA <0: n> (where 'n' is a natural number of 1 or more), respectively. The bank select signal BS <0: m> for selecting a bank is outputted in which 'm' is a natural number of 1 or more. At this time, each bank selector 22 is provided in a one-to-one correspondence to each bank (not shown). For example, when there are 'm' banks, 'm' bank selectors 22 are also disposed.

The bank activation control circuit 26 combines the internal command signal CMD and the bank selection signals BS <0: m> and outputs the bank activation signals BA_ACT <0: m>, and the bank selection signals BS <0: m>. When any one of, for example, BS <0> is enabled, the bank activation signal BA_ACT <0> corresponding to the bank selection signal BS <0> in the enabled state is enabled.

Specifically, the bank activation control circuit 26 may include a configuration as shown in FIG. 3.

Referring to FIG. 3, the bank activation control circuit 26 includes a plurality of bank activation path units 34, and a delay unit 30 and a combination unit for controlling precharge of each bank activation path unit 34. (32) may be further included.

Each bank activation path section 34 is provided in a one-to-one correspondence with each bank selector 22 and each bank, and receives the internal command signal CMD in common, and receives the bank select signals BS <0: m>, respectively.

In addition, at least one bank activation path unit 34 is selected by the bank selection signals BS <0: m> input to each bank activation path unit 34, and is internal to the selected bank activation path unit 34. The command signal CMD is transferred and output as the bank activation signal BA_ACT <0: m>.

The bank activation path parts 34 may all be configured in the same configuration, that is, the transfer part 35, the output part 36, and the precharge part 37, respectively, and typically, the bank selection signal BS < The configuration of the transfer section 35, the output section 36, and the precharge section 37 of the bank activation path section 34 controlled by 0> and selectively outputting the bank activation signal BA_ACT <0> will be described below. same.

The transfer unit 35 receives the active command signal ACT as the internal command signal CMD, and selectively transfers the active command signal ACT according to the state of the bank selection signal BS <0>.

The transfer unit 35 selectively transfers the active command signal ACT according to the inverter INV3 for inverting the bank selection signal BS <0> and the output of the bank selection signal BS <0> and the inverter INV3. It may be configured to include a pass gate (PG).

The output unit 36 latches the signal transmitted from the transfer unit 35 and outputs the bank activation signal BA_ACT <0>. The output unit 36 includes two inverters INV4 and INV5 latching the signal transferred from the transfer unit 35. The latch LAT3 and the inverter INV6 which inverts the output of the latch LAT3 and outputs the bank activation signal BA_ACT <0> may be configured.

The precharge unit 37 selectively disables the bank activation signal BA_ACT <0> according to the state of the control signal CTRL. In particular, the precharge unit 37 is connected between the transfer unit 35 and the output unit 36 to control the state of the control signal CTRL. In accordance with the present invention, the output terminal of the transmission unit 35 may be selectively pre-directed. Here, the control signal CTRL is a signal that is enabled upon precharge and may correspond to a precharge command signal PCG, which is an internal command signal CMD, or a combination of the precharge command signal PCG and the reset signal RST.

The precharge unit 37 may include an NMOS transistor N5 connected between the output terminal of the transfer unit 35 and the ground terminal VSS and receiving a control signal CTRL as a gate.

On the other hand, when the precharge unit 37 is configured to be enabled when a precharge command is externally input and is enabled upon precharge after the low active time tRAS, the bank activation path unit 34 is delayed. The unit 30 and the combination unit 32 may be further provided.

The delay unit 30 delays the active command signal ACT corresponding to the low active time tRAS and outputs the reset signal RST. The low active time tRAS is a minimum low active time defined in the semiconductor memory device. (tRAS_min) is preferred.

The combination unit 32 then combines the reset signal RST and the precharge command signal PCG, which is the internal command signal CMD, to output a control signal CTRL that is enabled when any one of the reset signal RST and the precharge command signal PCG is enabled. do. To this end, the combination unit 32 may be configured to include a NOR gate NR that logically operates the reset signal RST and the precharge signal PCG.

Referring to the operation of the semiconductor memory device according to the present invention having such a configuration in detail, first, the command decoder 20 provides the active command signal ACT, which is an internal command signal CMD, to the plurality of transfer units 35 in common. The precharge command signal PCG serving as the internal command signal CMD is provided to one combination part 32 or a plurality of precharge parts 37.

The active command signal ACT input to each transfer unit 35 is selectively transmitted to the output unit 36 according to the state of the bank select signals BS <0: m> provided from each bank selector 22. Each bank selection signal BS <0: m> transmitted to each output unit 36 is latched through the output unit 36 and output as a bank activation signal BA_ACT <0: m>.

For example, when only the bank select signal BS <0> of the bank select signals BS <0: m> output from the bank selectors 22 is output in an enabled state, the active command signal ACT is transmitted to the transfer unit 35. And the bank activation signal BA_ACT <0> in the enabled state through the output unit 36 and the other bank activation signals BA_ACT <1: m> are all kept in the disabled state.

When the active operation ends and the precharge operation is performed, the bank activation signal BA_ACT <0; m> in the enabled state is disabled through each precharge unit 37.

That is, in the case where the bank activation signal BA_ACT <0> is enabled and the corresponding bank is activated, the precharge unit 37 receives an external precharge command or passes the precharge unit 37 when the low active time has passed. The output stage of 35) is precharged. Therefore, the bank activation signal BA_ACT <0> remains enabled only within the active period and is disabled during the precharge operation.

As described above, in the semiconductor memory device according to the present invention, when the internal command signal CMD, ie, the active command signal ACT, is generated in the command decoder 20, only the activation path of the corresponding bank is distinguished by identifying which bank is activated. Enable.

That is, the internal command signal CMD output from the command decoder 20 is commonly input to the plurality of bank activation path units 34 and transferred only to the bank activation path unit 34 selected according to the bank selection signals BS <0: m>. Therefore, only one command decoder 20 may be provided.

As described above, since the semiconductor memory device according to the present invention includes only one command decoder 20, the area of the semiconductor memory device according to the present invention may be significantly reduced compared to a configuration in which a command decoder (eg, 10 of FIG. 1) corresponding to the number of banks is conventionally provided. There is an effect that the net die can be improved.

In addition, the bank activation control circuit 26 provided in the semiconductor memory device according to the present invention selectively receives the active command signal ACT, latches the active command signal ACT during the active period, and deactivates the active command signal ACT during the precharge operation. It has a configuration to enable.

Therefore, the bank activation control circuit 26 has only a configuration for selectively transferring the active command signal ACT corresponding to each bank, a configuration for latching the active command signal ACT, and a configuration for disabling the active command signal ACT upon precharging. Just do it.

To this end, the bank activation control circuit 26 according to the present invention includes a plurality of transfer units 35, a plurality of output units 36, and a plurality of precharge units 37 corresponding to banks. Each transfer unit 35, output unit 36, and precharge unit 37 have a minimum configuration as shown in FIG. 3, so that the layout area of the bank activation control circuit 26 can be reduced. have.

In addition, when only one of the precharge command signal PCG and the reset signal RST is enabled, the bank activation signal BA_ACT <0; m> in the enabled state is disabled, so that the bank activation control circuit 26 resets the precharge command signal PCG and the reset signal. The precharge can be controlled by providing a control signal CTRL in combination with the signal RST to the bank activation path parts 34 in common.

Accordingly, the bank activation control circuit 26 according to the present invention has an effect that the layout area can be reduced compared to the configuration in which the precharge is controlled separately by the precharge command signal PCG and the reset signal RST.

1 is a block diagram showing any one of circuits for bank activation control included in a conventional semiconductor memory device.

2 is a block diagram illustrating a portion of a semiconductor memory device for bank activation control according to the present invention;

FIG. 3 is a circuit block diagram showing the detailed configuration of the bank activation control circuit 26 of FIG.

Claims (13)

A command decoder for decoding an external command signal and outputting the external command signal as an internal command signal; A plurality of bank selectors for decoding the bank address signals and outputting the bank address signals corresponding to the banks, respectively; And Bank activation path portions each of which is controlled by the bank selection signals, and including bank activation paths for transmitting the internal command signals to at least one bank activation path portion selected by the bank selection signals and outputting them as bank activation signals; And a control circuit. The method of claim 1, And each bank activation path unit selectively receives the internal command signal according to a state of each bank selection signal and outputs the internal command signal as the bank activation signal. The method of claim 2, And each bank activation path unit outputs the bank activation signal having an enable period from an active entry time to a precharge entry time as the internal command signal. The method of claim 1, The command decoder decodes the external command signal corresponding to active and outputs the active command signal as the internal command signal, decodes the external command signal corresponding to the precharge, and outputs the external command signal as the precharge command signal as the internal command signal. A semiconductor memory device. The method of claim 4, wherein Each bank activation path unit A transfer unit selectively transferring the active command signal according to the state of each bank selection signal; An output unit for latching a signal transmitted from the transfer unit and outputting the bank activation signal; And And a precharge unit for disabling the bank activation signal as the precharge command signal. The method of claim 5, wherein The transfer unit includes a pass gate to selectively transfer the active command signal according to a state of the bank select signal. The method of claim 5, wherein And the precharge unit precharges an output terminal of the transfer unit in response to the precharge command signal. The method of claim 5, wherein The bank activation control circuit, A delay unit delaying the active command signal corresponding to a low active time and outputting a reset signal; And And a combiner configured to combine the reset signal and the precharge command signal to provide the precharge unit with a control signal enabled when one of the reset signal and the precharge command signal is enabled. Device. A plurality of transfer units receiving a command signal in common and selectively transferring the command signals according to bank selection; A plurality of output units connected to output ends of the transfer units, respectively, for latching the command signals and outputting the command signals as bank activation signals when the command signals are transmitted from the transfer units; And And a plurality of precharge units connected to the transfer units and the output units, respectively, for disabling a bank activation signal corresponding to the banks when precharging a predetermined bank. The method of claim 9, And each transfer unit receives the command signal and a bank selection signal for determining the bank selection, and selectively transfers the command signal according to the state of the bank selection signal. The method of claim 10, And each transfer unit includes a pass gate for selectively transferring the command signal in accordance with a state of the bank select signal. The method of claim 9, And each precharge unit is enabled after a low active time has elapsed from an external precharge command or an active command input time point, thereby disabling the bank enable signal. The method of claim 9, And each precharge unit is coupled between each transfer unit and each output unit to precharge the output stage of the transfer unit when precharging the bank.
KR1020070135581A 2007-12-21 2007-12-21 Semiconductor memory device and circuit for controlling bank activity of the same KR20090067800A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9672157B2 (en) 2015-01-26 2017-06-06 SK Hynix Inc. Semiconductor device
CN116913343A (en) * 2023-09-13 2023-10-20 浙江力积存储科技有限公司 Activated precharge feedback circuit and memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9672157B2 (en) 2015-01-26 2017-06-06 SK Hynix Inc. Semiconductor device
CN116913343A (en) * 2023-09-13 2023-10-20 浙江力积存储科技有限公司 Activated precharge feedback circuit and memory
CN116913343B (en) * 2023-09-13 2023-12-26 浙江力积存储科技有限公司 Activated precharge feedback circuit and memory

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