KR20090064993A - Method for forming pattern of semiconductor device - Google Patents

Abstract

A method for forming a pattern of a semiconductor device is provided to reduce an error rate and to improve a yield by preventing generation of a bridge between patterns generated in an isolated line and a spacer through an OPC(Optical Proximity Correction) simulation. A fragmentation process is formed to divide a pattern of an original database into unit edges(S110). A designation process is performed to designate a target point on the unit edge(S120). A first target point and a second target point are moved to a place adjacent to a vertex of the target point(S130). An OPC process is performed. An image simulation process is performed to apply the first target point and the second target point(S140).

Description

Pattern Forming Method of Semiconductor Device {METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE}

The embodiment relates to a method of forming a pattern of a semiconductor device.

The photolithography process is an essential process for manufacturing a semiconductor device. The photolithography process is uniformly applied on a wafer, and then an exposure process is performed using a photo mask formed in a predetermined layout, and the exposed photoresist film is developed. The process of forming in a pattern of a specific shape.

The semiconductor photo lithography technique used in the photolithography process of manufacturing the semiconductor device makes it possible to appropriately control the amount of light emitted from the mask by precisely mask design. To this end, optical proximity correction (OPC) technology and phase shifting mask technology have emerged, and various methods for minimizing light distortion due to the pattern shape drawn on the mask have been sought.

1 is an original database to be implemented on a conventional wafer, and FIG. 2 is an image implemented on a wafer using a mask patterned according to the pattern of FIG. 1.

As shown in FIGS. 1 and 2, when the original database is not fabricated by OPC modeling, the pattern 10 of the original database is not formed as a desired pattern 20 on the wafer, but corners are rounded. The pattern A itself may be lost.

As the design rule has been refined according to the recent high integration of semiconductor devices, a problem arises in that a defect occurs in a pattern due to an optical proximity effect with an adjacent pattern in photolithography process technology.

In particular, when the degree of integration of the semiconductor pattern is very high, there is a problem in that a line width bridge between the patterns is generated and defects are generated and the yield is lowered.

The embodiment provides a method of forming a pattern of a semiconductor device to prevent a bridge from being generated in a pattern close to each other in order to secure a photo process margin during OPC simulation.

According to an embodiment, a method of forming a pattern of a semiconductor device may include: inputting an original database, a fragmentation step of dividing a pattern of the original database into unit edges, specifying a target point on the unit edges, Moving a first target point near a vertex of the target point and a second target point next to the first target point, and applying the first and second target points to perform image simulation after OPC (Optical Proximity Correction) Characterized in that it comprises a step.

The embodiment has the effect of reducing the failure rate and improving the yield by preventing the bridge between the patterns that can be generated in the isolated line and the spacer through OPC simulation.

The embodiment can secure the photo process margin by appropriately moving the target point in the OPC simulation, thereby ensuring the reliability of the process.

Hereinafter, a method of forming a pattern of a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. However, one of ordinary skill in the art who understands the spirit of the present invention may easily propose another embodiment by adding, adding, deleting, or modifying elements within the scope of the same spirit, but this also belongs to the scope of the present invention. I will say.

Hereinafter, a pattern forming method of a semiconductor device according to example embodiments will be described in detail with reference to the accompanying drawings. Hereinafter, when referred to as "first", "second", and the like, this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure being additionally formed therebetween. Therefore, the meaning should be determined by the technical spirit of the invention.

3 is a flowchart illustrating a method of forming a pattern of a semiconductor device according to an exemplary embodiment, and FIGS. 4 to 9 are plan views illustrating a method of forming a pattern of a semiconductor device according to the flowchart of FIG. 3.

The embodiment is used in a process application in which the smallest margin isolated lines and spaces are grown in order to secure photolithography process margins in the OPC process. The photolithography process margin can be secured by improving the bridge generated by the rapid movement of the target point of the unit edge during the OPC simulation.

3 and 4, if the pattern information on the wafer to be formed is an original database, the original database is input to the OPC device (S100).

The OPC equipment that inputs the original database sets the mask pattern so that the pattern closest to the original database can be formed on the wafer by performing optical proximity compensation according to the spacing between the patterns and the size of the pattern, and finally through various optical conditions The operation to predict the image on the formed wafer is performed.

3 and 5, when the original database is input, a process called fragmentation is performed (S110). The fragmentation is a task of dividing the pattern 100 into small pieces to facilitate image simulation according to a predetermined rule according to the corner of the pattern 100 and the surrounding environment of the original database.

Therefore, when the fragmentation operation is performed, the corners of the pattern 100 of the original database are separated into small unit edges UE.

3 and 6, target points are set for the unit edges UE (S120).

The target point is present on the edge of the pattern 100 of the original database, the first unit corner point (F1) near the vertex where the two corners meet is set as the first target point (T1), the first unit corner point The intermediate point between F1 and the second unit corner point F2 is set as the second target point T2.

This operation is performed at the boundary edges of the isolated space and the isolated line.

The first target point T1 and the second target point T2 are set in the same manner at opposite corners and vertices.

As shown in FIGS. 3 and 7, after the first and second target points T1 and T2 are set, the first and second target points T1 and T2 are moved into the pattern (S130). .

Current photolithography processes require the definition of patterns smaller than the resolution limit of exposure equipment. The embodiment intentionally changes the target point during the OPC process so that the isolated lines and the isolated spaces with the least processing margins are implemented on the wafer larger than the drawn size in order to fine-tune patterns smaller than the resolution limit.

As such, the second target point T2 is moved 5 nm to 30 nm from the edge into the pattern to make the photolithography process margin larger than the original database pattern for the isolated line and the isolated space.

In this case, the first target point T1 is moved by a movement distance smaller than the movement distance of the second target point T2.

If the first target point T1 is not moved, the pattern embodied on the wafer due to the rapid movement of the second target point T2 protrudes a lot from the original database, and the bridge defect is not generated at the protruding portion. Although it may be generated, by slightly moving the first target point into the pattern to act as a buffer, it is possible to secure the photolithography process margin while preventing the bridge failure.

The first moving distance a of the first target point T1 may be about 30% to 70% of the second moving distance b of the second target point T2.

The first target point T1 is a first set target point at a vertex where two edges meet, and the second target point T2 is a next target point.

Thereafter, as shown in FIGS. 3 and 8, OPC simulation is performed to move the unit edges to obtain an OPC pattern 110. The OPC pattern 110 is a mask pattern corrected so that the original database can be implemented as close to the original as possible on the wafer in consideration of the diffraction phenomenon of light.

As shown in FIG. 9, when the implementation pattern on the wafer is expected through the OPC simulation, the wafer pattern 120 is not formed to protrude out of the pattern 100 of the original database, and thus the adjacent line in the isolated line and the space pattern is not formed. It is possible to prevent the bridge pattern from being generated between the spaces.

Current photolithography processes fine-tune patterns smaller than the resolution limit of the exposure equipment. In order to fine-tune patterns smaller than the resolution limit, the isolated lines and isolation spaces with the least process margins are sized in the pattern 100 of the original database. By intentionally changing the target point in the OPC process so as to be embodied on the wafer larger, by slightly moving the first target point T1 as a buffer point that bridge failure occurs due to the rapid movement of the second target point T2. I can solve it.

FIG. 10 is a plan view illustrating an OPC simulated image for forming a pattern of a semiconductor device according to an embodiment, and FIG. 11 is an enlarged plan view illustrating a region 'C' of FIG. 10.

As shown in Figs. 10 and 11, the original database pattern 100, which is a pattern smaller than the resolution limit, is fragmented and the unit edges are moved to form the OPC corrected pattern 110, and the target points are moved. OPC simulation can predict the wafer image pattern 120.

At this time, the first target point (T1) of the target point is gently moved by the first moving distance (a), the second target point (T2) by the second moving distance (b) larger than the first moving distance (a) The image pattern 120 may protrude from the original database pattern 100 to prevent the occurrence of a bridge failure with the neighboring pattern at the 'B' point.

That is, since the pattern of the isolation space can be large, the spacing between the patterns can be secured, thereby securing a photolithography process margin.

In the illustrated embodiment, the target point is moved inside the pattern to increase the space size in the isolated space. However, in the case of the isolated line, the target point may be moved outside the pattern to increase the line size.

The embodiment has the effect of reducing the failure rate and improving the yield by preventing the bridge between the patterns that can be generated in the isolated line and the spacer through OPC simulation.

The embodiment can secure the photo process margin by appropriately moving the target point in the OPC simulation, thereby ensuring the reliability of the process.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not exemplified above without departing from the essential characteristics of the present invention. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a raw database to be implemented on a conventional wafer.

FIG. 2 is an image implemented on a wafer using a mask patterned according to the pattern of FIG. 1.

3 is a flowchart illustrating a method of forming a pattern of a semiconductor device according to an embodiment.

4 through 9 are plan views illustrating a method of forming a pattern of a semiconductor device according to the flowchart of FIG. 3.

10 is a plan view illustrating an OPC simulated image for forming a pattern of a semiconductor device according to an embodiment.

FIG. 11 is an enlarged plan view of a region 'C' of FIG. 10.

Claims (5)

Entering a source database; A fragmentation step of dividing the pattern of the original database into unit edges; Designating a target point on the unit edge; Moving a first target point near a vertex of the target points and a second target point after the first target point; And And patterning an image after applying optical proximity correction (OPC) by applying the first and second target points. The method of claim 1, And a first moving distance of the first target point is 30 to 70% of a second moving distance of the second target point. The method of claim 1, The second moving distance is a pattern forming method of a semiconductor device, characterized in that 5nm ~ 30nm. The method of claim 1, And wherein the pattern for moving the first target point and the second target point is an isolated line or an isolated spacer. The method of claim 1, In specifying the target point on the unit edge, And a point separated from the vertex by the first unit corner as the first target point, and a middle point of the second unit corner as the second target point as the second target point.

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