KR20090062026A - Reconfiguable logic circuit and method of reconfiguing the same - Google Patents

Abstract

Disclosed are a reconfigurable logic circuit and a method of reconfiguring the same. The reconfigurable logic circuit includes a first plurality of transistors and a second plurality of variable resistor parts, and according to an operation of the first plurality of transistors corresponding to a plurality of input signals, a first of the second plurality of variable resistor parts. A first input unit whose total resistance value is variable; The fourth plurality of transistors and the fourth plurality of variable resistor parts operating in opposition to the first plurality of transistors, and the fourth plurality of variable transistors according to the operation of the third plurality of transistors corresponding to the input signal. A second input unit for varying second total resistance values of the resistor units; And an output unit configured to output an intermediate voltage between the first and second input units determined as the final output signal according to the first and second total resistance values, wherein the first and second plurality of variable resistor units are respectively. It is programmed to one of at least two resistance values and is reconfigured to one of a first basic logic element and a second basic logic element by varying the first total resistance value and the second total resistance value.

Description

Reconfigurable logic circuit and method of reconfiguing the same}

The present invention relates to a reconfigurable logic circuit, and more particularly, to a reconfigurable logic circuit that can reduce the number of logic elements required to generate at least two or more logic functions and a method for reconfiguring the same.

Application specific integrated circuits (ASICs) of semiconductor devices generally tend to be expensive because they guarantee high performance and set up corresponding processes for each application. Microprocessors, on the other hand, are very flexible, but perform poorly because they run applications only in software.

On the other hand, as an alternative between ASICs and microprocessors, reconfigurable hardware has been developed and studied. Reconfigurable hardware can reconfigure the hardware to suit a particular application, thus satisfactorily satisfying performance and trade-offs between processes. That is, in reconfigurable hardware, the logic function can be reconfigured, for example, by using static random access memory (SRAM) as a switch to control the connection between logical elements in the logic function block. However, in order to implement all the logic functions to be reconstructed, all the logic elements needed for each logic function must be integrated, so more chips are required than those required for a single application. In addition, in the case of a logic function with a large number of connection points, the distance between the logic elements increases, resulting in performance degradation due to signal delay.

The technical problem to be solved by the present invention is to provide a reconfigurable logic circuit that can be selectively driven by at least two basic logic elements.

Another technical problem to be solved by the present invention is to provide a method for reconfiguring the logic circuit described above.

In order to solve the above technical problem, a reconfigurable logic circuit according to the present invention includes a first variable in which a first total resistance value of a second plurality of variable resistor parts is changed according to operations of a first plurality of transistors corresponding to a plurality of input signals. An input unit; A second input unit in which a second total resistance value of the fourth plurality of variable resistor units is changed according to an operation of the third plurality of transistors opposite to the first plurality of transistors in response to the input signal; And an output unit configured to output an intermediate voltage between the first and second input units determined as the final output signal according to the first and second total resistance values, wherein the first and second plurality of variable resistor units are respectively. It is programmed to one of at least two resistance values and is reconfigured to one of a first basic logic element and a second basic logic element by varying the first total resistance value and the second total resistance value.

In order to solve the above technical problem, a reconfigurable logic circuit according to the present invention includes a first variable in which a first total resistance value of a second plurality of variable resistor parts is changed according to operations of a first plurality of transistors corresponding to a plurality of input signals. An input unit; A second input unit configured to vary a second total resistance value of the fourth plurality of variable resistor units according to an operation of the third plurality of transistors opposite to the first plurality of transistors in response to the input signal; And an output unit configured to output an intermediate voltage between the first and second input units determined as the final output signal according to the first and second total resistance values, and included in each gate array. The first and second plurality of variable resistance parts are programmed to each of at least two resistance values, and the gate array is connected to the first basic logic element by varying the first total resistance value and the second total resistance value. It is reconfigured to one of the second basic logic elements.

In order to solve the above other technical problem, the reconstruction method of the logic circuit according to the present invention may change the first total resistance of the second plurality of variable resistor parts according to the operation of the first plurality of transistors corresponding to the plurality of input signals. Configuring a first input unit; Configuring a second input unit in which a second total resistance value of the fourth plurality of variable resistor units is changed according to an operation of the third plurality of transistors opposite to the first plurality of transistors in response to the input signal; Configuring an output unit to output an intermediate voltage between the first and second input units determined as the final output signal according to the first and second total resistance values; And programming the first and second plurality of variable resistance parts to each of at least two resistance values so as to be reconfigured into one of the first basic logic element and the second basic logic element.

The reconstruction method of the logic circuit may be embodied as a computer-readable recording medium that records a program for execution in a computer.

According to the reconfigurable logic circuit and the reconstruction method of the present invention, since one general-purpose logic element plays the role of at least two basic logic elements without using SRAM and a switch as compared with the related art, the chip area can be reduced, It is not necessary to have all the logic elements necessary to implement each logic function, thereby reducing the distance between logic elements, and as a result, there is an effect of reducing the delay time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B show a logic circuit of a typical NOR gate and a NAND gate, respectively, and FIG. 1C shows a selective use of a NOA gate and a NAND gate as a comparative example of a reconfigurable logic circuit according to the present invention. Referring to FIGS. 1A and 1B, the NOR gate 110 and the NAND gate 120 correspond to logic devices that are most widely used as four transistors, respectively. Referring to FIG. 1C, the logic circuit 170 for selectively using the NOR gate and the NAND gate may include the NOA gate 110, the NAND gate 120, the SRAM controller 130, the inverter 140, the first and the first gates. It consists of two switches 150 and 160. In this configuration, six for the SRAM control unit 13, two for the inverter 140, four for the first and second switches 150 and 160, for the noah gate 110 and the NAND gate 120. This takes eight transistors and a total of 20 transistors.

Figure 2 illustrates the concept of a reconfigurable logic circuit according to the present invention. Referring to FIG. 2, the logic function blocks 210 and 230 are for implementing at least two logic functions. The general logic function block 210 uses all possible logic elements 221, 223, 225, and 227 to implement each logic function. In the logic function block 230 according to the present invention, the logic elements 221, 223, 225, and 227 are implemented as one general-purpose logic element 240. Here, the logic elements 221, 223, 225, and 227 perform one of basic logic, for example, a Noah operation and a NAND operation, required to implement a plurality of logic functions. The general purpose logic element 240 of the logic function block 230 according to the present invention operates as either the first basic logic element or the second basic logic element depending on the application. Here, examples of the first basic logic element and the second basic logic element are a noah gate and a NAND gate, respectively.

3 illustrates the concept of the present invention described with reference to FIG. 2 in detail. One logic function block 310 or 330 generates two logic functions, for example, Y1 = ABCD and Y2 = AB (C + D). The general logic function block 310 includes basic logic elements 321, 322 and 323 for generating the first logic function Y1 and basic logic elements 324, 325 and 326 for generating the second logic function Y2. It can be used selectively according to the logic function. Meanwhile, in addition to the basic logic elements 341 and 345 which are commonly required to implement two logic functions Y1 and Y2, the logic function block 330 according to the present invention may be used separately. Is implemented as one general-purpose logic element 343, and controls the basic logic selectively required in the general-purpose logic element 343 according to the corresponding logic function.

4 shows an example of implementing eight logic functions with three basic logic elements using a reconfigurable logic circuit according to the present invention. According to FIG. 4, when eight logic functions are implemented, the basic logic element requires 24 transistors, that is, at least 3 * 8 * 4 = 96 transistors, and input signals A and B, input signals C and D, and outputs. When implemented as shown in FIG. 1C such that a basic logic element for the signals Y1 to Y8 is used as either a noah gate or a NAND gate, at least 20 * 3 = 60 transistors are required. Meanwhile, according to the present invention, the basic logic elements for the input signals A and B, the input signals C and D, and the output signals Y1 to Y8 are constituted by general-purpose logic elements 410, 430, and 430, respectively, to operate as noah gates or NAND gates depending on the application. In this case, three general-purpose logic devices can be used to significantly reduce the chip area compared to the 24 basic logic devices.

5 shows an example of a variable resistance device used in the present invention, a magnetic random access memory (MRAM) device using a resistance change of a magnetic tunneling junction (MTJ) cell according to a magnetization state of a ferromagnetic material, and a random random access memory (RRAM). ) And a phase-change random access memory (PRAM) device in which a resistance value is changed due to a phase change, but is not limited thereto. For convenience of description, an example of implementing a variable resistance element as an MRAM element will be described.

Referring to FIG. 5, the variable resistor element 500 may include a variable resistor 530 and further include upper and lower electrodes 510 and 520. The variable resistor 530 has at least two different resistance states, for example, a low resistance state and a high resistance state, depending on the current applied thereto. When the variable resistor 530 is implemented as an MTJ cell, the free layer 541, the tunneling layer 543, the pinned layer 545, and the anti-ferromagnetic layer are sequentially stacked. (547). The free layer 541 and the pinned layer 545 are ferromagnetic layers, and the tunneling layer 543 may be an oxide layer as an insulating layer for tunneling electrons. For example, the free layer 541, the tunneling layer 543, the pinned layer 545, and the antiferromagnetic layer 547 may be a CoFeB layer, an MgO layer, a CoFeB layer, and a PtMn layer, respectively. Since the antiferromagnetic layer 547 serves to fix the magnetization direction of the pinned layer 545, the magnetization direction of the pinned layer 545 is fixed in a predetermined direction. The magnetization direction of the free layer 545 may vary depending on the current applied to the variable resistor 530. In FIG. 5, the arrows displayed on the free layer 541, the pinned layer 545, and the antiferromagnetic layer 547 represent examples of magnetization directions each of them may have. When the free layer 541 has the same magnetization direction as the fixed layer 545, the variable resistor 530 is in a parallel state (P), and the variable resistor 530 has a small resistance value. On the other hand, when the free layer 541 has a magnetization direction opposite to the pinned layer 545, the variable resistor 530 is in an anti-parallel state (AP), and the variable resistor 530 is high. It has a resistance value. In one embodiment, the relationship between the resistance value in the parallel state and the resistance value in the antiparallel state is set to 1: 3, but is not limited thereto and may vary according to the constituents of each layer.

The structure of the variable resistor 530 illustrated in FIG. 5 is only an example of an MTJ cell structure, and the MTJ cell structure that may be used as the variable resistor 530 may be variously modified. For example, the variable resistor 530 having the MTJ cell structure can be reversed up and down, and has a non-magnetic separation layer such as a Ru layer and a CoFe layer between the fixed layer 545 and the antiferromagnetic layer 547. The same ferromagnetic layer may be further provided. In addition, the variable resistor 530 may have a structure similar to that of a storage unit used in a structure other than the MTJ cell structure, for example, RRAM, PRAM, and FRAM. That is, the variable resistance element 530 may have a structure including a data storage layer formed of any one of a resistance change layer, a phase change layer, and a ferroelectric layer.

Although not shown, a magnesium oxide layer or a silicon oxide layer may be used to prevent unwanted leakage of current between the upper electrode 510 and / or the lower electrode 520 and the variable resistor 530 and for other purposes. A resistive barrier layer such as may be further provided.

In the variable resistance element as shown in FIG. 5, currents in the first or second directions D1 and D2 may flow through the variable resistor 530 according to a voltage applied between the upper electrode 510 and the lower electrode 520. have. In this case, the variable resistor 530 may be in a low resistance state (parallel state) or a high resistance state (antiparallel state) according to the magnitude, direction, and / or application time of the current.

6A and 6B illustrate a resistance state according to the magnitude and direction of a current flowing through the variable resistance element shown in FIG. 5.

When the current I in the first direction D1 flows through the variable resistor 530, electrons move in the second direction D2, and when the current I becomes larger than the critical current Ic, As shown in FIG. 6A, in the variable resistor 530, the free layer 541 is magnetized in the same direction as the pinned layer 545 to form a parallel state (P). This is because only electrons having the same magnetization direction as the pinned layer 545 pass through the pinned layer 545 to magnetize the free layer 541.

On the other hand, when the current I in the second direction D2 flows through the variable resistor 530, electrons move in the first direction D1, where the current I is greater than the critical current Ic. 6b, the free layer 541 is magnetized in a direction opposite to the pinned layer 545 to become an antiparallel state (AP). This is because electrons having a magnetization direction opposite to the pinned layer 545 accumulate in the free layer 541 to magnetize the free layer 541.

The transition to the parallel or antiparallel state in the variable resistance element implemented by the MTJ cell is due to the spin transfer torque (STT) phenomenon.

7 is a circuit diagram illustrating a configuration of a reconfigurable logic circuit according to an embodiment of the present invention. The reconfigurable logic circuit includes a first input unit 710, a second input unit 730, and an output unit 750. The first input unit 710 may include at least two P-type first and second transistors TR11 and TR12 corresponding to the number of input signals, between the intermediate voltage V and the first transistor TR11, and the first transistor ( The first to third variable resistance parts VR11, VR12, and VR13 are respectively disposed between the TR11 and the second transistor TR12, and between the first power supply voltage VDD and the second transistor TR12. The second input unit 730 includes at least two N-type third and fourth transistors TR21 and TR22 corresponding to the number of input signals, the second power supply voltage VSS, the third transistor TR21 and the third transistor. Fourth to sixth variable resistor parts VR21, VR22, and VR23 are disposed between TR21 and fourth transistor TR22, and between intermediate voltage V and fourth transistor TR22, respectively. The output unit 750 includes an N-type fifth transistor TR31 and a P-type sixth transistor TR32. Here, for the convenience of description, an embodiment in which the input signal is X and Y is disclosed. However, the general-purpose logic elements of NOR and NAND gates having two or more input signals are modified by modifying the circuit shown in FIG. It can be seen that.

In detail, the gate terminal of the first transistor TR11 is connected to the first input signal X, the drain terminal is connected to the first power supply voltage VDD, and the source terminal is formed by the first variable resistor VR11. 1 terminal is connected. The first terminal of the second variable resistance unit VR12 is connected to the source terminal of the first transistor VR11, and the second terminal is connected to the drain terminal of the second transistor VR12. The first terminal of the third variable resistor unit VR13 is connected to the first power supply voltage VDD and the second terminal is connected to the drain terminal of the second transistor VR12. The gate terminal of the second transistor TR12 is connected to the second input signal Y, and the drain terminal is connected to the second terminal of the third variable resistance part VR13. The second terminal of the first variable resistor unit VR11 and the source terminal of the second transistor TR12 provide an intermediate voltage V and are connected to an input terminal of the output unit 750. The gate terminal of the third transistor TR21 is connected to the first input signal X, the drain terminal is connected to the second terminal of the first variable resistor unit VR11, and the source terminal is connected to the first terminal of the fourth variable resistor unit VR21. Connected to the terminal. The first terminal of the fifth variable resistor unit VR22 is connected to the source terminal of the third transistor VR21, and the second terminal is connected to the drain terminal of the fourth transistor VR22. The first terminal of the sixth variable resistor unit VR23 is connected to the source terminal of the second transistor VR12, and the second terminal is connected to the drain terminal of the fourth transistor VR22. The gate terminal of the fourth transistor TR22 is connected to the second input signal Y, the drain terminal is connected to the second terminal of the sixth variable resistor unit VR23, and the source terminal is connected to the second power supply voltage VSS.

Referring to FIG. 7, in the first input unit 710, the first and second transistors TR11 and TR12 are turned on or turned off in accordance with logic signals of the first and second input signals X and Y. In accordance with the operation of the first and second transistors TR11 and TR12, the total resistance values of the first to third variable resistance parts VR11, VR12, and VR13 are varied.

In the second input unit 730, the third and fourth transistors TR21 and TR22 are different from the first and second transistors TR11 and TR12 according to logic signals of the first and second input signals X and Y. In reverse operation, the total resistance values of the fourth to sixth variable resistor parts VR21, VR22, and VR23 are varied according to the operations of the third and fourth transistors TR21 and TR22.

The output unit 750 includes the total resistance values of the first to third variable resistor units VR11, VR12, and VR13 of the first input unit 710 and the fourth to sixth variable resistor units VR21 of the second input unit 730. The intermediate voltage V determined according to the overall resistance values of VR22 and VR23 is input, and the final output signal Vout is determined and output according to the magnitude of the intermediate voltage V.

FIG. 8 shows a truth table of NAND gates or NOR gates according to the resistance of the variable resistor unit in the logic circuit shown in FIG. 7. An operation of the NAND gate and the NOA gate according to the logic value of the input signal will be described in detail with reference to FIGS. 7 and 8.

In order for the logic circuit of FIG. 7 to operate as a NAND gate, the first to sixth variable resistor units VR11, VR12, VR13. VR21, VR22, and VR23 each have a low resistance, a high resistance, a low resistance, a high resistance, and a low resistance. It is preprogrammed with high resistance. Here, the low resistance is 1 kilo ohm (kΩ), the high resistance is 3 kilo ohms (kΩ) as an example.

When the first input signal X is '1' and the second input signal Y is '0', the first transistor TR11 is turned off and the second transistor TR12 is turned on. Therefore, the total resistance value of the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 is 1 kΩ, which is the resistance value of the third variable resistance part VR13. Meanwhile, when the first input signal X is '1' and the second input signal Y is '0', the third transistor TR21 is turned on and the fourth transistor TR22 is turned off. Therefore, the total resistance value of the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 is 3 kΩ, which is the resistance value of the fourth variable resistance part VR21. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 4 kΩ in total, and when VDD = 1 V and VSS = 0 V, the current becomes 0.25 mA so that the intermediate voltage V is 0.75. It becomes V. When the intermediate voltage V is 0.75V, the fifth transistor TR31 is turned on, the sixth transistor TR32 is turned off, and the final output signal Vout outputs '1'.

When the first input signal X is '0' and the second input signal Y is '1', the first transistor TR11 is turned on and the second transistor TR12 is turned off. Therefore, the total resistance value of the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 is 1 kΩ, which is the resistance value of the first variable resistance part VR11. Meanwhile, when the first input signal X is '0' and the second input signal Y is '1', the third transistor TR21 is turned off and the fourth transistor TR22 is turned on. Therefore, the total resistance value of the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 is 3 kΩ, which is the resistance value of the sixth variable resistance part VR23. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 4 kΩ in total, and when VDD = 1 V and VSS = 0 V, the current becomes 0.25 mA so that the intermediate voltage V is 0.75. It becomes V. When the intermediate voltage V is 0.75V, the fifth transistor TR31 is turned on, the sixth transistor TR32 is turned off, and the final output signal Vout outputs '1'.

When the first input signal X is '0' and the second input signal Y is '0', the first transistor TR11 is turned on and the second transistor TR12 is turned on. Accordingly, the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 are connected in parallel, and the total resistance thereof is 3/8 kΩ. Meanwhile, when the first input signal X is '0' and the second input signal Y is '0', the third transistor TR21 is turned off and the fourth transistor TR22 is turned off. . Accordingly, the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 are connected in series, and the total resistance thereof is 7 kΩ. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 59/8 kΩ in total, and when VDD = 1 V and VSS = 0 V, the current becomes 8/59 mA so that the intermediate voltage ( V) becomes 0.95V. When the intermediate voltage V is 0.95V, the fifth transistor TR31 is turned on, the sixth transistor TR32 is turned off, and the final output signal Vout outputs '1'.

When the first input signal X is '1' and the second input signal Y is '1', the first transistor TR11 is turned off and the second transistor TR12 is turned off. Accordingly, the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 are connected in series, and the total resistance thereof is 5 kΩ. Meanwhile, when the first input signal X is '1' and the second input signal Y is '1', the third transistor TR21 is turned on and the fourth transistor TR22 is turned on. Accordingly, the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 are connected in parallel, and the total resistance thereof is 3/5 kΩ. The total resistance of the first input unit 710 and the total resistance of the second input unit 730 total 28/5 kΩ, and when VDD = 1 V and VSS = 0 V, the current becomes 5/28 mA so that the intermediate voltage ( V) becomes 0.11V. When the intermediate voltage V is 0.11V, the fifth transistor TR31 is turned off and the sixth transistor TR32 is turned on so that the final output signal Vout outputs '0'.

In summary, in the logic circuit of FIG. 7, the first to sixth variable resistor parts VR11, VR12, VR13. VR21, VR22, and VR23 each have a low resistance, a high resistance, a low resistance, a high resistance, a low resistance, and a high resistance. If it is set to, it can be seen that it operates as a NAND gate.

Meanwhile, in order for the logic circuit of FIG. 7 to operate as a noar gate, the first to sixth variable resistor parts VR11, VR12, VR13. VR21, VR22, and VR23 each have a high resistance, a low resistance, a high resistance, a low resistance, Programmed as high resistance, low resistance. Similarly, low resistance is set to 1 kiloohm (kΩ) and high resistance to 3 kiloohms (kΩ).

When the first input signal X is '1' and the second input signal Y is '0', the first transistor TR11 is turned off and the second transistor TR12 is turned on. Therefore, the total resistance value of the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 is 3 kΩ, which is the resistance value of the third variable resistance part VR13. Meanwhile, when the first input signal X is '1' and the second input signal Y is '0', the third transistor TR21 is turned on and the fourth transistor TR22 is turned off. Therefore, the total resistance value of the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 is 1 kΩ, which is the resistance value of the fourth variable resistor part VR21. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 4 kΩ in total, and when VDD = 1V and VSS = 0V, the current becomes 0.25 mA and the intermediate voltage V is 0.25. It becomes V. When the intermediate voltage V is 0.25V, the fifth transistor TR31 is turned off and the sixth transistor TR32 is turned on so that the final output signal Vout outputs '0'.

When the first input signal X is '0' and the second input signal Y is '1', the first transistor TR11 is turned on and the second transistor TR12 is turned off. Therefore, the total resistance value of the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 is 3 kΩ, which is the resistance value of the first variable resistance part VR11. Meanwhile, when the first input signal X is '0' and the second input signal Y is '1', the third transistor TR21 is turned off and the fourth transistor TR22 is turned on. Accordingly, the total resistance value of the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 is 1 kΩ, which is the resistance value of the sixth variable resistor part VR23. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 4 kΩ in total, and when VDD = 1 V and VSS = 0 V, the current becomes 0.25 mA and the intermediate voltage V is 0.25. It becomes V. When the intermediate voltage V is 0.75V, the fifth transistor TR31 is turned off and the sixth transistor TR32 is turned on so that the final output signal Vout outputs '0'.

When the first input signal X is '0' and the second input signal Y is '0', the first transistor TR11 is turned on and the second transistor TR12 is turned on. Accordingly, the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 are connected in parallel, and the total resistance thereof is 3/5 kΩ. Meanwhile, when the first input signal X is '0' and the second input signal Y is '0', the third transistor TR21 is turned off and the fourth transistor TR22 is turned off. . Accordingly, the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 are connected in series, and the total resistance thereof is 5 kΩ. The total resistance of the first input unit 710 and the total resistance of the second input unit 730 total 28/5 kΩ, and when VDD = 1 V and VSS = 0 V, the current becomes 5/28 mA so that the intermediate voltage ( V) becomes 0.89V. When the intermediate voltage V is 0.89V, the fifth transistor TR31 is turned on, the sixth transistor TR32 is turned off, and the final output signal Vout outputs '1'.

When the first input signal X is '1' and the second input signal Y is '1', the first transistor TR11 is turned off and the second transistor TR12 is turned off. Accordingly, the first to third variable resistance parts VR11, VR12, and VR13 of the first input part 710 are connected in series, and the total resistance thereof is 7 kΩ. Meanwhile, when the first input signal X is '1' and the second input signal Y is '1', the third transistor TR21 is turned on and the fourth transistor TR22 is turned on. Accordingly, the fourth to sixth variable resistor parts VR21, VR22, and VR23 of the second input part 730 are connected in parallel, and the total resistance thereof is 3/8 kΩ. The total resistance value of the first input unit 710 and the total resistance value of the second input unit 730 are 59/8 kΩ in total, and when VDD = 1 V and VSS = 0 V, the current becomes 8/59 mA so that the intermediate voltage ( V) becomes 0.05V. When the intermediate voltage V is 0.05V, the fifth transistor TR31 is turned off and the sixth transistor TR32 is turned on so that the final output signal Vout outputs '0'.

In summary, in the logic circuit of FIG. 7, the first to sixth variable resistor parts VR11, VR12, VR13. VR21, VR22, and VR23 each have a high resistance, a low resistance, a high resistance, a low resistance, a high low resistance, and a low resistance. If it is set to, it can be seen that it operates as a noah gate.

On the other hand, it is preferable to select the fifth transistor TR31 and the sixth transistor TR32 having an appropriate threshold Vth, for example, a threshold of 0.5V, so that the logic circuit of FIG. 7 operates as a NAND gate or a no-gate. .

Although not shown in FIG. 7, the first to sixth resistors VR11, VR12, VR13, VR21, VR22, and VR23 are applied to the first and second transistors TR11 and TR12 in advance to program the first to sixth variable resistor parts VR11, VR12, VR13, VR21, VR22, and VR23. At least one transistor may be further provided to block the power supply voltage VDD and the second power supply voltage VSS applied to the third and fourth transistors TR21 and TR22. In addition, a signal for turning off or turning on the transistor may be provided from a separate controller (not shown).

FIG. 9 is a diagram for describing a method of programming the first to sixth variable resistor parts VR11, VR12, VR13, VR21, VR22, and VR23 shown in FIG. 7.

9, the third variable resistor unit VR13 and the sixth variable resistor unit VR23 are connected to each other in the first to sixth variable resistor units VR11, VR12, VR13, VR21, VR22, and VR23. The first variable resistor unit VR11 is connected in series to the fourth variable resistor unit VR21, and the third variable resistor unit VR11 is connected to the third power supply voltage V _CC , and the fourth variable resistor unit VR21 is connected to the fourth variable resistor unit VR21. The fourth power voltage V _REF is applied to allow current to flow. At this time, the direction of the current is changed according to the magnitudes of V _CC and V _REF , and each of the variable resistance units VR11, VR12, VR13, VR21, VR22, and VR23 is programmed with different values according to the direction of the current.

Although not shown in FIG. 9, after the programming of the first to sixth variable resistor parts VR11, VR12, VR13, VR21, VR22, and VR23 is completed, a third power supply voltage applied to the first variable resistance part VR11 ( V _CC ), the fourth power supply voltage V _REF applied to the fourth variable resistor unit VR21, and the connection between the third variable resistor unit VR13 and the sixth variable resistor unit VR23. At least one transistor may be further provided to cut off. In addition, a signal for turning off or turning on the transistor may be provided from a separate controller (not shown).

10A and 10B are diagrams illustrating a current direction according to the magnitudes of V _CC and V _REF and a programming state of each of the variable resistor units 1010 to 1060 in FIG. 9. Here, the serial connection order of the first to sixth variable resistor parts VR11, VR12, VR13, VR21, VR22, and VR23 is VR11, VR12, VR13, VR23, VR22, and VR21.

Referring to FIG. 10A, when V _CC is 2 V and V _REF is 0 V, current flows from the first variable resistor parts VR11 and 1010 to the fourth variable resistor parts VR21 and 1060. When each of the variable resistor units 1010 to 1060 has the same configuration as that of the variable resistor element shown in FIG. 5, the first variable resistor units VR11 and 1010, the third variable resistor units VR13 and 1030, and the fifth variable unit are configured. In the resistor units VR22 and 1050, current flows in the first direction D1 to form a parallel state P, thereby having low resistance. Meanwhile, current flows in the second direction D2 in the second variable resistor parts VR12 and 1020, the sixth variable resistor parts VR23 and 1040, and the fourth variable resistor parts VR21 and 1060. It becomes the state AP and has high resistance.

Referring to FIG. 10B, when V _CC is 0 V and V _REF is 2 V, current flows from the fourth variable resistor parts VR21 and 1060 to the first variable resistor parts VR11 and 1010. When each of the variable resistor units 1010 to 1060 has the same configuration as that of the variable resistor element shown in FIG. 5, the first variable resistor units VR11 and 1010, the third variable resistor units VR13 and 1030, and the fifth variable unit are configured. The resistors VR22 and 1050 have a high resistance because current flows in the second direction D2 to become an antiparallel state AP. Meanwhile, current flows in the first direction D1 in the second variable resistor parts VR12 and 1020, the sixth variable resistor parts VR23 and 1040, and the fourth variable resistor parts VR21 and 1060. It becomes (P) and has low resistance.

11A and 11B illustrate a method of operating a plurality of gate arrays when the reconfigurable logic circuit shown in FIG. 7 is configured as one gate array.

FIG. 11A illustrates a circuit implemented to operate a plurality of gate arrays as noah gates or end gates. In one embodiment, four gate arrays 1110 to 1140, each gate array 1110 to 1140, and a first power source are illustrated. A seventh transistor TR41 connected between the voltage VDD, and an eighth transistor TR42 connected between each of the gate arrays 1110-1140 and the second power supply voltage VSS. And the eighth transistors TR41 and TR42 may be any one of a P type and an N type, referring to FIG. The eighth transistors TR41 and TR42 are turned off to prevent the first power voltage VDD and the second power voltage VSS from being applied to each of the gate arrays 1110 to 1140. When programming of the variable resistor part included in 1110 to 1140 is completed, the seventh and eighth times The transistors TR41 and TR42 are turned on to apply the first power supply voltage VDD and the second power supply voltage VSS to each of the gate arrays 1110 to 1140. At this time, the seventh and eighth transistors TR41 are applied. The signal for turning off or turning on TR 42 may be provided from a separate controller (not shown).

FIG. 11B is a circuit implemented to program the variable resistors included in each of the gate arrays 1110 to 1140. In one embodiment, the third power supply voltage V _CC and the first and third gate arrays 1110 and 1130 are illustrated in FIG. ), A ninth transistor TR51 connected between the third power source voltage V _CC , and a tenth transistor TR52 connected between the second and fourth gate arrays 1120 and 1140, and a fourth power supply voltage V. _REF ) connected between the eleventh transistor TR61 and the fourth power voltage V _REF connected to the first and second gate arrays 1110 and 1120 and the third and fourth gate arrays 1130 and 1140. And the ninth through twelfth transistors TR51, TR52, TR61, and TR62 may be any of P type and N type, referring to Fig. 11B. When programming the variable resistance parts of 1110, the third power supply is turned on by turning on the ninth transistor TR51 and the eleventh transistor TR61. Such that applying a (V _CC) and a fourth power supply voltage (V _REF). The case of programming the variable resistance portions of the second gate array 1120, by turning on the tenth transistor (TR52) and the eleventh transistor (TR61) The third power source voltage V _CC and the fourth power source voltage V _REF are applied to each other When the variable resistor parts of the third gate array 1130 are programmed, the ninth transistor TR51 and the twelfth transistor TR62 are programmed. ) Is turned on to apply the third power supply voltage V _CC and the fourth power supply voltage V _REF , etc. When programming the variable resistor parts of the fourth gate array 1140, the tenth transistor TR52 and the fourth power supply voltage V _CC are applied. The 12 transistor TR62 is turned on to apply the third power voltage V _CC and the fourth power voltage V _REF .

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. And functional programs, codes and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1A and 1B show a logic circuit of a typical NOR gate and a NAND gate, respectively, and FIG. 1C shows a comparative example of a reconfigurable logic circuit according to the present invention.

2 is a diagram illustrating the concept of a reconfigurable logic circuit according to the present invention.

3 is a view showing in detail the concept of the present invention described in FIG.

4 is a view showing an example of implementing eight logic functions with three basic logic elements using a reconfigurable logic circuit according to the present invention.

5 is a view showing an example of a variable resistance element used in the present invention.

6A and 6B are diagrams illustrating a resistance state according to the magnitude and direction of a current flowing through the variable resistance element illustrated in FIG. 5.

7 is a circuit diagram illustrating a configuration of a reconfigurable logic circuit according to an embodiment of the present invention.

FIG. 8 shows a truth table of NAND gates or NOR gates according to the resistance of the variable resistor unit in the logic circuit shown in FIG. 7.

FIG. 9 is a diagram for describing a method of programming the first to sixth variable resistor parts shown in FIG. 7.

10A and 10B are diagrams illustrating a direction of current and a programming state of each variable resistor unit according to the magnitudes of V _CC and V _REF in FIG. 9.

11A and 11B illustrate a method of operating a plurality of gate arrays when the reconfigurable logic circuit shown in FIG. 7 is configured as one gate array.

Claims (23)

A first input unit configured to vary a first total resistance value of the second plurality of variable resistor units according to operations of the first plurality of transistors corresponding to the plurality of input signals; A second input unit in which a second total resistance value of the fourth plurality of variable resistor units is changed according to an operation of a third plurality of transistors opposite to the first plurality of transistors in response to the input signal; And An output unit configured to output an intermediate voltage between the first and second input units determined according to the first and second total resistance values as a final output signal, Each of the first and second plurality of variable resistor parts may be programmed to at least two resistance values, and the first and second basic logic elements may be changed by varying the first and second total resistance values. Reconfigurable logic circuit reconfigured into one. 2. The reconfigurable logic circuit of claim 1 wherein the first basic logic element is a nogate and the second basic logic element is a NAND gate. The reconfigurable logic circuit of claim 1, wherein the first and second variable resistor units are implemented as one of an MRAM device, an RRAM device, and a PRAM device having a variable resistance due to a phase change. . According to claim 1, The first input unit includes first and second transistors connected to first and second input signals, respectively, between the intermediate voltage and the first transistor, between the first transistor and the second transistor, and a first power supply voltage. First to third variable resistance parts respectively disposed between the second transistors, The second input unit includes third and fourth transistors connected to the first and second input signals, respectively, a second power supply voltage and the third transistor, between the third transistor and the fourth transistor, and the intermediate voltage. And fourth to sixth variable resistor parts respectively disposed between the fourth transistor and the fourth transistor. 2. The method of claim 1, wherein when the first and second plurality of variable resistor units are formed of an MRAM device using a resistance change of an MTJ cell, the variable resistor units are programmed to one of the at least two resistance values by adjusting a direction of a flowing current. Reconfigurable logic circuit. The method of claim 4, wherein when the logic circuit operates as a NAND gate, the first, third and fifth variable resistor parts have a first resistance value, and the second, fourth and sixth variable resistor parts have the first resistance value. A reconfigurable logic circuit programmed to have a second resistance value less than the resistance value. 5. The variable resistance circuit of claim 4, wherein the first, third, and fifth variable resistor parts have a first resistance value, and the second, fourth, and sixth variable resistor parts have a first resistance value. A reconfigurable logic circuit programmed to have a second resistance value higher than the resistance value. The method of claim 4, wherein in order to program the first to sixth variable resistor parts, the connection of the first power supply voltage and the first input unit and the connection of the second power supply voltage and the second input unit are disconnected. A reconfigurable logic circuit configured to apply the third power supply voltage and the fourth power supply voltage by configuring the first to sixth variable resistor parts connected in series. The method of claim 8, wherein when the first and second plurality of variable resistor parts are formed of an MRAM device using resistance changes of an MTJ cell, the first and sixth variable values are varied by varying the magnitudes of the third and fourth power supply voltages. A reconfigurable logic circuit that controls the direction of the current flowing through the resistor. A first input unit configured to vary a first total resistance value of the second plurality of variable resistor units according to operations of the first plurality of transistors corresponding to the plurality of input signals; A second input unit in which a second total resistance value of the fourth plurality of variable resistor units is changed according to an operation of the third plurality of transistors opposite to the first plurality of transistors in response to the input signal; And an output unit configured to output an intermediate voltage between the first and second input units determined as the final output signal based on the first and second total resistance values. The first and second plurality of variable resistor parts included in each of the gate arrays may be programmed to each of at least two resistance values, and the gate array may be adjusted by varying the first total resistance value and the second total resistance value. A reconfigurable logic circuit reconfigured into one of a first basic logic element and a second basic logic element. The fifth plurality of transistors of claim 10, wherein the logic circuit supplies or cuts off a first power supply voltage and a second power supply voltage connected to each of the gate arrays for programming each of the variable resistor parts included in the gate arrays. Reconfigurable logic further comprising. 12. The reconfigurable circuit of claim 11, wherein the logic circuit further comprises a sixth plurality of transistors for supplying or disconnecting a third power supply voltage and a fourth power supply voltage to each gate array for selectively programming the respective gate arrays. Logic circuit. 11. The reconfigurable logic circuit of claim 10 wherein the first basic logic element is a nogate and the second basic logic element is a NAND gate. The reconfigurable logic circuit of claim 10, wherein the first and second plurality of variable resistor parts are implemented as MRAM devices using a resistance change of an MTJ cell. 11. The reconfigurable logic circuit of claim 10 wherein the first and second plurality of variable resistor portions are programmed to one of the at least two resistance values by adjusting the direction of the flowing current. Constructing a first input unit in which a first total resistance value of the second plurality of variable resistor units is changed according to operations of the first plurality of transistors corresponding to the plurality of input signals; Configuring a second input unit in which a second total resistance value of the fourth plurality of variable resistor units is changed according to an operation of the third plurality of transistors opposite to the first plurality of transistors in response to the input signal; Configuring an output unit to output an intermediate voltage between the first and second input units determined as the final output signal according to the first and second total resistance values; And Programming each of the first and second plurality of variable resistance parts to at least two resistance values so as to be reconfigured to one of a first basic logic element and a second basic logic element. 17. The method of claim 16, wherein the first basic logic element is a nogate and the second basic logic element is a NAND gate. 17. The logic circuit of claim 16, wherein the first and second plurality of variable resistor units are implemented as one of an MRAM device, an RRAM device, and a PRAM device having a variable resistance due to a phase change. Way. The method of claim 16, In the configuring of the first input unit, first and second transistors connected to the first and second input signals, respectively, between the intermediate voltage and the first transistor, the first transistor and the second transistor. Between the first power supply voltage and the second transistor, and having first to third variable resistor parts respectively, In the second input unit configuring step, between the third and fourth transistors, the second power supply voltage and the third transistor, respectively, connected to the first and second input signals, between the third transistor and the fourth transistor, And a fourth to sixth variable resistor parts respectively disposed between the intermediate voltage and the fourth transistor. 17. The method of claim 16, wherein in the programming step, when the first and second plurality of variable resistor units are formed of an MRAM element using a resistance change of an MTJ cell, each of the variable resistor units controls the direction of the current flowing through the at least two resistance values. A method of reconfiguring a logic circuit that is programmed to one of the following. 20. The method of claim 19, wherein, in the programming step, when the logic circuit operates as a NAND gate, the first, third and fifth variable resistor parts include a first resistance value, and the second, fourth and sixth variable resistors. The reprogramming method of a logic circuit for programming to have a second resistance value lower than the first resistance value. 20. The method of claim 19, wherein, in the programming step, when the logic circuit operates as a no-gate, the first, third and fifth variable resistor parts are provided with a first resistance value, and the second, fourth and sixth variable resistors are used. The reprogramming method of the logic circuit for programming to have a second resistance value higher than the first resistance value. 20. The method of claim 19, wherein in the programming step, the connection of the first power supply voltage and the first input unit and the connection of the second power supply voltage and the second input unit are interrupted, and the first to sixth variable resistor units are connected in series. Reconfigurable logic circuit configured to perform a programming by varying the direction of the current according to the magnitude of the third power supply voltage and the fourth power supply voltage.

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