KR20090054837A - Programmable logic controller based digital reactor protection system with independent triple redundancy of bistable processor and coincidence processor and initiation circuit with 2/3 voting logic per channel and method thereof - Google Patents

Abstract

A programmable logic controller based digital reactor protection system is provided to increase the stability of a nuclear power plant by preventing the leakage of a radioactive substance and radiation in accident. A digital reactor safeguard system comprises m channels, and each channel comprises 3 groups and an initiation logic circuit. A BP generates a trip signal by comparing input signal value with a predetermined trip set value based on a plurality of sensors. BP transmits the trip signal to CP of the same group within each channel, and the CP outputs the final trip signal among m trip signal and a logic combination of a part trip signal.

Description

PROGRAMMABLE LOGIC CONTROLLER BASED DIGITAL REACTOR PROTECTION SYSTEM WITH INDEPENDENT TRIPLE REDUNDANCY OF BISTABLE PROCESSOR AND COINCIDENCE PROCESSOR AND INITIATION CIRCUIT WITH 2 3 VOTING LOGIC PER CHANNEL AND METHOD THEREOF}

The present invention is a digital reactor protection system using a programmable safety logic controller (PLC), consisting of four channels, for each channel includes a pair of comparative logic processor and simultaneous logic processor in a tripled group Digital reactor protection system and digital reactor protection system for stopping the reactor or mitigating the accident by generating an output from the tripled group as a control signal through an initiation logic circuit having 2/3 voting logic. It relates to a driving method of.

A nuclear power plant usually consists of a system with more than 100 individual functions. These systems are largely divided into a nuclear steam supply system (NSSS) centered on a nuclear reactor, a secondary circulation cooling system that delivers steam to a generator, and a turbine that receives steam from the secondary circulation cooling system and runs a generator. Generator system, and other auxiliary equipment. Looking at the pressurized water reactor-type power plant, which is currently dominated by Korea's nuclear power plants, the primary system centered on nuclear reactors, the secondary system including steam generators, turbines, generators, and condensers, and the engineering safety facility system for accidents It consists of transmission and distribution system, measurement control system, and other auxiliary systems.

In order to monitor the health of each system while operating the nuclear power plant, various types of sensors must be installed in the reactor system, and the signals input from the sensors must be monitored to determine the state of the nuclear power plant. At this time, if there is an abnormality in the system affecting the safety of the reactor during operation of the nuclear power plant or an abnormality in the cooling function in the nuclear steam supply system, such an abnormal state is detected and the reactor stop function is started by the dropping of the control rod. The reactor operating system must be driven to cool the reactor, and the reactor protection system is the actual implementation of this process.

The reactor protection system serves to protect the nuclear reactor, keeping the nuclear power plant safe even if an accident occurs in the nuclear power plant, and preventing radiation and radioactive material from leaking to the outside. Thus, the nuclear reactor protection system plays the most important role in the safety and reliability of nuclear power plants.

For the optimal application of the reactor protection system to the power plant site, it is necessary to implement the reactor protection system with high reliability and high precision, and also to stop the reactor in the event of minor failures inside and outside the reactor protection system. There should be no.

To this end, nuclear power plants usually form a reactor protection system with multiple channels (usually four). When four channels are implemented, each of the four channels receives a plant status signal from a sensor or a device belonging to the channel to determine reactor shutdown or safety device operating conditions, and the reactor protection system includes two out of four channels. In consideration of the determination result from the above channel, when the set condition is satisfied, an operation signal is generated to stop the reactor or operate the safety equipment.

To date, in Korea, only analog reactor protection system or digital reactor protection system that outputs only one judgment result based on single information in one channel is used. Therefore, the reliability of the judgment result output from each channel is very low. It tends not to be high.

For example, although the DPPS (Digital Plant Protection System) used in Uljin Nos. 5 and 6 uses four simultaneous logic processors, the DPPS also outputs only one determination result based on a single information per channel. High reliability is not guaranteed.

The present invention has been made to solve the problems of the prior art as described above, the digital reactor protection system and the digital reactor to develop a digital reactor protection system and a practical logic for realizing a triple independent structure in each channel. Its purpose is to provide a way to implement protection systems.

In addition, the present invention includes three groups each corresponding to a comparative logic processor and a simultaneous logic processor in each channel of the digital reactor protection system, each group using a plurality of trip signals received from the comparison logic processor of another channel The present invention provides a digital reactor protection system and a method for implementing the digital reactor protection system for outputting a final trip signal, and logically combining these final trip signals to accurately determine an abnormality of the digital reactor so that appropriate safety procedures can be performed. Has its purpose.

In addition, the present invention, a digital reactor protection system and the digital reactor that can contribute to the improvement of nuclear power plant safety and reliability, so that even if an accident occurs in the nuclear power plant, the nuclear power plant is kept in a safe state and radiation and radioactive materials are not leaked to the outside. Another purpose is to provide a way to implement the protection system.

In order to achieve the above object and to solve the above-mentioned problems of the prior art, the digital reactor protection system according to an embodiment of the present invention, three comparative processor (Bistable Processor) and three simultaneous logic processor ( A reactor is operated by driving a reactor stop circuit breaker (RTSG) by using (1) a group of triplets and a final trip signal of some of the three final trip signals outputted from the groups. And (2) m channels including an initiation logic circuit for stopping or for operating an engineering safety equipment (ESF) by driving an engineering safety equipment-equipment control system (ESF-CCS). A trip signal is generated based on a plurality of sensor signals indicating the state of the reactor systems, and a trip signal is generated, and the trip signal is generated. The simultaneous logic processor transmits to the concurrent logic process of each group in each channel, and the simultaneous logic processor performs logical combination on some trip signals among the m trip signals received from each of the comparison logic processors of the same group in each channel, and performs the final trip signal. It is characterized by outputting.

In addition, the method for driving the digital reactor protection system according to an embodiment of the present invention, comprising a triple group consisting of three comparative logic processors and three simultaneous logic processors corresponding to each other, for each of m channels step; In the comparison logic processor, a trip signal is generated by comparing an input signal value based on a plurality of sensor signals indicating a state of nuclear reactor systems with a preset trip set value, and the generated trip signal is generated in each of the m channels. Transmitting to the concurrent logic process of the group; In the simultaneous logic processor, outputting a final trip signal by logically combining some of the trip signals among the m trip signals received from each of the comparison logic processors of the same group in each channel; And in a start logic circuit provided in each channel, by using a final trip signal of a part of three final trip signals output from each of the groups to which the respective channels belong, driving a reactor stop circuit breaker (RTSG) to stop the reactor; Or control the engineering safety equipment (ESF) by operating the engineering safety equipment-equipment control system (ESF-CCS).

As described above, in the digital reactor protection system and method according to the present invention, a triple redundancy structure is provided in which three groups including a comparative logic processor and a simultaneous logic processor operate completely independently on each channel of the digital reactor protection system. By employing it, it is possible to contribute to the improvement of nuclear power plant safety and reliability in order to keep the nuclear power plant in a safe state even if an accident occurs in the nuclear power plant and to prevent leakage of radiation and radioactive materials to the outside.

According to the present invention, each channel of the digital reactor protection system includes three groups corresponding to each other in the comparison logic processor and the simultaneous logic processor, and uses a plurality of trip signals received from the comparison logic processor of another channel. Outputs a final trip signal to each group, and provides a method for implementing a digital reactor protection system and a method for implementing the digital reactor protection system by logically combining these final trip signals to accurately determine the abnormality of the digital reactor so that appropriate safety procedures can be performed. can do.

In addition, according to the present invention, the digital reactor protection system and the digital that can contribute to the improvement of nuclear power plant safety and reliability, so that even if an accident occurs in the nuclear power plant, the nuclear power plant is kept in a safe state and radiation and radioactive materials are not leaked to the outside. It is possible to provide a method for implementing a reactor protection system.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings and the contents described in the accompanying drawings, but the present invention is not limited or limited to the embodiments.

1 is a view showing a specific implementation configuration for the digital reactor protection system according to the present invention.

The digital reactor protection system of the present invention includes a group of triplets in which three comparative logic processors (BP) and three simultaneous logic processors (CP) are interconnected, and three final trip signals output from each of the groups of triplets. It includes m channels composed of control circuits for outputting control signals associated with equipment (reactor stop circuit breaker (RTSG), safety equipment-equipment control system (ESF-CCS), etc.) for the protection of the reactor.

The m may be any natural number of one or more, and in the present specification, when the m is composed of four channels, i.

As shown in Figure 1, the digital reactor protection system of the present invention is composed of four (channel A, channel B, channel C, channel D), each channel is a comparative logic processor (BP) -simultaneous logic processor (CP) ) And three groups (group 1, group 2, group 3) composed of pairs, and a control circuit for outputting a control signal using the last trip signal output from each group.

First, the comparison logic processor BP generates a trip signal by comparing an input signal value based on a plurality of sensor signals indicating a state of nuclear reactor systems with a preset trip setting value.

In addition, the comparison logic processor (BP) transmits the generated trip signal to the comparison logic processor (BP), the simultaneous logic processor (CP) of the same group in the same channel, and the simultaneous logic processor (CP) of the same group in the other channel. do. That is, the comparison logic processor BP transmits the generated trip signal to the simultaneous logic processor CP of the same group as the group identified by the comparison logic processor BP in each channel.

FIG. 2 is a diagram illustrating a specific example in which a trip signal generated by the comparative logic processor BP is transmitted to the simultaneous logic processor CP of the same group in each channel.

As shown in Figure 1, each of the channels constituting the digital reactor protection system of the present invention includes a group 1, group 2, group 3 of the triplet. One group is informationally correlated with the same group in another channel. For example, group 1 of channel A is informatively related to group 1 of channel B, group 1 of channel C, and group 1 of channel D. It can be correlated.

As shown in (i) of FIG. 2, it is assumed that the comparative logic processor BP _A1 of Group 1 in the channel A receives a sensor signal from the outside and generates a trip signal accordingly. The BP _A1 is a simultaneous logic processor associated with its group 'Group 1' in each channel, that is, the simultaneous logic processor CPA1 of Group 1 in Channel A, the simultaneous logic processor CP _B1 of Group 1 in Channel B, _and in Channel C. The generated trip signal can be transmitted to the simultaneous logic processor CP _{C1 of the} group 1 and the simultaneous logical processor CP _D1 of the group 1 in the channel D.

Similarly, the simultaneous logic processor BPA1 of group 1 in channel A will receive a trip signal from each of the comparative logic processors associated with its group 'group 1' in each channel.

As shown in ii) of FIG. 2, for example, the simultaneous logic processor CP _{A1 of} group 1 in channel A is a comparative logic processor associated with 'group 1' in each channel, that is, the comparative logic processor BP _A1 of group 1 in channel A _and channel B. A trip signal can be received from the comparative logic processor BP _{B1 of the} group 1 in the group 1, the comparative logic processor BP _C1 of the group 1 in the channel C, _and the comparison logic processor BP _D1 of the group 1 in the channel D.

Referring back to FIG. 1, the simultaneous logic processor CP receiving the trip signal from each of the four intra-channel comparison logic processors BP performs a logical combination on some of the received trip signals and generates a final trip signal. Will print That is, the simultaneous logic processor CP plays a role of generating a final trip signal by logically combining two of four trip signals transmitted from the comparison logic processor BP of the same group in four channels.

The digital reactor protection system of the present invention may further include a switch provided in each group for each channel, and may generate a bypass request signal for the comparative logic processor (BP) using the switch. In an environment equipped with such a switch, the simultaneous logic processor CP is transmitted from the comparison logic processor BP of the same group in m-1 channels except for the comparison logic processor BP from which the bypass request signal is generated. The final trip signal is generated by logical combination of the m-1 trip signals.

For example, when a bypass request signal is generated for the comparative logic processor BP _A1 of the group 1 in the channel A, the simultaneous logic processor CP _A1 of the group 1 in the channel A is the comparative logic processors BP _B1 and BP _C1 except for the BP _{A1 .} 3 (= '4-1') trip signals may be received from BC _D1 , and the final trip signal may be generated by performing a logical combination of these two-fourths.

The initiation logic circuit combines two-thirds of the three final trip signals output from each of the triplet groups, and the reactor stop circuit breaker (RTSG) or the engineering safety equipment-equipment control system (ESF-CCS) according to the logic combination result. Outputs a control signal for driving. In other words, the start logic circuit accurately recognizes the abnormality of the digital reactor through a plurality of check processes, and serves to make the protection processor for the digital reactor according to the recognized information.

In addition, the initiation logic circuit includes a watchdog timer (WDT) for detecting a failure of the CPU of the simultaneous logic processor (CP), and excludes a group related to the simultaneous logic processor detected by the watchdog timer (WDT). Two final trip signals from the remaining groups can be logically combined. Accordingly, the disclosed logic circuit of the present invention can output the control signal using only the reliable last trip signal from the simultaneous logic processor in the steady state, thereby providing an environment for more accurate determination of abnormality for the digital reactor. Can be.

Although not shown in FIG. 1, the digital reactor protection system of the present invention collects operating states for a comparative logic processor (BP) or a simultaneous logic processor (CP) to diagnose an integrity test and an automatic processor (Automatic Test and Interface). Processor may be further included.

Accordingly, according to the present invention, each channel of the digital reactor protection system includes three groups corresponding to each other in the comparison logic processor and the simultaneous logic processor, and receives a plurality of trip signals received from the comparison logic processor of another channel. The final trip signal is output to each group, and the final trip signal may be logically combined to accurately determine whether the digital reactor is abnormal, so that appropriate safety procedures may be performed.

In addition, according to the present invention, even if an accident occurs in the nuclear power plant, it can contribute to improving the safety and reliability of the nuclear power plant so that the nuclear power plant is kept in a safe state and radiation and radioactive materials do not leak to the outside.

3 is a diagram illustrating a configuration of a digital reactor protection system according to an embodiment of the present invention.

As shown in FIG. 3, the digital reactor protection system 300 includes four channels (channels) of a tripled structure in which three comparative logic processors (BPs) and three simultaneous logic processors (CPs) correspond to each channel. A, B, C, D), a remote stop operator module (RSR OM), main control unit operator module (MCR OM). The channel may be configured with N or more (N is a natural number of 3 or more), such as 3, 4, 5, 6, 7, and 8, but a redundancy structure of 4 channels is preferable in consideration of redundancy efficiency and circuit complexity. can do. Each of the four channels is configured to maintain physical / electrical independence between the channels. Remote stop room operator module (RSR OM) and main control room operator module (MCR OM) may serve to monitor and control the operating status of the reactor protection system.

In addition, the digital reactor protection system 300 may be configured in the form of a cabinet that is equipped with a controller and a test-diagnostic man-machine interface (MMI: Man-Machine Interface). At this time, the external system has' Tr. CPC, nuclear reactor trip device (RTSG), and engineering safety equipment-equipment control system (ESF-CCS). Here, Tr may be referred to as PI (Process Instrument).

The four channels (channel A, channel B, channel C, channel D) are each driven completely independently from the input of the sensor signal to the output of the output signal for the sensor signal. The trip signal transmission and reception between the comparative logic processor (BP) and the simultaneous logic processor (CP) is performed through a communication method using a safety data link (SDL). For example, the comparative logic processor BPA1 of group 1 in channel A is generated by the simultaneous logic processors CP _A1 , CP _B1 , CP _C1 and CP _D1 of the same group (group 1) in each channel through the safety data link. The trip signal of each process variable can be transmitted.

Sensor signals for each process variable measured by the sensor include the process inputs of each reactor system, the internal factor values calculated by the Core Protection Calculator (CPC), and the ex-core neutron flux monitoring system (ENFMS). Monitoring system) includes neutron flux output values, and these values are input independently for each channel.

The sensor signals input at the input terminal are transmitted to the comparison logic processor BP. The comparison logic processor BP compares a trip set value preset with the received sensor signal, and generates a trip signal for a related variable when the sensor signal exceeds the trip set value as a result of the comparison. do. In addition, the comparison logic processor BP generates the generated trip signal in each channel (four channels) in a simultaneous logic processor (CP of channel A, CP of channel B) associated with the group identified by the comparison logic processor BP. , CP of channel C and CP of channel D) are transmitted through the safety data link.

The simultaneous logic processor (CP) receives trip signals corresponding to the number of channels (e.g., four) from the comparison logic processor BP belonging to the same channel and the comparison logic processors BP belonging to another channel (three channels). do. In addition, the simultaneous logic processor (CP) performs a 2/4 logic combination by taking a portion, for example, two of the four trip signals received, and satisfies the logic result of the performed 2/4 logic combination, that is, If the logical value is the same from two of the four channels, the final trip signal is generated and transmitted to the start logic circuit.

When the initiation logic circuit receives the final trip signal from the simultaneous logic processor (CP), i.e., each of the group of triplets included in the channel, the starting logic circuit cuts off the control rod power through the reactor trip switch (RTSG) to drop the control rod. The reactor is shut down and the reactor is cooled by running the Engineered Safety Features-Component Control System (ESF-CCS).

Hereinafter, a detailed configuration of each channel will be described with reference to FIG. 4.

4 is a view for explaining the configuration of a channel according to an embodiment of the present invention.

Each channel (channels A, B, C, and D) of the digital reactor protection system 300 is a comparative logic processor 'BP ₁ , BP ₂ , BP ₃ ' of the triplex structure, and a simultaneous logic processor 'CP ₁ of the triplex structure. , CP ₂ , CP ₃ ′, and a start logic circuit with 2/3 start logic.

The comparative logic processors 'BP ₁ , BP ₂ , BP ₃ ' and the simultaneous logic processors 'CP ₁ , CP ₂ , CP ₃ ' use a digital controller such as a programmable logic controller (PLC) or an ASIC. The digital controller includes an input / output module for processing analog and digital signals, a CPU module for performing protection logic, a communication module for processing data communication, and a power module.

The digital reactor protection system 200 satisfies the safety class (Class 1E) and is classified into seismic category I.

For the channel A 4, the group 1 is compared to the logical processor BP _A1 and co-processor logic and CP _{A1 mutually} corresponding, similarly to Group 2 'BP _A2 -CP _A2 ', group 3 is' BP _A3 ' -CP _A3 '.

Groups 1 to 3 in the channel are completely separated from the input module to the output module, and share sensor signals for each process variable or predetermined input signals for each trip variable. That is, only the processors belonging to each group are interconnected, and the comparative logic processors and the concurrent logic processors in different groups operate independently. The output of the comparative logic processor may be transmitted to the same group simultaneous logic processor of the same channel and other channels through the safety data link (SDL).

For example, the output of the comparative logic processor BP _A1 of group 1 in channel A, together with the simultaneous logic processor CPA1 of group 1 in channel A, is the simultaneous logic processors' CP _B1 , CP _{C1 in} group B in channels B, C, and D. , CP _D1 'can be delivered to each.

The comparison logic processors BP ₁ , BP ₂ , and BP ₃ acquire a signal value from the sensor signals converted into a digital signal through an input signal processing processor, compare the obtained signal value with a trip setting value, and then trip or reserve a trip value. Determine the trip condition.

Comparative logic processors BP ₁ , BP ₂ , BP ₃ determine a trip set point, the trip set point being a fixed set point, a manual reset type variable set point, and a ratio limited variable set point.

In addition, the comparison logic processors BP ₁ , BP ₂ , and BP ₃ generate channel trips when the input signal value exceeds the trip set value or decreases below the trip set value. That is, the comparison logic processors BP ₁ , BP ₂ , and BP ₃ determine a channel trip (pre-bit trip) with respect to the corresponding sensor signal which is a digital input trip variable from the core protection calculator CPC. .

The comparative logic processors BP ₁ , BP ₂ and BP ₃ receive a request for bypass of each channel from the operator through a switch on the front of each channel when the signal value is within the allowable range of the trip setpoint. Initiate a bypass. When operation bypass is entered, the comparative logic trip and the pre-trip for the corresponding trip variables (log output trip and pressurized base pressure trip) are bypassed and invalidated. When the process value is out of the allowable range, the started operation bypass is automatically removed.

In addition, the comparative logic processors BP ₁ , BP ₂ , and BP ₃ are the same group of simultaneous logic processors (CP) in the four channels (magnetic channel and other channels) through the safety data link (SDL). Transmits status signals such as the pre-rip, bypass request and bypass and beat signals. In addition, the comparison logic processors BP ₁ , BP ₂ , and BP _{3 transmit} the state information and the operation information to the remote stop operator module (RSR OM) and main control room operator through an inter-channel network (ICN). Module (MCR OM), cabinet operator module (COM), and automatic test and associated processor (ATIP).

Simultaneous logic processors CP ₁ , CP ₂ , and CP ₃ generate a final trip signal by logically combining two-four trip signals output from the corresponding logical processors in the four channels in the four channels. Simultaneous logic processors CP ₁ , CP ₂ , and CP ₃ transmit the generated final trip signal to the start logic circuit IC. Simultaneous Logic Processors CP ₁ , CP ₂ , and CP ₃ transmit the operation information such as trip state, trip channel bypass state, etc. MCR OM), cabinet operator module (COM), and automatic test and associated processor (ATIP).

According to the present invention, it is necessary to bypass the failure or the output of the channel under test for the maintenance and testing of the comparative logic processor. To this end, the simultaneous logic processors CP ₁ , CP ₂ , CP ₃ provide a means for bypassing individual trip variables and all channel bypass trap channels. The individual trip variable bypass bypasses only one channel for one trip variable, and a variable to which a trip channel bypass (TCB) has already been applied may ignore a trip channel request of another channel. At this time, trip channel bypass is allowed for other variables in one channel. If a trip channel request for the same variable is input in two or more channels at the same time, the priority is given in the order of A, B, C, and D channels.

The all-channel bypass (ACB) may bypass one channel as a whole, and bypassing two or more channels at the same time is prohibited. The full channel bypass is initiated when a bypass is required for a channel to be bypassed in three or more channels. That is, in order to initiate full channel bypass of channel A, all channel bypass for channel A must be input in three or more channels among four channels A, B, C, and D.

In addition, the simultaneous logic processors CP ₁ , CP ₂ , and CP ₃ may perform 2/4 simultaneous logic on four trip signals received from the four-channel comparative logic processors BP ₁ , BP ₂ , and BP ₃ . Perform For example, if there is a fault in the process variable input and a trip channel bypass exists for a variable, the simultaneous logic processors CP ₁ , CP ₂ , CP ₃ ignore the bypass channel for that variable and the remaining three channels. If two-thirds of the logic is satisfied in the signal, a trip occurs.

The all-channel bypass bypasses only the comparative logic processor, and there is no method of blocking the output signal in an unavailable state of the output module of the concurrent logic processor, such as a failure or testing of the concurrent logic processor. The output of each channel produces the final reactor stop or safety device operation signal of the channel by 1/2 logic, so even when maintenance or failure of the simultaneous logic processor, the above operation signal is stopped / operated by the fail safe design. The signal is generated on that channel. Another optional package (B-type) according to the present invention can bypass (overpass) a simultaneous logic processor that is failing or under maintenance in a tripled channel. At this time, it is configured as an interworking structure so as not to bypass the two simultaneous logic processors in only one channel.

Simultaneous logic processors have three digital output cards needed to generate a final trip signal and send it to the start logic circuit by two-fourth logic combination, and one digital relay output module to drive the watchdog timer. The three digital output cards output the same result, which is sent to the relay contacts of the starting logic circuit.

The Initiation Logic Circuit consists of three watchdog timers, an optical transmitter (ESFS), a relay coil, a variable capacitor, a diode and a power supply. More specifically, the start logic circuit is characterized in that the start using the watch dog timer in series to start at the time of CPU failure of the simultaneous logic processor.

The initiation logic circuit receives the output signals from the simultaneous logic processors of each group to stop the reactor through the reactor stop circuit breaker (RTSG) or operate the engineering safety equipment through the engineering safety equipment-equipment control system (ESF-CCS). The initiating logic circuit implements voting three groups of simultaneous logic processor outputs with 2/3 logic. The output of the reactor protection system initiation logic circuit is connected to the reactor stop circuit breaker (RTSG) of the corresponding channel through the hard wire, and the output of the engineering safety equipment-device control system (ESF-CCS) initiation logic circuit is connected to the engineering safety equipment through the optical cable. -Device control system Connects to the group controller of each division.

The watchdog timer monitors the pulsation signals of the simultaneous logic processors, and if an error occurs in the pulsation signal, the start logic circuit is opened to open the reactor stop circuit breaker (RTSG) and the engineering safety equipment-device control system (ESF-CCS). To generate a control signal for

The start logic circuit can generate control signals for reactor shutdown, engineering safety equipment operation and prohibiting control rod withdrawal, depending on the conditions of the input variables. The control signal is realized by de-energized the relay coil being operated. Types of the control signals include: Under Voltage Reactor Stop, Shunt Reactor Stop, Safety Injection Start, Main Steam Sequestration Start, Containment Container Containment Start, Containment Container Spray Start, First Auxiliary Water Supply Start, Second Auxiliary Water Supply Start Start, control rod withdrawal operation.

The Automatic Test and Interface Processor (ATIP) tests and monitors the correct operation of the functions of the intra- and other channels of comparative and simultaneous logic processors. The automatic test and associated processor (ATIP) receives the state of the variable value, set value, trip / pre-trip state and operation bypass from the comparison logic processor through the intra-channel data network (ICDN). Watch. In addition, the automatic test and associated processor (ATIP) receives the status of trip, trip channel bypass, and all channel bypass from the simultaneous logic processor through the ICDN and monitors the concurrent logic processor.

The automatic test and associated processor (ATIP) is an engineering safety facility-equipment control system (ETF) through the engineering safety facility-device control system (ETIP, ESF-CCS Test & Interface Processor) and the safety data link (SDL). It receives the state information of the CCS, and transmits it to the operator module (OM). In addition, it detects and monitors the connection status (current flow) of each leg of the reactor stop circuit breaker (RTSG) and monitors the internal devices such as power supply, temperature detector, cabinet door open signal, and start logic circuit. Obtain and monitor the operating status of the system.

In addition, the automatic test and associated processor (ATIP) provides the cabinet operator module (COM) and the information processing system (IPS) the trouble state of the digital reactor protection system. Trouble alarms in the digital reactor protection system include cabinet temperature anomalies, hardware failures, and test errors. The ATIP must provide the CPC Test Enable output signal to the CPC when both Low DNBR and High LPD are bypassed in the channel. The automatic test and associated processor (ATIP) determines the bypass status when the concurrent logic processor in the cabinet is a trip channel bypass for both of the above variables.

The automatic test and associated processor (ATIP) shall have a manual initiated automatic test function to verify that the comparative and concurrent logic processors perform correctly. The automatic test function can be performed manually or automatically by the operator if necessary. To this end, the automatic test and associated processor (ATIP) generates a test start signal for the automatic test, and transmits the test start signal to the comparative logic processor and the simultaneous logic processor, and receives the results to check the soundness.

The automatic test and associated processor (ATIP) generates a pulsating signal and sends it to the watchdog timer of the starting logic circuit through the digital output module to ensure soundness. In addition, ATIP transmits the heartbeat signal through the channel data communication network (ICDN) to monitor the operation status of the IN and other channels.

The operator linkage of the digital reactor protection system consists of a remote stop room operator module (RSR OM), main control room operator module (MCR OM) and cabinet operator module (COM). Here, the Remote Shutdown Room Operator Module (RSR OM) and the Main Control Room Operator Module (MCR OM) operate reactor operation such as bypass operation and manual reset of the set value. Cabinet Operator Module (COM) performs all monitoring and manipulation for preventive maintenance and repair. These signals are initiated through a hardware switch and transmitted via hardwires to the associated comparative or concurrent logic processor.

In the cabinet operator module (COM), Trip-Channel Bypass (TCB), All-Channel Bypass (ACB), Reactor Protection System Stop Circuit Breaker Reset (RPS Trip Circuit Breaker Reset), The reset of the engineering safety equipment (ESF) activation signal is initiated via a hardware switch. The cabinet operator module (COM) consists of a touch screen, a computer, a trackball, a keyboard, and a manual control panel. One cabinet is installed at the front of the cabinet. The cabinet operator module (COM) is connected to the comparative logic processor, simultaneous logic processor, automatic test and link processor (ATIP) through the channel internal communication network (ICN), and the operation status of the reactor protection system (IPS: Information Processing system). It is used as a gateway for transmission to the system.

The digital reactor protection system has three types of data communication networks for signal transmission between each processor module. The SDL sends the comparative logic processor outputs to the concurrent logic processor and uses unidirectional and deterministic protocols. The communication between the automatic test and associated processor (ATIP) and the engineering safety equipment-device control system (ESF-CCS) test and associated processor (ETIP) is also made up of SDL. The channel internal communication network (ICN) is used to exchange information between the comparative logic processor, the simultaneous logic processor, the automatic test and association processor (ATIP), and the operator module (OM) in each channel. Inter-channel data communication network (ICDN) is a communication network that connects channels to each other, and exchanges operation information between each channel's automatic test and associated processor (ATIP), and performs automatic tests and tests with Qualified Indication & Alarm System (QIAS). Perform communication between ATIPs.

5 is a flowchart illustrating a method of driving a digital reactor protection system according to an embodiment of the present invention.

First, the digital reactor protection system of the present invention configures a triplet group for three channels, each of which comprises three comparative logic processors BP and three simultaneous logic processors CP, respectively (S510). .

The m may be any natural number of one or more, and in the present specification, a method of driving the digital reactor protection system according to the present invention will be described assuming that m is composed of four channels, i.e., for convenience of understanding the invention. .

In step S510, the digital reactor protection system comprises four (channel A, channel B, channel) groups comprising three groups (group 1, group 2, group 3) consisting of pairs of comparative logic processor (BP) -simultaneous logic processors (CP). C, channel D).

In addition, the digital reactor protection system generates a trip signal by comparing an input signal value with a pre-stored trip set value based on a plurality of sensor signals indicating the state of the reactor systems through a comparative logic processor (BP) of each channel in each channel. (S520).

Subsequently, the digital reactor protection system transmits the trip signal generated by the comparative logic processor BP to the simultaneous logic processor CP of the same group in the same channel, and the simultaneous logic of the same group in the other channel. The processor transmits the signal to the processor CP (S530). That is, the comparison logic processor BP transfers the generated trip signal to the simultaneous logic processor CP of the same group as the group identified by the comparison logic processor BP in each channel.

For example, it is assumed that the comparative logic processor BP _A1 of the group 1 in the channel A receives a sensor signal from the outside and generates a trip signal accordingly. The BP _A1 is a simultaneous logic processor associated with its group 'Group 1' in each channel, that is, the simultaneous logic processor CPA1 of Group 1 in Channel A, the simultaneous logic processor CP _B1 of Group 1 in Channel B, _and in Channel C. The generated trip signal can be transmitted to the simultaneous logic processor CP _{C1 of the} group 1 and the simultaneous logic processor CP _D1 of the group 1 in the channel D.

In addition, the digital reactor protection system logically combines a part of trip signals among the received trip signals through a simultaneous logic processor (CP) that receives a trip signal from each of the four intra-channel comparative logic processors (BP). The last trip signal is output (S540). That is, the simultaneous logic processor CP generates a final trip signal by logically combining two of four trip signals transmitted from the comparison logic processor BP of the same group in four channels, respectively.

In step S540, the digital reactor protection system may identify whether a bypass request signal for the comparative logic processor BP is generated, and the simultaneous logic processor CP of the digital reactor protection system may compare the generated bypass signal. The final trip signal is generated by logically combining the m-1 trip signals transmitted from the comparison logic processor BP of the same group in the m-1 channels except the logic processor BP.

For example, when a bypass request signal is generated for the comparative logic processor BP _A1 of the group 1 in the channel A, the simultaneous logic processor CP _A1 of the group 1 in the channel A is the comparative logic processors BP _B1 and BP _C1 except for the BP _{A1 .} 3 (= '4-1') trip signals may be received from BC _D1 , and the final trip signal may be generated by performing a logical combination of these two-fourths.

Next, the digital reactor protection system logically combines the three final trip signals output from each of the triplet groups by two-thirds, and depending on the result of the logical combination, a reactor stop circuit breaker (RTSG) or an engineering safety equipment-device control system. A control signal for driving the (ESF-CCS) is output (S550). That is, the start logic circuit accurately recognizes the abnormality of the digital reactor through a plurality of check processes, and performs a protection processor for the digital reactor according to the recognized information.

In addition, the start logic circuit of the digital reactor protection system in step S550 except for the group associated with the simultaneous logic processor detected by the watchdog timer (WDT) for detecting a failure of the CPU of the simultaneous logic processor (CP). The two final trip signals output from the 2/3 logic combination can be performed. Accordingly, the disclosed logic circuit of the present invention can output the control signal using only the reliable last trip signal from the simultaneous logic processor in the steady state, thereby providing an environment for more accurate determination of abnormality for the digital reactor. Can be.

Although not shown in FIG. 5, the method for driving the digital reactor protection system of the present invention may further include a process of diagnosing health by collecting operating states for a comparative logic processor (BP) or a simultaneous logic processor (CP). .

Accordingly, according to the present invention, each channel of the digital reactor protection system includes three groups corresponding to each other in the comparison logic processor and the simultaneous logic processor, and receives a plurality of trip signals received from the comparison logic processor of another channel. The final trip signal is output to each group, and the final trip signal may be logically combined to accurately determine whether the digital reactor is abnormal, so that appropriate safety procedures may be performed.

In addition, according to the present invention, even if an accident occurs in the nuclear power plant, it can contribute to improving the safety and reliability of the nuclear power plant so that the nuclear power plant is kept in a safe state and radiation and radioactive materials do not leak to the outside.

The triple method of the digital reactor protection system according to the present invention can be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

1 is a view showing a specific implementation configuration for the digital reactor protection system according to the present invention.

FIG. 2 is a diagram illustrating a specific example in which a trip signal generated by the comparative logic processor BP is transmitted to the simultaneous logic processor CP of the same group in each channel.

3 is a diagram illustrating a configuration of a digital reactor protection system according to an embodiment of the present invention.

4 is a view for explaining the configuration of a channel according to an embodiment of the present invention.

5 is a flowchart illustrating a method of driving a digital reactor protection system according to an embodiment of the present invention.

Claims (13)

In the digital reactor protection system, (1) a group of triplexes that comprise three comparative logic processors and three concurrent logic processors, and a final trip of some of the three final trip signals output from each of the groups; (2) Initiation logic using the signal to drive the reactor stop circuit breaker (RTSG) to stop the reactor or to operate the engineering safety equipment-equipment control system (ESF-CCS) to operate the engineering safety equipment (ESF). Contains m channels containing circuitry, The comparison logic processor, A trip signal is generated by comparing the input signal value based on a plurality of sensor signals indicating the state of the reactor systems with a pre-stored trip setting value, and transmitting the generated trip signal to a simultaneous logic process of the same group in each channel. The simultaneous logic processor, And outputting the final trip signal by logically combining some of the trip signals among the m trip signals received from each of the comparative logic processors of the same group in each channel. The method of claim 1, The start logic circuit, Two-third logical combination of the three final trip signals output from each of the triplet groups, and driving the reactor stop circuit breaker (RTSG) or the engineering safety equipment-equipment control system (ESF-CCS) according to the logic combination result. Digital reactor protection system, characterized in that for outputting a control signal for. The method of claim 1, If m is '4', The simultaneous logic processor, And digitally combining two of the four trip signals transmitted from the comparative logic processors of the same group in the four channels to generate the final trip signal. The method of claim 1, The start logic circuit, A watchdog timer (WDT) for detecting a failure of the CPU of the simultaneous logic processor; 2/3 logical combination of two final trip signals output from the remaining groups except the group associated with the simultaneous logic processor detected by the watchdog timer (WDT), And a control signal for driving the reactor stop circuit breaker (RTSG) or the engineering safety equipment-equipment control system (ESF-CCS) according to the logic combination result. The method of claim 1, The channel is, A switch provided for each group, the switch generating a bypass request signal for the comparative logic processor, The simultaneous logic processor, The final trip signal may be generated by logically combining m-1 trip signals transmitted from a comparison logic processor of the same group in m-1 channels, except for the comparison logic processor in which the bypass request signal is generated. Reactor Protection System. The method of claim 1, Automatic Test and Interface Processor for collecting the operating state of the comparative logic processor or the simultaneous logic processor to diagnose the health (Automatic Test and Interface Processor) Digital reactor protection system further comprises. Constructing a group of triplets for three channels, the three comparison logic processors and the three simultaneous logic processors corresponding to each other; In the comparison logic processor, a trip signal is generated by comparing an input signal value based on a plurality of sensor signals indicating a state of nuclear reactor systems with a preset trip set value, and the generated trip signal is generated in each of the m channels. Transmitting to the concurrent logic process of the group; In the simultaneous logic processor, outputting a final trip signal by logically combining some of the trip signals among the m trip signals received from each of the comparison logic processors of the same group in each channel; And In the starting logic circuit provided in each of the channels, the reactor stop circuit breaker (RTSG) is used to stop the reactor by using a final trip signal of a part of three final trip signals output from each of the groups to which the respective groups belong, or Control phase to operate engineering safety equipment (ESF-CCS) by operating engineering safety equipment (ESF-CCS) Method of driving a digital reactor protection system comprising a. The method of claim 7, wherein The control step, Two-third logical combination of the three final trip signals output from each of the triplet groups, and driving the reactor stop circuit breaker (RTSG) or the engineering safety equipment-equipment control system (ESF-CCS) according to the logic combination result. Outputting a control signal for Method of driving a digital reactor protection system comprising a. The method of claim 7, wherein If m is '4', The step of outputting the last trip signal, Generating the final trip signal by logically combining two-four (4) trip signals transmitted from the comparative logic processors of the same group in four channels. Method of driving a digital reactor protection system comprising a. The method of claim 7, wherein The control step, Logically combining two final trip signals output from groups other than the group associated with the failure-detected simultaneous logic processor by a watchdog timer (WDT) for detecting a failure of the CPU of the simultaneous logic processor; And Outputting a control signal for driving the reactor stop circuit breaker (RTSG) or the engineering safety equipment-equipment control system (ESF-CCS) according to the logical combination result; Method of driving a digital reactor protection system comprising a. The method of claim 7, wherein Identifying whether a bypass request signal for the comparative logic processor is generated; The step of outputting the last trip signal, Generating the final trip signal by logically combining m-1 trip signals transmitted from a comparison logic processor of the same group in m-1 channels, except for the comparison logic processor in which the bypass request signal is generated. Method of driving a digital reactor protection system comprising a. The method of claim 7, wherein Diagnosing health by collecting an operating state of the comparative logic processor or the simultaneous logic processor; Method of driving a digital reactor protection system further comprising. A computer-readable recording medium having recorded thereon a program for performing the method of any one of claims 7 to 12.

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