KR20090053163A - Flash memory control apparatus and method sharing control signal - Google Patents

Abstract

A memory control apparatus and method are provided. The memory control apparatus of the present invention includes a plurality of flash memory units and an interface portion connected to the plurality of flash memory units via a common input / output bus and a common control signal line, wherein the interface portion is the common input / output An identification code for identifying each of the plurality of flash memory units is transmitted via a bus, and only a first flash memory unit corresponding to the transmitted identification code of the flash memory units corresponds to the common control signal. In this case, the number of control signal lines can be reduced for a plurality of flash memory units.

Flash memory, interface, common control signal

Description

Flash memory control device and method for sharing control signals {FLASH MEMORY CONTROL APPARATUS AND METHOD SHARING CONTROL SIGNAL}

The present invention relates to an interface method between a flash memory device and a flash memory, and more particularly, to a flash memory interface for interfacing a flash memory of a plurality of flash memories or a multi-die package structure and a method of using the same. This study was conducted as part of the core technology development project for IT new growth engines of the Ministry of Information and Communication and the ICT Research Promotion Agency. [2006-S-040-01, Development of Embedded Memory Software Technology based on Flash Memory]

Flash memory generally uses a 48-pin thin small outline package 1 (TSOP1) type and a 52-pin tilted land grid array (TLGA) type package. A plurality of control signals, 8-bit or 16 It has a bit I / O signal, Vcc and Vss pins, and a plurality of NC (No Connection) pins.

As semiconductor technology and its processes progress gradually, the amount of memory that can be embedded per unit chip is increasing, but in order to overcome the capacity limitation of current technology, stacking and embedding a plurality of dies in a single package is required. Multi-die packaging technology has been proposed and widely used. This multi-die package chip can overcome the limitations of memory technology by implementing a plurality of chips that share external leads and implement high integrated capacity. Since a plurality of chips can be embedded in one package, a printed circuit board (PCB) ) Has the advantage of reducing the area of the package occupies.

In the case of a multi-die package chip, a plurality of stacked chips operate independently of each other although they exist in a single package, and each chip has different CE signal lines and RnB signal lines. To access a specific chip in a package, an external host applies 0 to a Chip Enable (CE) signal line corresponding to a desired chip, and then commands the chip using other control signals and I / O signals.

As described above, in the case of the conventional flash interface methods, as the number of NAND flash memory chips to be controlled increases, the number of CE signal lines and RnB signal lines as many as the number of chips must be added to the interface device. In addition, in the case of using a multi-die package chip, the number of independent CE leads and RnB leads must be as many as the number of stacked chips, so that the lead of the external package may be insufficient when a large number of chips are stacked. In addition, as many CE signals and RnB signals as the number of stacked chips must be further connected to the flash interface device.

Therefore, when developing a flash interface device for the development of an application using a plurality of NAND flash memory chips, such as a large-capacity solid-state disk (SSD) using a NAND flash memory, the size of the chip with the built-in interface device increases. The number of patterns on the printed circuit board for connecting the flash memory chip with each other must be increased, thereby increasing the system design cost.

In the present specification, a flash memory control apparatus and method capable of efficiently controlling a plurality of flash memories without increasing the cost are proposed. In addition, in the present specification, a flash memory control apparatus and method for simplifying the configuration of hardware are proposed.

The present invention has been made to solve the problems of the prior art as described above, in the interface device for controlling a plurality of flash memory or the interface device for controlling a NAND flash memory of a multi-die package structure, a plurality of flash memory By sharing these control signals, it is an object to provide an interface which does not need to increase the number of control signals even if the number of controlled flash memories is increased.

It is also an object of the present invention to provide a flash memory interface device and method for reducing the number of control signals while maintaining compatibility with conventional flash interface devices.

In order to achieve the object of the present invention as described above, the flash memory control apparatus according to an aspect of the present invention comprises a plurality of flash memory units, and a plurality of flash memory via a common input and output bus and a common control signal line An interface unit coupled to the units, wherein the interface unit transmits an identification code identifying each of the plurality of flash memory units via the common input / output bus, and to the transmitted identification code of the flash memory units. Only the corresponding first flash memory unit operates in response to the common control signal.

In addition, according to another aspect of the present invention, a memory control method for controlling a plurality of flash memory units using a common input / output bus and a common control signal line includes a plurality of flash memories with identification codes via a common input / output bus. Transmitting to the units, receiving a confirmation message from the first flash memory unit corresponding to the identification code, and transmitting a command and an address to the first flash memory unit via the common input / output bus. It is characterized by including.

According to the present invention, since a plurality of flash memories share a control signal, it is possible to implement an interface that does not need to increase the number of control signals even if the number of controlled flash memories is increased.

According to the present invention, it is possible to implement a flash memory interface device and method for reducing the number of control signals while maintaining compatibility with a conventional flash interface device.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

Flash memory generally uses a 48-pin thin small outline package 1 (TSOP1) type and a 52-pin tilted land grid array (TLGA) type package. A plurality of control signals, 8-bit or 16 It has a bit I / O signal, Vcc and Vss pins, and a plurality of NC (No Connection) pins.

1 is a diagram illustrating an example of a flash memory system 100.

Referring to FIG. 1, the flash memory system 100 includes a flash interface device 110 and a NAND flash memory 120.

Address Latch Enable (ALE), Command Latch Enable (CLE), Chip Enable (CE), Read Enable (RE), Write Enable (WE), Read / Busy (RNB) control signals of the flash interface device 110 and I The / O (Input / Output) signal is connected to the NAND flash 120.

In order for a host to access data stored in the NAND flash 120, the host must pass through the flash interface device 110.

In the flash memory system 100, signals for addresses, commands, and data are not separated, and addresses, commands, and data are transmitted using I / O signals. The flash interface device 110 uses the ALE and CLE signals to specify which type of I / O signal is transmitted among an address, a command, and data.

2 is a timing diagram illustrating an operation of a plurality of control signals and an I / O signal of the flash memory system 100.

Referring to FIG. 2, when 1 is applied as an ALE signal, the NAND flash memory 120 recognizes the transferred I / O signal as an address. The NAND flash memory 120 recognizes the I / O signal as a command when 1 is applied as the CLE signal. The NAND flash memory 120 recognizes the transferred I / O signal as data when 0 is applied as both the ALE signal and the CLE signal.

At this time, the NAND flash memory 120 recognizes the address, command, and data transmitted as valid only when the CE (Chip Enable) signal is zero. The NAND flash memory 120 transmits the current state to the flash interface device 110 using an RnB (Ready / Busy) signal.

3 is a diagram illustrating an example of a flash memory system 300.

Referring to FIG. 3, the flash memory system 300 includes a flash interface device 310 and includes n NAND flash memories.

The flash interface device 310 controls n number of NAND flash memories.

In the flash memory system 300, a CE signal line and an RnB signal line are provided for each of the n NAND flash memories.

In the flash memory system 300, control signals ALE, CLE, RE, and WE that instruct an operation are shared by n NAND flash memories. The I / O signal is also shared by n NAND flashes. However, the CE signal and the RnB signal are provided independently for each of the NAND flash memories.

For example, the NAND flash memory 0 320 is provided with the CE [0] and RnB [0] signals, and the NAND flash memory 1 330 is provided with the CE [1] and RnB [1] signals. Similarly, the NAND flash memory n 340 is provided with the CE [n] and RnB [n] signals.

4 is a diagram illustrating an example of a multi-die package of a flash memory.

Referring to FIG. 4, the multi-die package includes Die 1 410, Die 2 420, Die 3 430, and Die 4 440.

According to an embodiment, a multi-die package to which a stacking technique is applied, in which one package includes six dies, may be implemented.

As semiconductor technology and its processes progress gradually, the amount of memory that can be embedded per unit chip is increasing, but in order to overcome the capacity limitation of current technology, stacking and embedding a plurality of dies in a single package is required. Multi-die packaging technology has been proposed and widely used. The multi-die package chip can implement a high integrated capacity by embedding a plurality of chips that share external leads, and a plurality of chips can be embedded in one package, so that the package is relatively printed circuit board (PCB). It can reduce the area occupied by.

In the case of a multi-die package chip, a plurality of stacked chips operate independently of each other although they exist in a single package, and each chip has different CE signal lines and RnB signal lines. Therefore, as in the case of controlling the plurality of flash memory units described above, in order to access a specific chip in the package, 0 is applied to the CE signal line corresponding to the selected chip to activate the selected chip, and then control signals and I / O signals are applied. Command the active chip.

However, the configuration of providing the CE signal line and the RnB signal line for each chip requires as many CE signal lines and RnB signal lines as the number of chips as the number of controlled flash memory chips increases. Therefore, the increasing number of CE signal lines and RnB signal lines has a problem of increasing the hardware complexity of the interface.

In addition, since the multi-die package chip requires independent CE leads and RnB leads as many as the number of chips stacked, the lead supplied to the outside of the package may be insufficient. If the package requires multiple leads, this causes an increase in the circumferential length of the package and thus an increase in the area of the package.

In addition, since the number of leads connected to hosts outside the package increases, the complexity of the connection increases.

For applications that use multiple NAND flash memory chips, such as large-capacity solid-state disks (SSDs) using NAND flash memory, which are increasing in recent years, not only the size of the chip having a built-in flash interface device is increased, As the number of patterns of printed circuit boards for connecting flash memory chips increases, the system design cost increases accordingly.

6 is a diagram illustrating a memory control device according to an embodiment of the present invention.

Referring to FIG. 6, the memory control device includes a flash interface device 610 and sixteen NAND flash memory units. According to an embodiment, the memory control device may include N flash memory units.

The flash interface device 610 controls 16 NAND flash memory units via I / O signal buses, ALE, CLE, RE, WE signal buses, CE signals, and RnB signal lines shared by all NAND flash memory units. .

An operation of controlling the NAND flash memory units by the flash interface device 610 will be described with reference to FIG. 5.

5 is a timing diagram illustrating a read operation of the memory control apparatus according to an embodiment of the present invention.

Referring to FIG. 5, CE, CLE, ALE, RnB, and I / O signals commonly applied to a plurality of NAND flash memory units are shown.

The flash interface device 610 applies "1" to the CE signal when none of the 16 NAND flash memory units are selected. When one of the NAND flash memory units is selected, the flash interface device 610 applies “0” to the CE signal, and identifies a division code (or identification code) corresponding to the selected NAND flash memory unit on the I / O bus line. Apply.

The flash interface device 610 applies a division code to the I / O bus line while the combination of the CLE and ALE signals indicates the division code transmission mode.

In the memory control apparatus, when the CLE signal is "1" and the ALE signal is "0", the combination of the CLE signal and the ALE signal indicates the command transfer mode, when the CLE signal is "0" and the ALE signal is "1". The combination of, CLE and ALE signals indicates an address transfer mode.

In the memory control apparatus, when both the CLE signal and the ALE signal are "1", the combination of the CLE signal and the ALE signal indicates the division code transmission mode. According to an embodiment, the division code transmission mode may be represented by a combination of a plurality of control signals. According to an embodiment, the division code transmission mode may be represented as not conventionally used among a combination of a plurality of control signals.

If the CE signal is "0" and a discrimination code is applied to the I / O bus, the memory unit corresponding to the selected discrimination code among the NAND flash memory units is activated, and the activated memory unit corresponds to a control signal which is subsequently received. To work.

The flash interface device 610 applies "1" to the CLE signal, "0" to the ALE signal, and applies a command to the I / O bus. The activated memory unit recognizes that the signal received via the I / O bus is a command according to the combination of the CLE signal and the ALE signal.

The flash interface device 610 applies "0" to the CLE signal, "1" to the ALE signal, and applies an address to the I / O bus. The activated memory unit recognizes that the signal received via the I / O bus is an address according to the combination of the CLE signal and the ALE signal.

In the memory control apparatus, when " 0 " is applied to both the CLE signal and the ALE signal, the combination of the CLE signal and the ALE signal can indicate the data transfer mode.

The activated memory unit applies "0" to the RnB signal while performing the received command to indicate that the current state is busy. When the received command is completed, the activated memory unit applies a "1" to the RnB signal to indicate that the current state is ready.

According to an embodiment, the value "1" of the RnB signal may indicate a busy state, and the value "0" of the RnB signal may indicate a ready state.

The flash interface device 610 determines the current state of the activated memory unit according to the value of the RnB signal.

Only the memory unit activated corresponding to the identification code may apply the RnB signal. Memory units other than the activated memory unit cannot change the value of the RnB signal.

The activated memory unit changes the value of the RnB signal to a value corresponding to the ready state when the received command is completed and ends the sequence.

When the value of the RnB signal is changed to a value corresponding to the ready state, the flash interface device 610 starts to perform the next command.

Referring again to FIG. 6, each of the NAND flash memory units includes a discrimination code identification circuit capable of determining a discrimination code received via an I / O bus.

The fifteen NAND flash memory units form a discrimination code identification circuit 621 using a power terminal and a ground terminal on an unconnected (N.C.) pin. In the memory control apparatus, since the number of NAND flash memory units is 16, a 4-bit discrimination code is required.

Memory unit 0 620 has four N.C. All pins are connected to the ground terminal to implement the identification circuit 621 corresponding to the identification code "0000". Memory unit 0 620 is activated only when the received discrimination code is "0000" and may occupy the RnB signal line.

Memory unit 1 630 is one N.C. Connect the pin to the power supply terminal and the remaining three N.C. The pin is connected to the ground terminal to implement the identification circuit 631 corresponding to the identification code "0001". The memory unit 1 630 may be activated only when the received discrimination code is “0001” and may occupy the RnB signal line.

Memory unit 5 640 has two N.C. Connect the pin to the ground terminal and connect the remaining two N.C. The pin is connected to the power supply terminal to implement the identification circuit 641 corresponding to the identification code "0000". The memory unit 5 640 is activated only when the received discrimination code is "0101" and may occupy the RnB signal line.

Memory unit 15 (650) has four N.C. The pin is connected to a power supply terminal to implement an identification circuit 651 corresponding to the identification code "1111". The memory unit 15 650 is activated only when the received discrimination code is "1111" and may occupy the RnB signal line.

7 is a diagram illustrating a memory control apparatus of a multi-die package according to another embodiment of the present invention.

Referring to FIG. 7, a memory control device includes CE demultiplexing / RnB multiplexing logic 720 and a separator code register 710, and the multi-die package includes a plurality of memory chip dies. Include them.

Chips in a package are assigned unique identification codes. The flash interface device transmits the identification code to the multi-die package and the memory control device using a combination of the ALE signal and the CLE signal. The received delimiter code is stored in delimiter code register 710. When the CE signal is activated, the CE demuxing / RnB muxing logic 720 activates the CE signal for the selected chip in the multi-die package according to the distinguishing code stored in the distinguishing code register 710. The CE demuxing / RnB muxing logic 720 activates and transmits the RnB signal to the flash interface device when any one of the RnB signal buses in the multi-die package is activated.

The memory control method according to another exemplary embodiment of the present invention may control a plurality of memory units using a common input / output bus and a common control signal line.

The memory control method may transmit an identification code to a plurality of memory units via a common input / output bus.

The memory control method may transmit a command and an address to the first memory unit via a common input / output bus.

The memory control method may check whether the first memory unit has completed the transmitted command. In this case, the memory control method may determine whether the first memory unit completes the transmitted command according to the value of the RnB signal commonly connected to the plurality of memory units.

According to an embodiment, if the command is a read command, the memory control method receives data corresponding to the command and the address from the first memory unit.

According to an embodiment, if the command is a write command, the memory control method transmits data corresponding to the command and the address to the first memory unit. If the command is an erase command, no separate data need be transmitted. At this time, the memory control method suspends execution of the next command until the first memory unit completes the transferred command.

According to an embodiment, in the step of transmitting the identification code to the plurality of memory units, the memory control method may apply the identification code transmission mode to the common control signal line. In this case, the memory control method may transmit the identification code to the plurality of memory units via the common input / output bus while the identification code transmission mode is applied to the common control signal line.

The memory control method according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by those equivalent to the claims.

1 is a diagram illustrating an example of a flash memory system 100.

2 is a timing diagram illustrating an operation of a plurality of control signals and an I / O signal of the flash memory system 100.

3 is a diagram illustrating an example of a flash memory system 300.

4 is a diagram illustrating an example of a multi-die package of a flash memory.

5 is a timing diagram illustrating a read operation of the memory control apparatus according to an embodiment of the present invention.

6 is a diagram illustrating a memory control device according to an embodiment of the present invention.

7 is a diagram illustrating a memory control apparatus of a multi-die package according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

610: flash interface device

620: NAND flash memory unit 0

630: NAND flash memory unit 1

640: NAND flash memory unit 5

Claims (14)

A plurality of memory units; And Interface unit connected to the plurality of memory units via a common input / output bus and a common control signal line Including, The interface unit transmits an identification code for identifying each of the plurality of memory units via the common input and output bus, And only a first memory unit corresponding to the transmitted identification code among the memory units operates in response to the common control signal. The method of claim 1, The common control signal line is And at least one of an address mode, a command mode, a data mode, and an identification code transmission mode. The method of claim 2, The interface unit And transmit the identification code when the common control signal line indicates the identification code transmission mode. The method of claim 2, The interface unit And transmitting the address via the common input / output bus when the common control signal line indicates the address mode. The method of claim 2, The interface unit And when the common control signal line indicates the command mode, transmitting a read or write command via the common input / output bus. The method of claim 2, The interface unit And when the common control signal line indicates the data mode, transfer data via the common input / output bus or receive data from the first flash memory. The method of claim 1, The plurality of memory units A memory control device characterized in that stacked in one package by a multi-die package technique. The method of claim 1, Each of the plurality of memory units An identification code comparison unit for storing an identification code and determining whether the stored identification code corresponds to the transmitted identification code Memory control device comprising a. The method of claim 1, Each of the plurality of memory units An identification code comparison section that displays an identification code by connecting a portion of the non-connection pin to a power terminal or a ground terminal, and determines whether the displayed identification code corresponds to the transmitted identification code. Memory control device comprising a. A memory control method for controlling a plurality of memory units by using a common input / output bus and a common control signal line, Transmitting the identification code to the plurality of memory units via a common input / output bus; Transmitting a command and an address to the first memory unit corresponding to the identification code via the common input / output bus; And Confirming whether the first memory unit has completed the transmitted command Memory control method comprising a. The method of claim 10, The step of transmitting the identification code to the plurality of memory units Applying an identification code transmission mode to the common control signal line; And Transmitting the identification code to the plurality of memory units via the common input / output bus while the identification code transmission mode is applied to the common control signal line. Memory control method comprising a. The method of claim 10, If the command is a read command, receiving data corresponding to the command and the address from the first memory unit Memory control method comprising a further. The method of claim 10, If the command is a write command, transmitting data corresponding to the command and the address to the first memory unit Memory control method comprising a further. A computer-readable recording medium in which a program for executing the method of any one of claims 10 to 13 is recorded.

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