KR20090052087A - Wafer package structure - Google Patents
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- KR20090052087A KR20090052087A KR1020070118618A KR20070118618A KR20090052087A KR 20090052087 A KR20090052087 A KR 20090052087A KR 1020070118618 A KR1020070118618 A KR 1020070118618A KR 20070118618 A KR20070118618 A KR 20070118618A KR 20090052087 A KR20090052087 A KR 20090052087A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 abstract 4
- 239000004020 conductor Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000010949 copper Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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Abstract
본 발명은 다층 웨이퍼 구조에 관한 것으로, 본 발명에 따른 다층 웨이퍼 구조의 일 예는, 적층되는 각 웨이퍼들(wafers)을 전기적으로 연결하는 비아들(vias)을 구비하되, 상기 각 비아는 화학적증착기상(CVD)을 TSV(through silicon via)에 가능하게 하기 위해 특정 금속으로 이루어진 다수 개의 소정 크기를 가진 비아 홀(via hole) 또는 슬릿(slit) 형태로 집적할 수 있는 마스크 구조를 가진 것을 특징으로 한다.The present invention relates to a multi-layered wafer structure, an example of the multi-layered wafer structure according to the present invention includes vias that electrically connect the respective wafers to be stacked, wherein each via is chemically deposited. Characterized by having a mask structure capable of integrating a plurality of predetermined size via holes or slits formed of a specific metal to enable CVD to TSV (through silicon via). do.
따라서, 본 발명에 의하면, 보이드(void) 및 심(seam) 현상을 최소화할 수 있다.Therefore, according to the present invention, voids and seams can be minimized.
반도체 소자, SiP, 다층 웨이퍼, 비아 홀, 슬릿, 보이드, 심 Semiconductor Devices, SiP, Multilayer Wafers, Via Holes, Slits, Voids, Shims
Description
본 발명은 다층 웨이퍼 구조에 관한 것으로, 특히 SiP(System in Package) 다층 웨이퍼 제조시에 보이드(void) 및 심(seam) 발생을 억제하는 비아 홀 또는 슬릿을 구비한 다층 웨이퍼 구조에 관한 것이다.BACKGROUND OF THE
현재 반도체 공정은 크게 웨이퍼 레벨(wafer level)에서의 제작 공정 및 제작된 웨이퍼를 절단해서 얻어진 칩(chip)을 조립하는 패키지(package) 공정으로 구분되어 진행되고 있다.Currently, the semiconductor process is largely divided into a manufacturing process at a wafer level and a package process of assembling a chip obtained by cutting a manufactured wafer.
관련하여, 기존의 구리 딥 컨덕터(Cu deep via conductor) 사용을 위해서는 알루미늄(Al) 배선 공정(back-end-of-the-line; BEOL) 공정과 혼용해서 사용할 수 없기 때문에 장비 사용 영역(area)이 격리되어야 한다.In this regard, the area of equipment use is not available for use with conventional copper deep via conductors because it cannot be mixed with aluminum back-end-of-the-line (BEOL) processes. This should be isolated.
따라서, 관련 장비를 새로 투자해야하는 문제점이 있다. 또한, 구리(Cu) 확산(diffusion)이 매우 빨라 장치 파라미터(device parameter)에 영향을 미치기 때문에 사용하기 힘든 문제점이 있다.Therefore, there is a problem that a new investment of the related equipment. In addition, since copper (Cu) diffusion is very fast and affects device parameters, it is difficult to use.
이에 따라, 상기와 같은 문제점을 해결하고자 텅스텐(W)을 딥 비어 컨덕터(deep via conductor)로 사용한다.Accordingly, in order to solve the above problem, tungsten (W) is used as a deep via conductor.
그러나, 상기와 같이 텅스텐(W)을 사용한다고 하더라도, 비어 홀 크기(via hole size)가 클 경우에는 비어 보이드(via void) 및 심(seam)이 발생하여 배선 신뢰도(reliability) 특성이 나빠지는 문제점이 있다.However, even when tungsten (W) is used as described above, when the via hole size is large, via voids and seams are generated, resulting in poor wiring reliability characteristics. There is this.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 보이드 및 심 현상을 최소화할 수 있는 다층 웨이퍼 구조를 제공하는 것을 목적으로 한다.The present invention is to solve the above problems, an object of the present invention to provide a multi-layered wafer structure that can minimize the void and seam phenomenon.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 다층 웨이퍼 구조의 일 예는, 적층되는 각 웨이퍼들을 전기적으로 연결하는 비아들(vias)을 구비하되, 상기 각 비아는 화학적증착기상(CVD)를 TSV(through silicon via)에 가능하게 하기 위해 특정 금속으로 이루어진 다수 개의 소정 크기를 가진 비아 홀(via hole) 또는 슬릿(slit) 형태로 집적할 수 있는 마스크 구조를 가진 것을 특징으로 한다.One example of a multi-layered wafer structure according to the present invention for achieving the above object is provided with vias for electrically connecting each wafer to be stacked, each via TSV chemical vapor deposition (CVD) TSV It is characterized by having a mask structure capable of integrating a plurality of predetermined size via holes or slits in a specific metal to enable through silicon via.
이때, 상기 각 비아는 2 내지 20 ㎛ 정도의 크기를 가질 수 있다.In this case, each of the vias may have a size of about 2 to 20 μm.
그리고 상기 각 비아 홀 또는 슬릿은 1 내지 3 ㎛ 정도의 크기를 가질 수 있다.Each via hole or slit may have a size of about 1 to 3 μm.
또한, 상기 특정 금속은 텅스텐(W) 또는 실리콘(Si) 일 수 있다.In addition, the specific metal may be tungsten (W) or silicon (Si).
상술한 본 발명에 따라 다층 웨이퍼 구조에 의하면, 보이드 및 심 현상을 최소화할 수 있는 효과가 있다.According to the multilayer wafer structure according to the present invention described above, there is an effect that can minimize the void and seam phenomenon.
이하 상기와 같은 목적을 달성하기 위한 본 발명의 구체적인 실시 예를 첨부된 도면을 참조하여 상세하게 설명하면, 다음과 같다.Hereinafter, specific embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
이하 본 발명에 따른 다층 웨이퍼 구조 및 그 제조 방법을 설명한다. 이때, 설명의 편의를 위해 본 명세서에서는 다층 웨이퍼 구조는 특히 SiP(System in Package) 다층 웨이퍼 구조를 일 예로 하여 설명한다.Hereinafter, a multilayer wafer structure and a method of manufacturing the same according to the present invention will be described. In this case, for convenience of description, the multilayer wafer structure will be described using an SiP (System in Package) multilayer wafer structure as an example.
상기 본 발명에 따른 SiP 다층 웨이퍼 구조는 제조시에 신뢰성 있는 텅스텐(W) CVD(Chemical Vapor Deposition; 화학적 기상성장)을 막을 TSV(through silicon via)에 사용하기 위해 보이드(void) 및 심(seam) 발생을 억제하고자 한다.The SiP multi-layered wafer structure according to the present invention is a void and seam for the use of a reliable tungsten (W) chemical vapor deposition (CVD) film in TSV (through silicon via) in manufacturing. To suppress the occurrence.
이를 위해 본 발명에서는 우선, 텅스텐(W)을 상기 TSV로써 사용하기 위해 다양한 패턴의 딥 비아 컨덕터(deep via conductor) 패턴을 형성한다.To this end, in the present invention, in order to use tungsten (W) as the TSV, deep via conductor patterns of various patterns are formed.
도 1a 내지 1d는 본 발명에 따라 구성한 텅스텐 비아 마스크의 단면도의 예를 도시한 것이다.1A-1D show examples of cross-sectional views of a tungsten via mask constructed in accordance with the present invention.
본 발명은, 첨부된 도 1a 내지 1d에 도시된 바와 같이, 다양한 패턴의 딥 비아 컨덕터 패턴을 형성하는 것을 특징으로 한다.The present invention is characterized by forming a deep via conductor pattern of various patterns, as shown in the accompanying Figures 1a to 1d.
상기 도 1a 내지 1d에 딥 비아 컨덕트 패턴은, 여러 가지 작은 사이즈(size)의 비아 홀(via hole) 및 슬리트(slit)를 집적(integration)한 것으로, 원하는 딥 비아 컨덕터(deep via conductor)로써의 역할을 할 수 있도록 고안되었다.The deep via conductor pattern shown in FIGS. 1A to 1D is an integration of various small size via holes and slits, and a desired deep via conductor. It is designed to play a role.
따라서, 상기와 같이 형성한 딥 비아 컨덕트 패턴에 의할 경우, 매크로(macro) 한 사이즈의 비아 홀(via hole)을 텅스텐(W)으로 채움으로 인해, 발생할 수 있는 비아 보이드(via void) 및 심(seam)을 방지할 수 있다. Therefore, in the case of the deep via conductor pattern formed as described above, via voids, which may occur due to filling the via holes of one size macro with tungsten (W), and The seam can be prevented.
이하에서는 본 발명에 따라 구성한 다양한 패턴의 딥 비아 컨덕터 패턴을 이용하여 다층 웨이퍼를 제조하는 과정을 설명하면, 다음과 같다.Hereinafter, a process of manufacturing a multilayer wafer using a deep via conductor pattern having various patterns configured according to the present invention will be described.
도 2a 내지 2l은 본 발명에 따른 다층 웨이퍼 제조 방법을 설명하기 위해 순차적으로 도시한 것이다. Figures 2a to 2l are shown in order to explain a method for manufacturing a multilayer wafer according to the present invention.
이하 본 발명에 따른 다층 웨이퍼 제조 방법을 순차적으로 설명하면, 다음과 같다.Hereinafter, a method of manufacturing a multilayer wafer according to the present invention will be described sequentially.
먼저, 구리(Cu)로 된 탑 금속(top metal)(1)을 CMP(Chemical Mechanical Polishing) 식각(etching)하여 도 2a와 같이 평탄화(planaration)한다.First, a
상기 탑 금속(1)을 CMP로 식각하여 평탄화한 층 상부에 패시베이션(passivation)을 도 2b와 같이 증착(deposition)한다.The
상기 패시베이션(passivation) 증착 후, 딥 비아(deep via)를 도 2c와 같이, 슬릿 형태로 패터닝(patterning)하고 식각한다.After the passivation deposition, deep vias are patterned and etched into slit shapes, as shown in FIG. 2C.
이때, 상기 비아(via)는 2 내지 20㎛ 정도의 사이즈(size)로 형성할 수 있다. 또한, 상기 비아 홀(via hole)은 1 내지 3㎛ 정도의 사이즈로 제한할 수 있다. 그리고 상기 슬릿(slit) 형태의 직각 사이즈(rectangular size)는 너비(width) 1 내지 3㎛ 정도로 형성하고, 높이(height)는 1 내지 4㎛ 정도로 형성할 수 있다.In this case, the via may be formed in a size of about 2 to 20 μm. In addition, the via hole may be limited to a size of about 1 to 3㎛. The rectangular size of the slit form may be formed in a width of about 1 to 3 μm, and a height of about 1 to 4 μm.
상기 식각된 딥 비아(deep via)와 증착된 패시베이션(passivation) 상부 전면에 배리어 산화막(barrier oxide)을 도 2d와 같이 증착한다.A barrier oxide layer is deposited on the etched deep via and the upper surface of the deposited passivation as shown in FIG. 2D.
그리고 상기 증착된 배리어 산화막 상부 전면에 텅스텐(W)을 증착하여 딥 비 아 텅스텐 CVD(deep via W CVD)를 도 2e와 같이 형성한다.Tungsten (W) is deposited on the entire surface of the deposited barrier oxide layer to form deep via tungsten CVD (Deep Via W CVD) as shown in FIG. 2E.
그리고 상기 형성된 딥 비아 텅스텐 CVD를 CMP로 식각하여 도 2f와 같이 평탄화한다.The formed deep via tungsten CVD is etched with CMP to planarize as shown in FIG. 2F.
다음으로, 상기 도 2f와 같이 평탄화한 후, 도 2g와 같이 패드(pad)를 오픈(open)하고, 상기 오픈된 패드를 포함하여 기판 전면에 도 2h와 같이 금속(metal)을 증착한다. 이때, 상기 금속은 알루미늄(Al)일 수 있다.Next, after planarization as shown in FIG. 2F, a pad is opened as shown in FIG. 2G, and metal is deposited on the entire surface of the substrate including the open pad as shown in FIG. 2H. In this case, the metal may be aluminum (Al).
상기와 같이, 기판 전면에 금속을 증착한 후, 도 2i와 같이 식각하고, 상기 식각 후 도 2j와 같이 기판 전면에 질화막 및 산화막(SiN, SiO2)을 증착한다.As described above, the metal is deposited on the entire surface of the substrate and then etched as shown in FIG. 2I. After the etching, the nitride film and the oxide layer (SiN, SiO 2) are deposited on the substrate as shown in FIG. 2J.
상기와 같이 기판 전면에 산화막을 증착한 후, 도 2k와 같이 증착한 산화막을 식각하고, 상기 식각 후 도 2l과 같이 딥 비아 텅스텐 CVD를 이용하여 다층 웨이퍼를 비아 홀의 보이드 및 심 현상을 발생시키지 않으면서 접합할 수 있게 된다.After the oxide film is deposited on the entire surface of the substrate as described above, the oxide film deposited as shown in FIG. 2K is etched, and after the etching, as shown in FIG. Can be joined together.
따라서, 본 발명에 따른 딥 비아 컨덕터를 이용함으로써, 제조 공정에 따라 텅스텐(W)을 작은 사이즈(size)의 비아 홀(via hole) 및 슬리트(slit) 형태로 형성하여 다층 웨이퍼를 제조할 수 있을 뿐만 아니라, 상기 비아 홀(via hole)의 보이드(void) 및 심(seam) 현상을 최소화할 수 있다.Accordingly, by using the deep via conductor according to the present invention, a multi-layer wafer may be manufactured by forming tungsten (W) into small via holes and slits in accordance with a manufacturing process. In addition, voids and seams of the via holes may be minimized.
또한, 이상 상술한 실시 예에서는 텅스텐을 이용하여 설명하였으나, 상기 텅스텐을 대신하여 실리콘(Si)을 이용하여 동일한 효과를 얻을 수도 있다.In addition, although the above-described embodiment has been described using tungsten, the same effect may be obtained by using silicon (Si) instead of the tungsten.
이상에서는 본 발명의 기술 사상을 설명함에 있어서, 특정 실시 예를 첨부된 도면과 함께 도시하고 설명하였다. 다만, 본 발명은 상술한 실시 예에 한정되는 것은 아니며, 본 발명의 기술 사상을 벗어나지 않는 범위 즉, 당해 발명이 속하는 기 술 분야에서 통상의 지식을 가진 자에 의해 다양한 수정 및 변경을 가능하다.In the above description of the technical idea of the present invention, specific embodiments have been shown and described with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and various modifications and changes may be made by those skilled in the art without departing from the spirit of the present invention, that is, the technical field to which the present invention pertains.
도 1a 내지 1d는 본 발명에 따라 구성한 텅스텐 비아 단면 마스크의 예를 도시한 것1A-1D illustrate examples of tungsten via cross-sectional masks constructed in accordance with the present invention.
도 2a 내지 2l은 본 발명에 따른 다층 웨이퍼 제조 방법을 설명하기 위해 순차적으로 도시한 것Figures 2a to 2l are shown sequentially to explain a method for manufacturing a multilayer wafer according to the present invention
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1; 탑 금속 2; 패시베이션One;
3; 비아 홀 4; 배리어 산화막3; Via
5; 텅스텐 CVD 6; 패드 메탈5;
7; 패드 산화막 8; 다층 웨이퍼7;
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