KR20090049409A - Package module - Google Patents

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KR20090049409A
KR20090049409A KR1020070115652A KR20070115652A KR20090049409A KR 20090049409 A KR20090049409 A KR 20090049409A KR 1020070115652 A KR1020070115652 A KR 1020070115652A KR 20070115652 A KR20070115652 A KR 20070115652A KR 20090049409 A KR20090049409 A KR 20090049409A
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South Korea
Prior art keywords
substrate
package module
chip
bare chip
passive element
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KR1020070115652A
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Korean (ko)
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김진수
임순규
김기찬
김태현
김동국
정태성
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삼성전기주식회사
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Priority to KR1020070115652A priority Critical patent/KR20090049409A/en
Publication of KR20090049409A publication Critical patent/KR20090049409A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

패키지 모듈이 개시된다. 기판; 기판의 일면에 실장되는 멀티칩(multi-chip)부; 기판에 실장되는 수동소자; 및 멀티칩부와 수동소자를 커버하도록 기판의 일면에 형성되는 몰딩부를 포함하되, 멀티칩부는, 전원 관리 베어칩(power management bare chip)과 베이스밴드 베어칩(baseband bare chip) 및 메모리 베어칩(memory bare chip) 중 어느 둘 이상이 적층되어 형성되는 것을 특징으로 하는 패키지 모듈은, 여러 기능을 가지는 전자소자를 통합함으로써 실장 면적을 줄일 수 있고, I/O 수를 감소시킬 수 있다.A package module is disclosed. Board; A multi-chip unit mounted on one surface of the substrate; A passive element mounted on the substrate; And a molding unit formed on one surface of the substrate to cover the multichip unit and the passive element, wherein the multichip unit includes a power management bare chip, a baseband bare chip, and a memory bare chip. The package module, which is formed by stacking any two or more of bare chips, can reduce the mounting area and reduce the number of I / Os by integrating electronic devices having various functions.

패키지, 모듈, 모바일 기기 Packages, modules and mobile devices

Description

패키지 모듈{package module}Package module

본 발명은 패키지 모듈에 관한 것이다.The present invention relates to a package module.

전자기기의 고기능화와 소형화가 동시에 이루어지고 있는 시장의 변화에 부응하기 위해, 부품의 패키징 기술은 최근 많은 발전을 거듭하고 있다. 특히, 여러 가지 기능이 하나로 통합되거나, 동일 기능을 위해 구성되는 여러 부품들이 한 개의 모듈 위에 패키징 되는 제품들이 출현하고 있다. 이러한 부품의 모듈화는 전자기기의 고기능화 및 소형화를 도모하는 좋은 방법 중의 하나이다.In order to cope with the changes in the market in which both high performance and miniaturization of electronic devices are simultaneously performed, the packaging technology of components has been developed in recent years. In particular, there are products in which several functions are integrated into one or several components configured for the same function are packaged on one module. Modularization of these components is one of the good ways to achieve high functionality and miniaturization of electronic devices.

모바일 폰 제품의 부품 구성은 기능군별로 크게 고주파(RF, radio frequency) 기능군, 베이스밴드(baseband) 기능군, 메모리(memory) 기능군, 파워(power) 기능군으로 나뉠 수 있다. 이러한 기능군들은 하나의 메인보드 위에 블록(block)의 형태로 자리잡고 있으며 이러한 블록은 각 기능의 핵심을 이루는 반도체 IC 패키지와 그 주변의 수동부품들로 구성된다. Component parts of the mobile phone products can be divided into radio frequency (RF), baseband (memory), memory (power) function group, power (function) group. These functional groups are placed in the form of blocks on a single motherboard, which are composed of semiconductor IC packages and the passive components around them that form the core of each function.

이렇게 부품들이 모두 하나의 메인보드에 직접 실장되는 경우, 메인보드의 여유면적이 좁아지고, 각 IC의 구동을 위한 I/O의 수가 증가함에 따라 메인보드의 설계가 복잡해지며 4층 이상의 구조가 불가피하게 된다. 그 결과, 제품 원가가 상승하게 될 뿐만 아니라, 메인보드의 설계에 많은 시간과 노력이 필요하게 된다. If all the components are directly mounted on one motherboard, the free space of the motherboard is narrowed, and the design of the motherboard becomes complicated as the number of I / Os for driving each IC increases. Done. As a result, not only will the product cost rise, but it will also take a lot of time and effort to design the motherboard.

또한 IC 패키지의 실장 불량이 발생하는 경우, 수리작업이 매우 어려워 경우에 따라서는 메인보드에 실장되어 있는 나머지 부품들까지도 동시에 폐기해야 하는 문제가 발생할 수 있다.In addition, when the IC package is badly mounted, repair work is very difficult, and in some cases, the remaining components mounted on the motherboard may be disposed of at the same time.

상기에서 언급한 모바일 폰의 각 기능군을 좁은 공간에 배치하고자, 수동부품의 소형화, 패키지 제품의 미세 피치화가 진행되고 있지만, 이러한 노력만으로 모바일 폰의 소형화를 구현하는 것은 한계가 있으며, 패키지 제품의 미세 피치화는 수리작업의 어려움을 한층 가중시키고 있는 실정이다.In order to arrange each functional group of the mobile phone mentioned above in a narrow space, miniaturization of passive components and fine pitch of packaged products are progressing, but the miniaturization of mobile phones is limited by such efforts. Fine pitching is a situation that increases the difficulty of repair work.

본 발명은 여러 기능을 가지는 전자소자를 통합함으로써 실장 면적을 줄일 수 있고, I/O 수를 감소시킬 수 있는 패키지 모듈을 제공하는 것이다.The present invention provides a package module capable of reducing the mounting area and reducing the number of I / O by integrating electronic devices having various functions.

본 발명의 일 측면에 따르면, 기판; 기판의 일면에 실장되는 멀티칩(multi-chip)부; 기판에 실장되는 수동소자; 및 멀티칩부와 수동소자를 커버하도록 기판의 일면에 형성되는 몰딩부를 포함하되, 멀티칩부는, 전원 관리 베어칩(power management bare chip)과 베이스밴드 베어칩(baseband bare chip) 및 메모리 베어칩(memory bare chip) 중 어느 둘 이상이 적층되어 형성되는 것을 특징으로 하는 패키지 모듈을 제공할 수 있다.According to an aspect of the invention, the substrate; A multi-chip unit mounted on one surface of the substrate; A passive element mounted on the substrate; And a molding unit formed on one surface of the substrate to cover the multichip unit and the passive element, wherein the multichip unit includes a power management bare chip, a baseband bare chip, and a memory bare chip. It is possible to provide a package module, characterized in that any two or more of bare chips are stacked and formed.

기판에는 쏘필터(SAW filter)가 추가로 실장될 수 있으며, 수동소자는 기판에 내장될 수도 있다.A SAW filter may be additionally mounted on the substrate, and the passive element may be embedded in the substrate.

한편, 기판은 유기(organic)기판 또는 세라믹(ceramic)기판일 수 있으며, 기판의 타면에는 복수의 전극이 형성될 수 있다. 이 때, 복수의 전극에는 각각 도전성 볼이 결합될 수도 있다.The substrate may be an organic substrate or a ceramic substrate, and a plurality of electrodes may be formed on the other surface of the substrate. In this case, conductive balls may be coupled to the plurality of electrodes, respectively.

본 발명의 바람직한 실시예에 따르면, 여러 기능을 가지는 전자소자를 통합함으로써 실장 면적을 줄일 수 있고, I/O 수를 감소시킬 수 있다. According to a preferred embodiment of the present invention, the mounting area can be reduced and the number of I / Os can be reduced by integrating electronic devices having various functions.

본 발명은 다양한 변환을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변환, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 본 발명을 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생 략한다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, when it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

이하, 본 발명에 따른 패키지 모듈의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.Hereinafter, a preferred embodiment of a package module according to the present invention will be described in detail with reference to the accompanying drawings, in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and duplicated thereto. The description will be omitted.

도 1은 본 발명의 일 실시예에 따른 패키지 모듈을 나타내는 단면도이고, 도 2는 종래기술에 따른 패키지 모듈을 구비하는 메인보드를 나타내는 평면도이며, 도 3은 본 발명의 일 실시예에 따른 패키지 모듈을 구비하는 메인보드를 나타내는 평면도이다. 도 1 내지 도 3을 참조하면, 기판(10), 패턴(12), 전극(14), 멀티칩부(20), 베어칩(22), 접착층(24), 쏘필터(30), 수동소자(40), 몰딩부(50), 도전성 볼(60), 패키지 모듈(100), 메인보드(1, 110), 전력 관리 칩(2), 베이스밴드 칩(3), 메모리 칩(4)이 도시되어 있다.1 is a cross-sectional view showing a package module according to an embodiment of the present invention, Figure 2 is a plan view showing a main board having a package module according to the prior art, Figure 3 is a package module according to an embodiment of the present invention It is a top view which shows the main board provided with. 1 to 3, a substrate 10, a pattern 12, an electrode 14, a multichip unit 20, a bare chip 22, an adhesive layer 24, a saw filter 30, a passive element ( 40, molding 50, conductive ball 60, package module 100, main boards 1 and 110, power management chip 2, baseband chip 3, and memory chip 4 are shown. It is.

본 실시예에 따른 패키지 모듈은 전력 관리 칩(power management chip), 메모리 칩(memory chip), 고주파 칩(RF chip), 베이스밴드 칩(baseband chip) 등과 같은 IC들이 베어칩(bare chip, 22) 상태로 적층되어 패키징 됨으로써 멀티칩부(20)를 구성하고, 이러한 멀티칩부(20)가 기판(10)에 실장되는 구조를 갖는 것에 특징이 있다.In the package module according to the present embodiment, ICs such as a power management chip, a memory chip, an RF chip, a baseband chip, and the like are bare chips 22. By stacking and packaging in a state, the multi-chip unit 20 is constituted, and the multi-chip unit 20 has a structure in which it is mounted on the substrate 10.

즉, 종래기술에 따른 패키지 모듈이, 도 2에 도시된 바와 같이 전력 관리 칩(2), 베이스밴드 칩(3), 메모리 칩(4) 등이 각각 별개의 패키지 형태로 실장되는 구조를 제시하는 것에 반해, 본 실시예는 여러 기능을 수행하는 IC들이 베어칩(22)의 형태로 하나의 기판에 적층되어 하나의 패키지를 형성함으로써 그 실장 면적을 현저히 줄일 수 있는 효과를 나타낼 수 있는 것이다. 여기서 베어칩이란 웨이퍼에서 잘라낸 IC로서, 개별적인 패키징이 수행되기 전 상태의 것을 의미한다.That is, the package module according to the prior art, as shown in FIG. 2, present a structure in which the power management chip 2, the baseband chip 3, the memory chip 4, etc. are mounted in separate packages, respectively. On the other hand, the present embodiment can exhibit an effect that the mounting area can be significantly reduced by stacking ICs performing various functions on one substrate in the form of a bare chip 22 to form one package. Here, the bare chip is an IC cut out from the wafer, and means a state before an individual packaging is performed.

이에 대해 도 1을 참조하여 보다 구체적으로 설명하도록 한다.This will be described in more detail with reference to FIG. 1.

기판(10)에는 소정의 회로패턴(12)이 형성되어 이하에서 설명할 멀티칩부(20) 및 수동소자(40) 등이 전기적으로 연결되도록 할 수 있으며, 단층 또는 다층으로 이루어질 수 있다. 이러한 기판(10)으로는 유기(organic) 기판이나 LTCC(low temperature co-fired ceramic)와 같은 세라믹(ceramic) 기판이 이용될 수 있다.A predetermined circuit pattern 12 is formed on the substrate 10 to allow the multi-chip unit 20 and the passive element 40 to be described below to be electrically connected, and may be formed in a single layer or a multilayer. As the substrate 10, an organic substrate or a ceramic substrate such as a low temperature co-fired ceramic (LTCC) may be used.

멀티칩부(20)는 상술한 바와 같이 전력 관리 칩(power management chip), 메모리 칩(memory chip), 고주파 칩(RF chip), 베이스밴드 칩(baseband chip) 등과 같은 IC들이 베어칩(22) 상태로 적층됨으로써 형성될 수 있다. 고주파 칩과 베이스 밴드 칩이 개별적으로 구현된 IC 이 외에, 고주파 칩과 베이스밴드 칩이 단일의 형태로 구현된 통합 IC를 이용할 수도 있음은 물론이다.As described above, the multi-chip unit 20 includes ICs such as a power management chip, a memory chip, an RF chip, a baseband chip, and the like. It can be formed by laminating with. In addition to the IC in which the high frequency chip and the baseband chip are separately implemented, an integrated IC in which the high frequency chip and the baseband chip are implemented in a single form may be used.

도 1에는 두 개의 베어칩(22)이 적층되어 있는 구조가 제시되어 있으나, 멀티칩부(20)에 포함되는 베어칩(22)의 종류는, 설계자의 의도에 따라 다양하게 변경될 수 있으며, 그에 따라 멀티칩부(20)의 층 수 또한 다양하게 변경될 수 있다.1 shows a structure in which two bare chips 22 are stacked, but the type of bare chips 22 included in the multi-chip unit 20 may be variously changed according to a designer's intention. Accordingly, the number of layers of the multichip unit 20 may also be variously changed.

각각의 베어칩(22)은 접착층(24)을 개재하여 차례로 적층될 수 있다. 이 때, 필요에 따라 각 층 사이에 인터포저(미도시), 금속층(미도시) 등이 구비되어 방열효과를 향상시킬 수도 있다.Each bare chip 22 may be stacked in this order via the adhesive layer 24. In this case, an interposer (not shown), a metal layer (not shown), or the like may be provided between the layers as necessary to improve the heat dissipation effect.

이처럼, 여러 기능을 수행하는 IC가 수직구조로 형성됨으로써, 기판(10)에의 실장 면적을 현저히 줄일 수 있게 되어, 모바일 기기의 소형화에 효율적으로 대처할 수 있게 된다.As described above, since the ICs that perform various functions are formed in a vertical structure, the mounting area on the substrate 10 can be significantly reduced, thereby efficiently coping with miniaturization of mobile devices.

한편, 모바일 기기의 특성 상, 트리밍(trimming)을 위한 쏘필터(30)와, 저항(R), 인덕터(L), 커패시터(C) 및 밸룬(Balun) 등과 같은 수동소자(40)가 기판(10)에 함께 실장될 수 있다. 이 때, 수동소자(40)들의 전부 또는 일부는 각각 패턴화 되어 기판(10)에 내장될 수도 있다.On the other hand, due to the characteristics of the mobile device, the saw filter 30 for trimming (trimming), passive elements 40 such as resistor (R), inductor (L), capacitor (C) and balun (Balun) is a substrate ( 10) can be mounted together. In this case, all or some of the passive elements 40 may be patterned and embedded in the substrate 10, respectively.

이처럼 수동소자(40)가 기판(10)의 내부에 내장되는 구조를 갖도록 함으로써, 기판(10) 표면의 설계 자유도를 보다 충분히 확보할 수 있게 된다. 뿐만 아니라, 얇은 필름 타입(thin film type)의 쏘필터(30)를 이용함으로써 실장 면적뿐만 아니라, 실장 부피 또한 감소시킬 수 있다.As described above, the passive element 40 has a structure embedded in the substrate 10, whereby the degree of freedom in designing the surface of the substrate 10 can be more sufficiently secured. In addition, by using a thin film type saw filter 30, not only the mounting area but also the mounting volume can be reduced.

이러한 수동소자(40)와 쏘필터(30) 및 상술한 멀티칩부(20)가 몰딩부(50)에 의해 함께 패키징됨으로써 도 1에 도시된 바와 같은 하나의 패키지 모듈(100)을 구성할 수 있게 된다. 이 때, 면적효율을 보다 높일 수 있도록 하기 위하여, 기판(10)의 하면에 복수의 전극(14) 즉, I/O를 형성하여 LGA(land grid array)를 구현할 수도 있다. 뿐만 아니라, 전극(14)에 각각 도전성 볼(60)을 결합하여 BGA(ball grid array)를 구현할 수도 있다. LGA 또는 BGA를 구현하기 위한 기판(10) 하면의 설계는 설계자의 의도에 따라 다양하게 변경될 수 있다.The passive element 40, the saw filter 30, and the multi-chip unit 20 described above may be packaged together by the molding unit 50 to form one package module 100 as shown in FIG. 1. do. In this case, in order to increase the area efficiency, a plurality of electrodes 14, that is, I / Os may be formed on the bottom surface of the substrate 10 to implement a land grid array (LGA). In addition, the ball grid array (BGA) may be implemented by coupling the conductive balls 60 to the electrodes 14, respectively. The design of the lower surface of the substrate 10 for implementing the LGA or the BGA may be variously changed according to the intention of the designer.

도 3에는 본 실시예에 따른 패키지 모듈(100)이 메인보드(110)에 실장된 모습이 도시되어 있다. 상술한 바와 같이, 여러 기능을 수행하는 IC가 수직구조로 적층되어 멀티칩부(20)를 형성하는 구조를 가짐으로써, 도 2에 도시된 종래기술에 비해 실장 면적이 현저히 감소한 것을 확인할 수 있다.3 shows the package module 100 according to the present embodiment mounted on the main board 110. As described above, since the ICs performing various functions are stacked in a vertical structure to form the multi-chip unit 20, the mounting area may be remarkably reduced as compared with the related art shown in FIG. 2.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야에서 통상의 지식을 가진 자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

전술한 실시예 외의 많은 실시예들이 본 발명의 특허청구범위 내에 존재한다.Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

도 1은 본 발명의 일 실시예에 따른 패키지 모듈을 나타내는 단면도.1 is a cross-sectional view showing a package module according to an embodiment of the present invention.

도 2는 종래기술에 따른 패키지 모듈을 구비하는 메인보드를 나타내는 평면도.Figure 2 is a plan view showing a main board having a package module according to the prior art.

도 3은 본 발명의 일 실시예에 따른 패키지 모듈을 구비하는 메인보드를 나타내는 평면도.Figure 3 is a plan view showing a main board having a package module according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10: 기판 12: 패턴10: substrate 12: pattern

14: 전극 20: 멀티칩부14: electrode 20: multichip part

22: 베어칩 24: 접착층22: bare chip 24: adhesive layer

30: 쏘필터 40: 수동소자30: Saw filter 40: Passive element

50: 몰딩부 60: 도전성 볼50: molding 60: conductive ball

100: 패키지 모듈 110: 메인보드100: package module 110: main board

Claims (6)

기판;Board; 상기 기판의 일면에 실장되는 멀티칩(multi-chip)부;A multi-chip unit mounted on one surface of the substrate; 상기 기판에 실장되는 수동소자; 및A passive element mounted on the substrate; And 상기 멀티칩부와 상기 수동소자를 커버하도록 상기 기판의 상기 일면에 형성되는 몰딩부를 포함하되, 상기 멀티칩부는,A molding part formed on the one surface of the substrate to cover the multichip part and the passive element, wherein the multichip part, 전원 관리 베어칩(power management bare chip)과 베이스밴드 베어칩(baseband bare chip) 및 메모리 베어칩(memory bare chip) 중 어느 둘 이상이 적층되어 형성되는 것을 특징으로 하는 패키지 모듈.A package module, characterized in that any two or more of a power management bare chip, a baseband bare chip, and a memory bare chip are stacked and formed. 제1항에 있어서,The method of claim 1, 상기 기판에 실장되는 쏘필터(SAW filter)를 더 포함하는 것을 특징으로 하는 패키지 모듈.The package module, characterized in that it further comprises a saw filter (SAW filter) mounted on the substrate. 제1항에 있어서,The method of claim 1, 상기 수동소자는 상기 기판에 내장되는 것을 특징으로 하는 패키지 모듈.The passive device is a package module, characterized in that embedded in the substrate. 제1항에 있어서,The method of claim 1, 상기 기판은 유기(organic)기판 또는 세라믹(ceramic) 기판인 것을 특징으로 하는 패키지 모듈.The substrate is a package module, characterized in that the organic substrate or a ceramic substrate (ceramic). 제1항에 있어서,The method of claim 1, 상기 기판의 타면에 형성되는 복수의 전극을 더 포함하는 것을 특징으로 하는 패키지 모듈.The package module further comprises a plurality of electrodes formed on the other surface of the substrate. 제5항에 있어서,The method of claim 5, 상기 복수의 전극에 각각 결합되는 도전성 볼을 더 포함하는 것을 특징으로 하는 패키지 모듈.The package module further comprises a conductive ball coupled to the plurality of electrodes, respectively.
KR1020070115652A 2007-11-13 2007-11-13 Package module KR20090049409A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563249A (en) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 Integrated packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563249A (en) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 Integrated packaging structure

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