KR20090047852A - Semiconductor light emitting device and fabrication method thereof - Google Patents

Abstract

An embodiment of the present invention relates to a semiconductor light emitting device.

According to an embodiment of the present invention, a semiconductor light emitting device may include: a substrate having an upper portion formed with a concave-convex pattern, and wherein at least one surface of the surface of the concave and convex pattern has a step structure; A first conductive semiconductor layer formed on the substrate; An active layer formed on the first conductive semiconductor layer; And a second conductive semiconductor layer formed on the active layer.

Semiconductor, Light Emitting Device, Substrate, Uneven Pattern

Description

Semiconductor light emitting device and method of manufacturing the same {Semiconductor light emitting device and fabrication method

An embodiment of the present invention relates to a semiconductor light emitting device and a method of manufacturing the same.

Group III-V nitride semiconductors are spotlighted as core materials of light emitting devices such as light emitting diodes (LEDs) or laser diodes (LDs) due to their physical and chemical properties.

Ⅲ-Ⅴ nitride semiconductor is made of a semiconductor material having a compositional formula of normal _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). It is widely used in the light emitting device for obtaining the light of the LED or LD using such a nitride semiconductor material, and is applied as a light source of various products such as keypad light emitting part of a mobile phone, an electronic board, a lighting device.

1 is a side cross-sectional view of a conventional nitride semiconductor light emitting device, in particular showing a nitride semiconductor light emitting diode (LED) device.

Referring to FIG. 1, the light emitting device 10 has a structure in which an n-type GaN layer 13, an active layer 15, and a p-type GaN layer 17 are sequentially stacked on a sapphire substrate 11. A portion of the n-type GaN layer 13 is exposed in the p-type GaN layer 17 by a mesa etching process. At this time, the n-side electrode 19 is formed on the exposed top surface of the n-type GaN layer 13, and the p-side electrode 21 is formed on the top surface of the p-type GaN layer 17.

Embodiments of the present invention provide a semiconductor light emitting device and a method of manufacturing the same, by forming a fine stepped structure on the surface of a yaw and / or iron pattern of a substrate, thereby preventing a decrease in ESD resistance.

An embodiment of the present invention provides a semiconductor light emitting device and a method of manufacturing the same, which can prevent degradation of the active layer by exposing a plurality of surfaces on the surface of the lens pattern of the substrate.

According to an embodiment of the present invention, a semiconductor light emitting device may include: a substrate having an upper portion formed with a concave-convex pattern, and wherein at least one surface of the surface of the concave and convex pattern has a step structure; A first conductive semiconductor layer formed on the substrate; An active layer formed on the first conductive semiconductor layer; And a second conductive semiconductor layer formed on the active layer.

According to an embodiment of the present invention, a semiconductor light emitting device includes: a first conductive semiconductor layer having a concave-convex pattern formed on a lower surface thereof, and wherein at least one surface of the concave and convex patterns has a step structure; An active layer formed on the first conductive semiconductor layer; And a second conductive semiconductor layer formed on the active layer.

A method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes forming an uneven pattern on an upper surface of a substrate, and forming at least one of the surfaces of the uneven and iron patterns in a step structure; Forming a first conductive semiconductor layer on the substrate; Forming an active layer on the first conductive semiconductor layer; Forming a second conductive semiconductor layer on the active layer.

According to the semiconductor light emitting device and the manufacturing method thereof according to the embodiment of the present invention, it is possible to prevent the generation of potential bundles on the substrate.

It can also improve LED reliability by preventing ESD immunity.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a side cross-sectional view of a semiconductor light emitting device according to a first exemplary embodiment of the present invention, FIG. 2 is a partial side cross-sectional view of the substrate of FIG. 1, and FIG. 3 is a plan view of FIG. 2.

2, the semiconductor light emitting device 100 may include a substrate 110 having an iron pattern 112 having a fine step structure 114 formed thereon, a buffer layer 120, an undoped semiconductor layer 130, and a first layer. The conductive semiconductor layer 140, the active layer 150, and the second conductive semiconductor layer 160 are included.

The substrate 110 may be selected from the group consisting of sapphire substrate (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, and GaAs, which will be described as an example of the sapphire substrate. The substrate 110 may be removed before or after forming the electrode of the light emitting device.

Concave-convex patterns 111 and 112 are integrally formed on the substrate 110, and the convex and concave patterns 112 may be formed in a protruding structure that may be formed by an etching process. It may be formed as a spaced apart branch structure. Here, the iron pattern 112 will be described as an example of a convex lens shape. The iron pattern 112 may be formed periodically or irregularly, the diameter is 1 ~ 5um and the height may be formed to 1 ~ 2um.

A step structure may be formed on a surface of at least one of the uneven patterns 111 and 112 of the substrate 110. As shown in FIGS. 3 and 4, a plurality of minute size step structures 114 are formed on the iron pattern 112 of the substrate 110 on the surface of the iron pattern 112. Although the step structure 114 is illustrated and described as being formed only on the surface of the iron pattern 112, the step structure 114 may be formed on the surface of the yaw pattern 111 or at least one surface of the yaw pattern 111 and the iron pattern 112. Can be.

The surface of the iron pattern 112 of the substrate 110 is a structure in which a portion of the surface is separated and exposed due to a difference in bonding strength with an external erase layer (not shown). At this time, the step structure 114 formed on the surface of the iron pattern 112 of the substrate 110 is exposed to the surface such that the vertical growth is well. The size of the step structure 114 may be formed to a nano size (for example, 10 ~ 90nm).

The buffer layer 120 is formed on the substrate 110. The buffer layer 120 is a layer for reducing the difference in lattice constant from the substrate 110, and is formed to a predetermined thickness (for example, 150 to 1000 Å) by using GaN, AlN, AlGaN, InGaN, AlInGaN, etc. An undoped semiconductor layer 130 may be formed on the buffer layer 120, and the undoped semiconductor layer 130 may be implemented as an undoped GaN layer. Only one of the layers 120 and the undoped semiconductor layer 130 may be formed or only one layer may be left, or both layers may not be formed.

The first conductive semiconductor layer 140 is formed on the undoped semiconductor layer 130. The first conductive semiconductor layer 140 is, for example, n-type to which may comprise a semiconductor layer, the n-type semiconductor layer is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0 ≤y A semiconductor material having a composition formula of ≤ 1, 0 ≤ x + y ≤ 1, for example, InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc., may be selected from the first conductive dopant (eg, Si, Ge, Sn, etc.) Is doped.

An active layer 150 is formed on the first conductive semiconductor layer 140, and the active layer 150 may be formed in a single or multiple quantum well structure. A conductive clad layer (not shown) may be formed on and / or under the active layer 150, and the conductive clad layer may be implemented as an AlGaN layer.

A second conductive semiconductor layer 160 is formed on the active layer 150, and the second conductive semiconductor layer 160 may be implemented as a p-type semiconductor layer, wherein the p-type semiconductor layer is In _x Al _y Ga. _{1 -x- y} N semiconductor materials having a composition formula of (0≤x≤1, 0 ≤y≤1, 0≤x + y≤1) , for example, InAlGaN, can be selected from GaN, AlGaN, InGaN, AlN, InN And a second conductive dopant (eg, Mg) is doped.

An electrode layer (not shown) may be formed on the first conductive semiconductor layer 140 and the second conductive semiconductor layer 160.

As described above, the uneven patterns 111 and 112 are formed on the substrate 110, the surface of the iron pattern 112 is formed of a step structure 114 having at least a surface, thereby the iron pattern 112 In order to reduce the critical angle from which light is extracted, the external light efficiency can be improved by improving the light extraction efficiency. In addition, since both the iron pattern 112 and the yaw pattern 111 of the step structure 114 having the [0001] surface can grow a nitride semiconductor layer such as the buffer layer 120, the potential bundle is prevented from being generated. It is possible to prevent the degradation of ESD resistance and to improve the quality of the active layer. This can solve the problem of a large amount of dislocation bundles due to the uneven structure of the existing substrate.

5 to 8 illustrate a method of manufacturing a semiconductor light emitting device according to the first embodiment of the present invention.

Referring to FIG. 5, the uneven patterns 111 and 112 are formed on the substrate 110. The substrate 110 may be selected from the group consisting of sapphire substrate (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, and GaAs, and may be removed before or after electrode formation of the light emitting device. Here, in the case of a sapphire substrate, a patterned sapphire substrate (PSS) pattern having a convex lens shape may be formed by an etching process. The etching process may be, for example, a dry etching method such as Reactive Ion Etching (RIE), Capacitively Coupled Plasma (CCP), Electron Cyclotron Resonance (ECR), Inductively Coupled Plasma (ICP), or the like.

An erase layer 115 made of a nitride semiconductor including aluminum (Al) is formed on the uneven patterns 111 and 112 of the substrate 110. The erase layer 115 may be formed of at least one of AlN, AlInN, and AlGaN, and may be formed on the substrate to have a predetermined thickness (for example, 100 to 800 μs). At this time, the erase layer 115 is difficult to initially have a thin film form due to the difference in lattice constant with the material of the sapphire substrate 110, is formed by agglomerated with each other in the form of granules. In this case, when the growth temperature of the erasing layer 115 is increased, the thin film may have a thickness of several hundred nm.

When the erase layer 115 is formed on the substrate, the growth chamber is thermally treated in a chlorine (HCI) gas atmosphere at a high temperature. In this case, as the erase layer 115 attached to the surface of the iron pattern 112 is vaporized to separate the surface of the iron pattern 112, as shown in FIG. 6, a plurality of surfaces of the iron pattern 112 are formed. Step structure 114 is formed. Since the step structure 114 is exposed, the GaN growth surface can be provided to the iron pattern 112. Here, the step structure as described above may also be formed on the surface of the yaw pattern 111, but does not significantly affect the GaN growth conditions are not shown and description thereof will be omitted.

In addition, the step structure 114 formed on the surface of the iron pattern 112 of the substrate 110 may be formed to a nano size (for example, 10 ~ 90nm), this size is the contact between the erase layer 115 and the substrate surface It can be proportional to the area being.

As shown in FIG. 7, the buffer layer 120 is formed on the uneven patterns 111 and 112 on the substrate 110 to have a predetermined thickness (for example, 150 to 1000 μs). Here, the buffer layer 120 is a layer for reducing the difference in the lattice constant with the substrate 110, GaN, AlN, AlGaN, InGaN, AlInGaN, etc. may be selectively formed. An undoped semiconductor layer 130 may be formed on the buffer layer 120, and the undoped semiconductor layer 130 may be implemented as an undoped GaN layer. Only one layer of the buffer layer 120 and the undoped semiconductor layer 130 or only one layer may be left on the substrate 110, or both layers may not be formed.

As shown in FIG. 8, a first conductive semiconductor layer 140 is formed on the undoped semiconductor layer 130. The first conductive semiconductor layer 140 is, for example, n-type to which may comprise a semiconductor layer, the n-type semiconductor layer is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0 ≤y A semiconductor material having a composition formula of ≤ 1, 0 ≤ x + y ≤ 1, for example, InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc., may be selected from the first conductive dopant (eg, Si, Ge, Sn, etc.) Is doped.

An active layer 150 is formed on the first conductive semiconductor layer 140, and the active layer 150 may be formed in a single or multiple quantum well structure. A conductive clad layer (not shown) may be formed on and / or under the active layer 150, and the conductive clad layer may be implemented as an AlGaN layer.

A second conductive semiconductor layer 160 is formed on the active layer 150, and the second conductive semiconductor layer 160 may be implemented as a p-type semiconductor layer. The p-type semiconductor layer may be In _x Al _y Ga. _{1 -x- y} N semiconductor materials having a composition formula of (0≤x≤1, 0 ≤y≤1, 0≤x + y≤1) , for example, InAlGaN, can be selected from GaN, AlGaN, InGaN, AlN, InN And a second conductive dopant (eg, Mg) is doped. Here, the transparent electrode layer may be further formed on the second conductive semiconductor layer 160.

First and second electrode layers (not shown) may be formed on the first conductive semiconductor layer 140 and the second conductive semiconductor layer 160.

FIG. 9 is a view showing a scanning electron microscope (SEM) image after growing about 0.5 μm of an undoped semiconductor layer on a substrate in the first embodiment, and FIG. 10 is a surface in which growth is completed up to the first conductive semiconductor layer in the first embodiment. Atomic Force Microscope (AFM) images are shown.

11 is a side cross-sectional view illustrating a semiconductor light emitting device 100A according to a second embodiment of the present invention.

Referring to FIG. 11, the uneven patterns 111 and 112 are formed on the substrate 110, and the step structure 114 is formed on the surface of the iron pattern 112. In this case, when the grain-shaped erasing layer (115 of FIG. 5) is partially removed without being completely removed on the surface of the iron pattern 112 of the substrate, the first conductive semiconductor layer 140 may be more effectively stacked. have. In other words, the partially remaining erase layer serves as the seed layer so that the semiconductor layer can be uniformly stacked on the entire region on the substrate.

A first conductive semiconductor layer 140 is formed on the substrate 110. The first conductive semiconductor layer 140 may include, for example, an n-type semiconductor layer, and is doped with a first conductive dopant.

An active layer 150 is formed on the first conductive semiconductor layer 140, and the active layer 150 may be formed in a single or multiple quantum well structure. A conductive clad layer (not shown) may be formed on and / or under the active layer 150, and the conductive clad layer may be implemented as an AlGaN layer.

A second conductive semiconductor layer 160 is formed on the active layer 150, and the second conductive semiconductor layer 160 may be implemented as a p-type semiconductor layer, and a second conductive dopant (eg, Mg) is doped. .

A third conductive semiconductor layer 165 is formed on the second conductive semiconductor layer 160. The third conductive semiconductor layer 165 is an n-type to which may comprise a semiconductor layer, the n-type semiconductor layer is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0 ≤y≤1 , 0 ≦ x + y ≦ 1), for example, InAlGaN, GaN, AlGaN, InGaN, AlN, InN, or the like, and a third conductive dopant (eg, Si, Ge, Sn, etc.) may be doped. do. A transparent electrode layer (not shown) may be formed on the third conductive semiconductor layer 165.

First and second electrode layers (not shown) may be formed on the first conductive semiconductor layer 140 and the third conductive semiconductor layer 165.

12 and 13 illustrate a process of manufacturing the semiconductor light emitting device 100B according to the third embodiment of the present invention. The semiconductor light emitting device 100B has a structure implemented as a vertical semiconductor light emitting device in which two electrode layers 145 and 170 corresponding to each other are disposed perpendicular to each other. In the description of such a semiconductor light emitting device, the position of the upper or lower layer will be described with reference to the drawings.

First, referring to FIG. 12, a step structure 114 is formed on a surface of at least one of the uneven patterns 111 and 112 of the substrate 110, and the first conductive semiconductor layer 150 is formed on the substrate 110. Is formed. Here, a buffer layer and an undoped semiconductor layer may be formed on the substrate 110 and both may be removed.

An active layer 150 is formed on the first conductive semiconductor layer 140, and a second conductive semiconductor layer 160 is formed on the active layer 150. The second electrode layer 170 is formed on the second conductive semiconductor layer 160. The conductive support substrate 180 is formed on the second electrode layer 170.

Thereafter, the substrate 110 is separated from the first conductive semiconductor layer 140 in a physical or / and chemical manner. For example, the substrate 110 may be separated from the first conductive semiconductor layer 140 in a laser lift off (LLO) manner.

As shown in FIG. 13, the conductive support substrate 180 is disposed under the semiconductor light emitting device 100B, and the first conductive semiconductor layer 140 is formed on the upper portion of the semiconductor light emitting device 100B. In this case, the concave-convex patterns 141 and 142 corresponding to the concave-convex patterns 111 and 112 of the substrate 110 of FIG. 12 are formed on the first conductive semiconductor layer 140, and the surface of the concave-convex concave pattern 142 is formed. It is formed of a step structure 144. The step structure 144 formed on the surface of the yaw pattern 142 of the first conductive semiconductor layer 140 may improve the external quantum efficiency.

The first electrode layer 145 is formed on the first conductive semiconductor layer 140. Although the semiconductor light emitting device 100B has been described with respect to the n-p junction structure, the semiconductor light emitting device 100B may also be manufactured with an n-p-n structure. Also, by doping the conductive dopant in the buffer layer on the substrate, a pattern corresponding to the uneven pattern of the substrate may be formed in the buffer layer.

In an embodiment of the present invention, it may be implemented as any one of a pn structure, an np structure, an npn structure, and a pnp structure. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on" or "under" the substrate, each layer (film), region, pad or patterns. In the case where it is described as being formed in, "on" and "under" include both the meaning of "directly" and "indirectly". In addition, the criteria for the top or bottom of each layer will be described with reference to the drawings.

The present invention has been described above with reference to the embodiments, which are merely examples and are not intended to limit the embodiments of the present invention. Those skilled in the art to which the embodiments of the present invention pertain have the essential characteristics of the present invention. It will be appreciated that various modifications and applications not illustrated above are possible without departing from the scope of the invention. For example, each component shown in detail in the embodiment of the present invention may be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a side cross-sectional view showing a conventional semiconductor light emitting device.

2 is a side cross-sectional view showing a semiconductor light emitting device according to the first embodiment of the present invention.

3 is a side cross-sectional view showing in detail the iron pattern of the substrate of FIG.

4 is a plan view of FIG.

5 to 8 are side cross-sectional views showing a semiconductor light emitting device according to the first embodiment of the present invention.

FIG. 9 is an image showing the surface of an undoped semiconductor layer on a substrate in the first embodiment. FIG.

FIG. 10 is a view showing a surface image formed up to a first conductive semiconductor layer in the first embodiment; FIG.

11 is a side cross-sectional view showing a semiconductor light emitting device according to a second embodiment of the present invention.

12 and 13 are side cross-sectional views illustrating a semiconductor light emitting device according to a third embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 100A, 100B: semiconductor light emitting device 110: substrate

111,142: yo pattern 112,141: iron pattern

114,144: Step Structure 115: Elimination Layer

120: buffer layer 140: first conductive semiconductor layer

145: first electrode layer 150: active layer

160: second conductive semiconductor layer 165: third conductive semiconductor layer

170: second electrode layer 180: conductive support substrate

Claims (13)

A substrate having an upper portion formed with a concave-convex pattern, and wherein at least one of the surfaces of the concave and convex pattern has a step structure; A first conductive semiconductor layer formed on the substrate; An active layer formed on the first conductive semiconductor layer; A semiconductor light emitting device comprising a second conductive semiconductor layer formed on the active layer. A first conductive semiconductor layer having a concave-convex pattern formed at a lower portion thereof, and having at least one of the surfaces of the concave and convex pattern formed in a step structure; An active layer formed on the first conductive semiconductor layer; A semiconductor light emitting device comprising a second conductive semiconductor layer formed on the active layer. The method according to claim 1 or 2, The step structure is a semiconductor light emitting device exposing at least a plane. The method according to claim 1 or 2, The pattern in which the step structure is formed is a semiconductor light emitting device formed in a concave or convex lens shape. The method according to claim 1 or 2, The step structure is a semiconductor light emitting device having a size of 10 ~ 90nm. The method of claim 1, A semiconductor light emitting device comprising at least one of a buffer layer and an undoped semiconductor layer formed on the substrate. The method according to claim 1 or 2, And at least one of a third conductive semiconductor layer, a conductive support substrate, a transparent electrode layer, and a second electrode layer formed on the second conductive semiconductor layer. Forming an uneven pattern on the substrate and forming at least one of the surfaces of the uneven and the uneven patterns in a step structure; Forming a first conductive semiconductor layer on the substrate; Forming an active layer on the first conductive semiconductor layer; And forming a second conductive semiconductor layer on the active layer. The method of claim 8, The step of forming a step structure on at least one surface of the surface of the yaw and iron pattern, Forming an uneven pattern on the substrate by an etching process; Forming an erase layer including Al on the substrate; And heat-treating the erase layer in a high temperature chlorine gas atmosphere to separate the substrate from the surface of the substrate to form a surface of the lens-shaped iron pattern in a stepped structure. The method of claim 9, The erase layer is a semiconductor light emitting device manufacturing method is formed of any one of AlInN, AlGaN and InGaN. The method of claim 8, And forming at least one of a buffer layer and an undoped semiconductor layer on the substrate. The method of claim 8, And forming at least one of a third conductive semiconductor layer, a transparent electrode layer, and an electrode layer on the second conductive semiconductor layer. The method of claim 8, And removing the substrate having the uneven pattern from the first conductive semiconductor layer.

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