KR20090047027A - Clock control circuit for testing of semiconductor circuit, method for controlling of clock for testing of semiconductor circuit and semiconductor device having the clock control circuit - Google Patents

Abstract

Disclosed are a clock control circuit for a semiconductor circuit test, a clock control method for a semiconductor circuit test, and a clock control circuit capable of testing a semiconductor circuit stably and reliably. The clock control circuit for a semiconductor circuit test outputs a test clock signal as an output clock signal in a shift period when the delay defect test enable signal is logic 'high' during a delay fault test, and launches a scan enable signal as logic 'low'. In the capture section, a delay fault test is performed by outputting an internal output clock signal including a clock pulse having the same frequency as a normal operating clock as an output clock signal, and a scan enable signal is logic 'low' and a delay fault test enable signal. If the logic is 'low', the delay fault test is not performed by preventing the internal output clock signal from being output during launch and capture periods. Therefore, the test can be performed independently for each test group of the semiconductor circuit, thereby making it possible to test the semiconductor circuit stably and reliably.

Semiconductor Circuits, Integrated Circuits, Test, Delay Faults, Freeze Faults, Clock Control

Description

Clock control circuit for semiconductor circuit test, clock control method for semiconductor circuit test, and semiconductor device having a clock control circuit (Clock Control Circuit For Testing Of Semiconductor Circuit, Method For Controlling Of Clock For Testing Of Semiconductor Circuit And Semiconductor Device Having The Clock Control Circuit}

The present invention relates to a test of a semiconductor circuit, and more particularly, a clock control circuit for a semiconductor circuit test, a clock control method and a clock control circuit for a semiconductor circuit test, which can improve test reliability and stability of a highly integrated semiconductor circuit. It relates to a semiconductor device having a.

As the integration of semiconductor devices increases and the operating speeds increase, the importance of testing a semiconductor device after fabrication of a semiconductor device to verify that the semiconductor device operates according to design intent and implementation specifications is increasing.

In particular, as the operating frequency of semiconductor circuits increases, the importance of delay defect testing is increasing, and various test methods for delay defect testing have been disclosed.

In general, in a delay defect test of a semiconductor circuit, a clock of a low speed (eg, 10 MHz) input from an outside of the semiconductor circuit is shifted in a shift section for inputting test data to increase test reliability. In the launch and capture periods for detecting delay defects in semiconductor circuits, clocks of the same high frequency (tens of tens to hundreds of MHz) that are used in the normal operation mode of the semiconductor circuits are used.

FIG. 1 shows a clock generation circuit for a conventional delay defect test, and FIG. 2 is a waveform diagram showing the operation of the clock generation circuit shown in FIG.

1 and 2, a clock generation circuit for a conventional delay defect test includes a low frequency test clock signal TCK provided externally for testing a semiconductor circuit and a scan activation signal SE activating a scan cycle. Scan scan mode signal (STM) and delay for selecting any one of a high frequency clock input signal (CLKI), an output clock signal (CLKO), and a clock input signal (CLKI) used during normal operation of a semiconductor circuit. An output clock signal CLKO for testing the semiconductor circuit is generated based on the defect enable signal DFE.

Specifically, the conventional clock generation circuit for the delay defect test includes a shift register 10 for shifting the scan enable signal SE in synchronization with the clock input signal CLKI, an output signal of the shift register 10, and a clock input. A logic gate 20 that generates a clock signal for a delay defect test of the semiconductor circuit based on the signal CLKI, a scan test mode signal STM, a scan enable signal SE, and a delay defect enable signal DFE. The switching unit 30 selects any one of a test clock signal TCK, an output of the logic gate 20, and a high frequency clock input signal CLKI, and outputs an output clock signal CLKO. .

Here, the clock input signal CLKI may use an output of a phase locked loop (PLL) provided in a semiconductor circuit to be subjected to a delay defect test, and has a frequency of several tens of MHz to several hundred MHz.

In addition, the scan activation signal SE is a logic 'high' in the shift period 50 for shifting the test data to a scan chain provided in the semiconductor circuit under test, and a logic 'low' in the launch and capture period 60. Have The delay fault enable signal DFE is set to logic 'high' during the delay fault test and to logic 'low' during other normal operations.

The clock generation circuit for the conventional delay defect test shown in FIG. 1 is synchronized to the output clock signal CLKO having the same frequency as the test clock signal TCK in the shift period 50 so that the test data is scanned in the scan chain. The output clock signal CLKO having the same frequency as the clock input signal CLKI at the first rising edge 61 and the second rising edge 63 of the load and capture interval 60 is loaded into the cell. After the test data is launched to the test target circuit at the first rising edge 61 in synchronization, the data output from the test target circuit is captured at the second rising edge 63.

If the data launched at the first rising edge 61 are not normally captured at the second rising edge 63, it is determined that the test data has a delay defect.

In the clock generation circuit for the conventional delay defect test as shown in FIG. 1, power noise is generated in the semiconductor circuit because the high frequency output clock signal output in the launch and capture periods is provided to the entire semiconductor circuit. More power may be generated than in normal operation, and power is also required more than in normal operation, and a value different from the expected value may be output, which may result in inaccurate test results. In addition, there is a problem in that the delay defect test cannot be performed by applying the clock generation circuit for the delay defect test to the entire semiconductor circuit due to the above disadvantage.

Accordingly, a first object of the present invention is to provide a clock control circuit for testing a semiconductor circuit capable of testing a semiconductor circuit stably and reliably.

In addition, a second object of the present invention is to provide a clock control method for testing a semiconductor circuit capable of testing a semiconductor circuit stably and reliably.

Further, a third object of the present invention is to provide a semiconductor device having a clock control circuit for the semiconductor circuit test.

A clock control circuit for testing a semiconductor circuit according to an aspect of the present invention for achieving the first object of the present invention described above, the first clock signal and at least one switching control signal based on the input at least one signal. A logic control unit to generate a first control signal for controlling whether the first clock signal is output based on a clock control unit to generate the first control signal and an output of the first clock signal based on the first control signal It includes a switching unit for switching. The clock controller is further configured to output a first switching control signal and the first switching signal for outputting any one of the first clock signal and a second clock signal having a first frequency based on the input at least one signal. The second switching control signal may be generated to output one of the output signal and the third clock signal having the second frequency. The clock controller generates a first switching control signal for outputting a second clock signal having a first frequency when the input scan activation signal is in a first logic state, and the input scan activation signal is in a second logic state. In this case, a second switching control signal for outputting the first clock signal may be generated. The logic calculator is configured to output the first clock signal when the test activation signal is in a first logic state, and not to output the first clock signal when the test activation signal is in a second logic state. A control signal can be generated. The switching unit outputs any one of the first clock signal, the second clock signal having a first frequency and the third clock signal having a second frequency based on the at least one switching control signal, and the at least one The one signal output based on the switching control signal of may be switched based on the first control signal. The clock control circuit for the semiconductor circuit test outputs a second clock signal having a first frequency when the first control signal is in a first logic state and the input scan activation signal is in a first logic state. When the scanned scan activation signal is in the second logic state, the first clock signal may be output. The clock control circuit for the semiconductor circuit test outputs a second clock signal having a first frequency when the first control signal is in a second logic state and the input scan activation signal is in a first logic state. When the input scan activation signal is in the second logic state, the first clock signal may not be output. The first clock signal may include two rising edges for launching test data into a test target circuit and capturing an output of the test target circuit.

In addition, the clock control method for testing a semiconductor circuit according to an aspect of the present invention for achieving the second object of the present invention generates a first clock signal and at least one switching control signal based on the input at least one signal. And generating a first control signal for controlling whether the first clock signal is output based on a test activation signal, and switching the output of the first clock signal based on the first control signal. It includes. The generating of the first clock signal and the at least one switching control signal may include generating a first switching control signal for outputting a second clock signal having a first frequency when the input scan activation signal is in a first logic state. And generating a second switching control signal for outputting the first clock signal when the input scan activation signal is in a second logic state. The generating of the first control signal may include outputting the first clock signal when the test activation signal is in a first logic state and outputting the first clock signal when the test activation signal is in a second logic state. The first control signal may be generated so as not to. The switching of the output of the first clock signal based on the first control signal may include the first clock signal, a second clock signal having a first frequency, and a second frequency based on the at least one switching control signal. The method may include a first step of outputting any one of a third clock signal having a and a second step of switching the signal output in the first step based on the first control signal.

In addition, a semiconductor device having a clock control circuit according to an aspect of the present invention for achieving the third object of the present invention, based on the input at least one signal and at least one switching control signal. A logic controller configured to generate a first control signal for controlling whether the first clock signal is output based on a clock control unit to generate the first control signal and a output signal of the first clock signal based on the first control signal; And at least one clock control circuit each including a switching unit for switching, and at least one test group independently performing a predetermined test based on first clock signals respectively output from the at least one clock control circuit. Each of the at least one test group may perform a predetermined test when the first clock signal is provided, and may not perform the predetermined test when the first clock signal is not provided. Each of the at least one test group may be distinguished by a criterion of at least one of clock relevance, integration, and circuit function.

According to the semiconductor device including the clock control circuit for the semiconductor circuit test, the clock control method for the semiconductor circuit test, and the clock control circuit, the delay defect test enable signal TDF_EN is logic 'high' during the delay defect test. The test clock signal TEST_CLK is output as the output clock signal CLK_OUT in the shift period in which the scan enable signal SE is logic 'high', and normal in the launch and capture period in which the scan enable signal SE is logic 'low'. The delay fault test of the semiconductor circuit may be performed by outputting the internal output clock signal CLK_O including the clock pulse having the same frequency as the operation clock as the output clock signal CLK_OUT.

Alternatively, when the scan enable signal SE is logic 'low' and the delay fault test enable signal TDF_EN is logic 'low', the delay fault test is performed by preventing the internal output clock signal CLK_O from being output in the launch and capture periods. Is not performed.

Therefore, the test can be performed independently for each test group of the semiconductor circuit, thereby reducing the possibility of test defects caused by obstacles such as power supply noise during the test of the semiconductor circuit.

In addition, high-density semiconductor circuits can be separated into smaller test groups and tests can be performed independently for each test group, enabling testing of semiconductor circuits in various combinations and reducing test vector development time for testing. . It also simplifies the verification and troubleshooting of test results by running tests independently for each test group.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In the following description of the present invention, the same reference numerals are used for the same elements in the drawings and redundant descriptions of the same elements will be omitted.

FIG. 3 illustrates a configuration of a clock control circuit for a semiconductor circuit test according to an exemplary embodiment of the present invention, and FIG. 4 illustrates a function table of the clock control circuit for the semiconductor circuit test illustrated in FIG. 3. 5 shows a timing diagram when the clock control circuit for testing the semiconductor circuit shown in FIG. 3 operates in the delay defect test mode.

3 to 5, a clock control circuit according to an embodiment of the present invention includes a clock controller 110, a logic calculator 120, a first switch 130, a second switch 140, and a first switch. 3 includes a switching unit 150, the clock input signal (CLK_IN), the test clock signal (TEST_CLK), the scan enable signal (SE), stuck defect test signal (SCAN_TEST), delayed defect test signal (TDF_TEST) and delayed defect test An output clock signal CLK_OUT is generated for testing the semiconductor circuit based on the activation signal TDF_EN.

The clock input signal CLK_IN is a clock signal having a frequency of tens to hundreds of MHz, and may be used as a clock signal for normal operation of a semiconductor circuit. The clock input signal CLK_IN may be a phase locked loop (PLL) provided in a semiconductor circuit under test. Can be provided through.

The test clock signal TEST_CLK is a low frequency (eg, 10 MHz) clock signal that is provided separately for the test of the semiconductor circuit and may be provided, for example, from a Joint Test Action Group (JTAG) controller or an external device of the semiconductor device. have.

The scan activation signal SE is a logic 'high' in the shift section 210 that shifts test data to scan test cells (not shown) of scan chains (not shown) configured inside the semiconductor circuit during a delay defect test of the semiconductor circuit. It is set to a logic 'low' in the launch and capture period 230 which launches and captures the shifted test data to the circuit under test.

Here, since the scan test cell corresponds to a known technique, although not shown in detail, the scan test cell is a kind of register installed inside the semiconductor circuit, and loads test data in synchronization with the clock of the shift period 210 of the output clock signal CLK_OUT. After shifting to another scan test cell connected to the scan chain, the test data is launched and captured in the test target circuit in synchronization with the clock of the output clock signal CLK_OUT and the clock of the capture period 230.

The stuck defect test signal SCAN_TEST is a signal that activates the stuck-at test of the semiconductor circuit. The stuck defect test signal SCAN_TEST is set to a logic 'high' during the stuck defect test, and is set to a logic 'low' in other cases.

The delay defect test signal TDF_TEST is a signal for activating a delay defect test of a semiconductor circuit. The delay defect test signal TDF_TEST is set to a logic 'high' for a delay defect test and a logic 'low' for a normal operation and a stuck defect test.

The delay defect test activation signal TDF_EN is a signal for controlling the output of a clock signal having the same frequency as the clock input signal CLK_IN in the launch and capture periods during the delay defect test of the semiconductor circuit.

The output clock signal CLK_OUT is provided to the scan test cells of the scan chain so that the test data can be shifted to a suitable position in the semiconductor circuit or launched and captured in the circuit under test.

Specifically, the clock control unit 110 is based on the clock input signal CLK_IN, the scan activation signal SE, the fixation defect test signal SCAN_TEST, the delay defect test signal TDF_TEST and the delay defect test activation signal TDF_EN. The internal output clock signal CLK_0, the first switching control signal MUX_C1, and the second switching control signal MUX_C2 are generated.

The internal output clock signal CLK_0 includes two clock pulses having the same frequency as the clock input signal CLK_IN in a predetermined period to test a delay defect using the same clock as in the normal operation of the semiconductor circuit. For example, it may be generated by performing a mask operation on a predetermined section of the clock input signal CLK_IN.

The logic operation unit 120 may be configured by a combination of an inverter (Not Gate) and an AND gate, and include a scan activation signal SE, a delay defect test signal TDF_TEST, and a delay defect test activation signal TDF_EN. Logic operation to generate a third switching control signal (MUX_C3).

The first switching unit 130 may be configured as a 21 multiplexer, and may be any one of the test clock signal TEST_CLK and the internal output clock signal CLK_0 based on the first switching control signal MUX_C1 provided from the clock control unit 110. Output one signal.

The second switching unit 140 may be configured of 21 multiplexers, and the output and the clock input signal CLK_IN of the first switching unit 130 based on the second switching control signal MUX_C2 provided from the clock control unit 110. Outputs any one of the signals.

The third switching unit 150 may be composed of 21 multiplexers, and any one of the second switching unit 140 and the logic 'low' signal based on the third switching control signal MUX_C3 provided from the logic calculating unit 120. Outputs the signal of.

As shown in FIG. 4, the clock control circuit according to an exemplary embodiment of the present invention may operate in a stuck defect test mode, a delayed defect test mode, and a normal operation mode, and in the stuck defect test mode, the stuck defect test signal SCAN_TEST. ) Is set to logic 'high' and the delay fault test signal is set to logic 'low'. In addition, regardless of the logic values of the scan activation signal SE and the delay defect test activation signal TDF_EN (that is, don't care), the clock control unit 110 generates a logic 'high' as the first switching control signal MUX_C1. Outputs a logic 'low' as the second switching control signal MUX_C2.

In addition, the logic operation unit 120 outputs a logic 'low' as the third switching control signal MUX_C3, so that the output clock signal CLK_OUT is a low-speed test clock signal TEST_CLK.

That is, in the fixed defect test mode, the clock control circuit tests a low frequency test by inputting predetermined test data into a predetermined test target circuit and checking whether or not the input test data is output regardless of delay time. The clock signal TEST_CLK is output as the output clock signal CLK_OUT.

In the delayed fault test mode, the stuck fault test signal SCAN_TEST is set to logic 'low', the delayed fault test signal TDF_TEST and the delayed fault test enable signal TDF_EN are set to logic 'high', and the scan enable signal SE is In the period set to logic 'high', that is, the shift period 210, the clock controller 110 outputs a logic 'high' as the first switching control signal MUX_C1 and a logic 'low' as the second switching control signal MUX_C2. Output ' The logic operation unit 120 outputs a logic 'low' as the third switching control signal MUX_C3, so that the output clock signal CLK_OUT outputs the test clock signal TEST_CLK.

In addition, the fixed defect test signal SCAN_TEST is set to logic 'low', the delayed defect test signal TDF_TEST and the delayed defect test enable signal TDF_EN are set to logic 'high', and the scan enable signal SE is set to logic 'low'. In the set period, that is, the launch and capture period 230, the clock controller 110 outputs a logic 'low' as the first switching control signal MUX_C1 and a logic 'low' as the second switching control signal MUX_C2. Outputs The logic operation unit 120 outputs a logic 'low' as the third switching control signal MUX_C3, so that the output clock signal CLK_OUT outputs the internal output clock signal CLK_O which is the output of the clock controller 110.

As shown in FIG. 5, the launch and capture period 230, in which the scan activation signal SE is set to a logic 'low', includes a first rising edge 231 and a second rising edge 233. The test data loaded in the scan test cell is launched in the test target circuit at the first rising edge 231, and the data output from the test target circuit is captured at the second rising edge 233.

In addition, in the normal mode, the scan enable signal SE, the stuck fault test signal SCAN_TEST, the delayed fault test signal TDF_TEST, and the delayed fault test enable signal TDF_EN are all set to logic 'low'. 110 outputs a logic 'high' as the second switching control signal MUX_C2, and the logic calculator 120 outputs a logic 'low' as the third switching control signal MUX_C3 to output the clock input signal CLK_IN. Output is by the output clock signal CLK_OUT.

In the clock control circuit for testing the semiconductor circuit according to the exemplary embodiment of FIG. 3, the scan enable signal SE is set to logic 'low' and the delay defect test signal TDF_TEST is set to logic 'high'. If set, when the delay defect test activation signal TDF_EN is set to a logic 'low', the logic operation unit 120 outputs a logic 'high' as the third switching control signal MUX_C3, thereby outputting the output clock signal CLK_OUT. ) Outputs a logic 'low' so that a clock signal having the same high frequency as the clock input signal CLK_IN is not generated.

6 is a block diagram illustrating a configuration of a semiconductor device having a clock control circuit according to an exemplary embodiment of the present invention. FIG. 7 is a diagram illustrating a delay defect test activation signal in the semiconductor device having the clock control circuit illustrated in FIG. 6. A timing diagram showing an output clock signal correspondingly output.

6 and 7, a semiconductor device having a clock control circuit according to an embodiment of the present invention may include a first clock control circuit 100, a second clock control circuit 200, and a third clock control circuit ( 300 may include a first test group 410, a second test group 420, a third test group 430, and a JTAG controller 510.

The first clock control circuit 100, the second clock control circuit 200, and the third clock control circuit 300 perform the same configuration and function as the clock control circuit for the semiconductor circuit test shown in FIG. The detailed description is omitted to avoid.

The clock input signal CLK_IN, the test clock signal TEST_CLK, the scan activation signal SE, and the fixation are attached to the first clock control circuit 100, the second clock control circuit 200, and the third clock control circuit 300, respectively. The defect test signal SCAN_TEST and the delayed defect test signal TDF_TEST are commonly input.

The first clock control circuit 100 generates a first output clock signal CLK_OUT_G1 based on the common input signals (ie, CLK_IN, TEST_CLK, SE, SCAN_TEST, and TDF_TEST) and the first delayed defect test activation signal TDF_EN_G1. It generates and provides it to the first test group 410.

The second clock control circuit 200 may generate a second output clock signal CLK_OUT_G2 based on the common input signals (ie, CLK_IN, TEST_CLK, SE, SCAN_TEST, and TDF_TEST) and the second delay defect test activation signal TDF_EN_G2. It generates and provides it to the second test group 420.

The third clock control circuit 300 receives a third output clock signal CLK_OUT_G3 based on the common input signals (ie, CLK_IN, TEST_CLK, SE, SCAN_TEST, and TDF_TEST) and the third delayed defect test activation signal TDF_EN_G3. It generates and provides it to the third test group 430.

The first test group 410, the second test group 420, and the third test group 430 may each include at least one scan test cell and a test target circuit forming a scan chain, and the first output In the shift period 610, test data is loaded into at least one scan test cell in synchronization with the clock signal CLK_OUT_G1, the second output clock signal CLK_OUT_G2, and the third output clock signal CLK_OUT_G3, respectively. At the first rising edge 631 of 630, test data is launched from the at least one scan test cell to the circuit under test and data output from the circuit under test at the second rising edge 633 is captured to delay test. Is performed.

Since the configuration and function of the Joint Test Action Group (JTAG) controller are well-known technologies, they are not shown in detail, but signals input through the JTAG port (TCK: Test Clock, TMS: Test Mode Select, TDI: Test Data Input, TRST_N). : Fixation fault test signal SCAN_TEST, delay fault test signal TDF_TEST, first delay fault test enable signal TDF_EN_G1, second delay fault test enable signal TDF_EN_G2 based on Test Reset, TDO: Test Data Output And a third delay defect test activation signal TDF_EN_G3.

The JTAG controller can be programmed and controlled through the JTAG port, depending on the test mode and test group of the semiconductor circuit.

For example, when a delay fault test is to be performed only for a circuit belonging to the first test group, the JTAG controller may determine that the stuck fault test signal SCAN_TEST is logic 'low' and the delay fault test signal TDF_TEST is logic 'high'. The first delayed defect test activation signal TDF_EN_G1 is logic 'high', the second delayed defect test activation signal TDF_EN_G2 is logic 'low', and the third delayed defect test activation signal TDF_EN_G3 is logic 'low'. It is programmed to

The first test group 410, the second test group 420, and the third test group 430 illustrated in FIG. 6 may be configured as clocks in a highly integrated semiconductor circuit (eg, a very large scale integration (VLSI)). The test group is divided according to the association, the function of the circuit and / or the degree of integration of the circuit. The test is independently performed according to the first output clock signal CLK_OUT_G1, the second output clock signal CLK_OUT_G2, and the third output clock signal CLK_OUT_G3. Can be performed.

For example, as shown in FIG. 7, when the delay defect test is performed only on the first test group 410 and the third test group 430, the first delay defect test activation signal TDF_EN_G1 and the third delay are performed. The fault test enable signal TDF_EN_G3 is set to logic 'high' and the second delay fault test enable signal TDF_EN_G2 is set to logic 'low' to launch and capture the scan enable signal SE is logic 'low'. In the period 630, the first output clock signal CLK_OUT_G1 and the third output clock signal CLK_OUT_G3 are generated by a clock signal having the same frequency as the clock input signal CLK_IN, but the second output clock signal CLK_OUT_G2 is logic. It is set to 'low'.

That is, when the delay defect test is performed only on the first test group 410 and the third test group 430, the launch and capture intervals of the first output clock signal CLK_OUT_G1 and the third output clock signal CLK_OUT_G3 may be The high frequency clock signal including the first rising edge 631 and the second rising edge 633 is included in the 630 such that the first test group 410 and the third test group 430 simultaneously perform a delay defect test. However, since the second output clock signal CLK_OUT_G2 is set to a logic 'low', the second test group 420 does not perform the delay defect test.

As shown in FIG. 6 and FIG. 7, a semiconductor device having a clock control circuit according to an exemplary embodiment of the present invention may include a semiconductor circuit in at least one test group according to a clock correlation, a circuit function, and / or an integration degree. And control the output clock signals (e.g., CLK_OUT_G1, CLK_OUT_G2, CLK_OUT_G3) provided to each test group according to the delayed fault test activation signals (e.g., TDF_EN_G1, TDF_EN_G2, TDF_EN_G3). Delay fault tests can be performed independently.

For example, when the delay defect test cannot be performed in the first test group 410 due to factors such as power noise, the second test group 420 and the third test group 430 may not be used. 1 Irrespective of the test group 410, a delayed defect test may be performed, thereby minimizing loss of a test area.

In addition, since the delay defect test for each test group can be independently performed, error occurrence factors such as power supply noise can be minimized, and test reliability is improved.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 shows a clock generation circuit for a conventional delay defect test.

FIG. 2 is a waveform diagram illustrating an operation of the clock generation circuit of FIG. 1.

3 illustrates a configuration of a clock control circuit for a semiconductor circuit test according to an embodiment of the present invention.

FIG. 4 shows a function table of the clock control circuit for the semiconductor circuit test shown in FIG. 3.

FIG. 5 shows a timing diagram when the clock control circuit for testing the semiconductor circuit shown in FIG. 3 operates in the delay defect test mode.

6 is a block diagram illustrating a configuration of a semiconductor device having a clock control circuit according to an exemplary embodiment of the present invention.

FIG. 7 is a timing diagram illustrating an output clock signal output in correspondence with a delay defect test activation signal in the semiconductor device having the clock control circuit illustrated in FIG. 6.

<Explanation of symbols for the main parts of the drawings>

100: first clock control circuit 110: clock control unit

120: logic operation unit 130: first switching unit

140: second switching unit 150: third switching unit

159: shared memory area 200: second clock control circuit

300: third clock control circuit

Claims (19)

A clock controller configured to generate a first clock signal and at least one switching control signal based on the input at least one signal; A logic calculator configured to generate a first control signal for controlling whether the first clock signal is output based on a test activation signal; And And a switching unit for switching the output of the first clock signal based on the first control signal. The method of claim 1, wherein the clock control unit A first switching control signal for outputting any one of the first clock signal and a second clock signal having a first frequency based on the input at least one signal and an output based on the first switching signal And a second switching control signal for outputting any one of a signal and a third clock signal having a second frequency. The method of claim 1, wherein the clock control unit When the input scan activation signal is in a first logic state, a first switching control signal is generated to output a second clock signal having a first frequency; and when the input scan activation signal is in a second logic state, And a second switching control signal for outputting a first clock signal. The logic calculation unit of claim 1, wherein the logical operation unit The first clock signal is output when the test activation signal is in a first logic state, and the first control signal is generated so that the first clock signal is not output when the test activation signal is in a second logic state. A clock control circuit for testing a semiconductor circuit, characterized in that. The method of claim 1, wherein the switching unit Outputs any one of the first clock signal, a second clock signal having a first frequency, and a third clock signal having a second frequency based on the at least one switching control signal, and the at least one switching control And switching the one signal output based on the signal based on the first control signal. The clock control circuit of claim 1, wherein the clock control circuit for testing the semiconductor circuit comprises: When the first control signal is in a first logic state and the input scan activation signal is in a first logic state, a second clock signal having a first frequency is output, and the input scan activation signal is in a second logic state. And outputting the first clock signal. The clock control circuit of claim 6, wherein the clock control circuit for testing the semiconductor circuit comprises: When the first control signal is in a second logic state and the input scan activation signal is in a first logic state, a second clock signal having a first frequency is output, and the input scan activation signal is in a second logic state. The control circuit of claim 1, wherein the first clock signal is not output. The method of claim 1, wherein the first clock signal is And two rising edges for launching test data into the circuit under test and capturing the output of the circuit under test. Generating a first clock signal and at least one switching control signal based on the at least one input signal; Generating a first control signal for controlling whether the first clock signal is output based on a test activation signal; And Switching the output of the first clock signal based on the first control signal. The method of claim 9, wherein generating the first clock signal and the at least one switching control signal comprises: Generating a first switching control signal for outputting any one of the first clock signal and a second clock signal having a first frequency based on the input at least one signal; And And generating a second switching control signal for outputting any one of a signal output based on the first switching signal and a third clock signal having a second frequency. Clock control method. The method of claim 9, wherein generating the first clock signal and the at least one switching control signal comprises: Generating a first switching control signal for outputting a second clock signal having a first frequency when the input scan activation signal is in a first logic state; And And generating a second switching control signal for outputting the first clock signal when the input scan activation signal is in a second logic state. 10. The method of claim 9, wherein generating the first control signal The first clock signal is output when the test enable signal is in a first logic state, and the first control signal is generated so that the first clock signal is not output when the test enable signal is in a second logic state. A clock control method for testing a semiconductor circuit, characterized in that. The method of claim 9, wherein the switching of the output of the first clock signal based on the first control signal comprises: A first step of outputting any one of the first clock signal, a second clock signal having a first frequency, and a third clock signal having a second frequency based on the at least one switching control signal; And And a second step of switching the signal output in the first step based on the first control signal. A clock controller configured to generate a first clock signal and at least one switching control signal based on the at least one input signal; and a first control signal for controlling whether to output the first clock signal based on a test activation signal; At least one clock control circuit each including a logic operation unit to generate and a switching unit to switch an output of the first clock signal based on the first control signal; And And a clock control circuit including at least one test group in which predetermined tests are independently performed based on first clock signals respectively output from the at least one clock control circuit. The method of claim 14, wherein each of the at least one test group performs a predetermined test when the first clock signal is provided, and does not perform the predetermined test when the first clock signal is not provided. A semiconductor device having a clock control circuit, characterized in that. 15. The semiconductor device according to claim 14, wherein each of said at least one test group is divided by a criterion of at least one of clock correlation, integration, and circuit function. 15. The circuit of claim 14, wherein the clock control circuit is When the first control signal is in a first logic state and the input scan activation signal is in a first logic state, a second clock signal having a first frequency is output, and the input scan activation signal is in a second logic state. And a clock control circuit for outputting the first clock signal. 18. The circuit of claim 17, wherein the clock control circuit for testing the semiconductor circuit is When the first control signal is in a second logic state and the input scan activation signal is in a first logic state, a second clock signal having a first frequency is output, and the input scan activation signal is in a second logic state. And the first clock signal is not output. 15. The semiconductor device of claim 14, wherein the semiconductor device including the clock control circuit is formed. And a JTAG (Joint Test Action Group) controller configured to provide the at least one signal and the test activation signal input to the clock controller in accordance with a test mode of the semiconductor device. Semiconductor device.

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