KR20090045614A - Semiconductor device for checking mode register set - Google Patents

Abstract

The present invention is to measure the setup / hold time for setting a mode register set (MRS) in a semiconductor memory device and to check whether the set value is appropriate. In accordance with another aspect of the present invention, a semiconductor memory device includes a mode register set for storing information for controlling an operation in a code form, a register for receiving a code set in a mode register set, a code for temporarily comparing a code temporarily stored in a register with a currently applied code. Comparing unit, and a result storage unit for outputting the comparison result output from the comparison unit to the outside. Through this, the present invention can determine the setup and hold time required for setting the mode register set (MRS), and the conditions and inappropriate setting values for the case where the setting of the mode register set (MRS) becomes incomplete.

Semiconductors, Mode Register Set (MRS), Extended Mode Register Set (EMRS), Memory, Test

Description

Semiconductor device for mode register set check {SEMICONDUCTOR DEVICE FOR CHECKING MODE REGISTER SET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mode register set (MRS) in a semiconductor memory device, and more particularly, to a semiconductor device capable of checking a value set in a mode register set and testing an error during a test process.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

BACKGROUND OF THE INVENTION As the operating speed of a system composed of semiconductor devices becomes faster and technology related to semiconductor integrated circuits develops, semiconductor memory devices have been required to output or store data at a higher speed. In order to store larger amounts of data and operate at higher speeds, semiconductor memory devices are setting the information that is required or required for performing various operations, such as burst length (BL) and casing. Latency (CAS Latency, CL), write latency (Write Latency, WL) and the like.

The semiconductor memory device performs a power-up sequence to determine an operation mode after receiving a power supply voltage, and sets various values in a mode register set (MRS). Specifically, the semiconductor memory device sets various values in the mode register set MRS by using an MRS code input through a plurality of address pins when an MRS command for setting the mode register set MRS is applied. Meanwhile, as the internal operation of the semiconductor memory device becomes more complicated and the types thereof increase, values that need to be set during the initial operation of the semiconductor memory device, such as newly added additional latency (AL), have increased. Therefore, it is difficult to store various information for determining the operation mode and controlling the performance of the operation only by the existing mode register set (MRS) alone, so that the semiconductor memory device extends the existing mode register set (MRS). (Extended Mode Register Set, EMRS) has been provided, and due to the recent increase in the number of versions, such as EMRS, EMRS2, EMRS3, etc. are also used.

In order to ensure operational reliability of the semiconductor memory device, it is necessary to confirm whether the mode register set (MRS) is properly set. To this end, indirect methods have been conventionally used. Here, the indirect method refers to a method of determining whether the mode register set (MRS) is normally set by performing a variety of operations after setting the mode register set (MRS) and looking at the result or the effect. For example, by checking the output of data transmitted internally in a read operation such as cas latency (CL), it is possible to check whether data is output at a predetermined time, or by checking the delay effect using cas latency (CL). If the result is obvious, it can be determined whether the setting is desirable. However, in the case of a value set in the mode register set (MRS) that determines the amount of internal current flowing in the semiconductor memory device, it may be difficult to accurately distinguish whether or not the MRS is set by this indirect method.

Therefore, in the conventional indirect method, it is very difficult to check whether all the setting values of the mode register set (MRS) are correctly set, which is cumbersome or difficult when debugging after the test. Indirectly, the setup / hold time of a mode register set (MRS) is determined during a power-up sequence for determining an operation mode after a power supply voltage is applied. It is also difficult to measure.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and detects an abnormal value by measuring a setup / hold time for setting a mode register set (MRS) in a semiconductor memory device and checking whether the set value is appropriate. The purpose of the present invention is to provide an MRS setting inspection device.

The present invention provides a mode register set for storing information for controlling an operation in code form, a register for receiving a code set in the mode register set, a comparator for comparing a code temporarily stored in a register with a currently applied code, and a comparison. A semiconductor memory device having a result storage unit for outputting a comparison result output from a unit to an external device is provided.

The present invention also provides a mode register set for storing basic information for controlling an operation in code form, one or more extension mode register sets for storing additional information for controlling the operation in addition to basic information, and a mode register. A plurality of mode register set checking circuits for storing a predetermined code and outputting a comparison result when the mode applying signal is activated corresponding to each of the set and the extended mode register sets, and comparing the code with the currently applied code, and a mode register set checking circuit. Provided is a semiconductor memory device having a plurality of data pads for selectively outputting each output and data transferred therein in response to a mode check signal.

Furthermore, the present invention corresponds to each of a set of mode registers for storing basic information for controlling an operation in code form and one or more extended mode register sets for storing additional information for controlling the operation in addition to basic information. And storing the predetermined code when the mode applying signal is activated, comparing the currently applied code, and outputting the comparison result, and selectively outputting the comparison result to the outside in response to the mode check signal. A test method of a memory device is provided.

According to the present invention, unlike the indirect method of estimating the code set in the mode register set (MRS) as an effect or result after the conventional mode register set (MRS) is set, the direct mode register set (MRS) is not checked through an indirect method. ) You can check the set value. The mode register set (MRS) is set in the initial process after the power is supplied, the direct method proposed in the present invention is to insert the internal additional circuit code of the currently applied mode register set (MRS) and the previously set mode The code in the register set (MRS) is compared directly and the result of the comparison is output through the data pin for monitoring. In this direct method, comparing the code of the currently applied mode register set (MRS) with the code of a previously stored mode register set (MRS) may not make much sense, but the mode register sets in different environments under test It is possible to measure the setup / hold time by setting the code of (MRS) and to check the set code directly.If the setting of the mode register set (MRS) is delayed or fails, the repetitive mode register set (MRS) By setting up and monitoring the code in), you can obtain meaningful results for environmental conditions that fail to configure and for debugging.

The present invention relates to the setting of the mode register set (MRS), conditions and inappropriate setting values for the measurement of the setup / hold time required for the mode register set (MRS) and the setting of the mode register set (MRS) becomes incomplete This can be useful for debugging and to help debug the code in the mode register set (MRS).

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 is a block diagram illustrating a mode register set checking circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

As shown, the semiconductor memory device according to an embodiment of the present invention stores a predetermined code when the mode applying signal load_mrs is activated corresponding to each of the mode register set and the extended mode register set, and compares it with the currently applied code. Outputs the data of each of the plurality of mode register set checking circuits 100_0 to 100_3 and the mode register set checking circuits 100_0 to 100_3 to output the comparison results (mrs_result, emrs1_result, emrs2_result, and emrs3_result). And a plurality of data pads 200_0 to 200_3 for selectively outputting the included information dq0_out_org to the outside in response to the mode check signal mon_en. In addition, although not shown, the semiconductor memory device may include a mode register set (MRS) for storing basic information for controlling an operation in a code form, and additional information for controlling the operation in addition to the basic information in code form. The extended mode register set (EMRS) is included. For example, the mode register set (MRS) stores basic information including the cascade latency (CL), and the extended mode register set (EMRS) stores additional information including additional latency (AL).

The present invention compares a currently applied code with a previously stored code so that the result can be output and monitored through an external pin. To this end, the proposed plurality of mode register set checking circuits 100_0 to 100_3 correspond to each of the mode register set MRS and the plurality of extended mode register sets MRS, EMRS1, EMRS2, and EMRS3 included in the semiconductor memory device. The illustrated number is only one example and can be changed according to the configuration of the semiconductor memory device. In addition, the data pads DQ0, DQ1, DQ2, and DQ3 included in the semiconductor memory device are allocated as the plurality of data pads 200_0 to 200_3, but this is only one example and may be changed according to the configuration and layout of the semiconductor memory device. This is possible. Furthermore, although the code set in the mode register set (MRS) is assumed to be 8 bits and described, it can be changed according to the design of the semiconductor memory device.

The configuration of each of the plurality of mode register set check circuits 100_0 to 100_3 is the same as shown. Hereinafter, the configuration and operation of the first mode register set checking circuit 100_0 corresponding to the mode register set MRS will be described.

The first mode register set checking circuit 100_0 receives a predetermined code of the mode register set MRS transmitted in response to the mode applying signal load_mrs, and a code mrs_reg <0: temporarily stored in the register. 7>) and the mode applying signal (load_mrs) as much as the time required to perform the comparison operation in the comparator 140 and the comparator 140 for comparing the currently applied code through the input terminal mrs_opcode <0: 7> A delay unit 160 for delaying the result, a result storage unit 180 for outputting the comparison result mrs_comp output from the comparator 140 in response to an external clock, and an output load_mrs_d of the delay unit 160. Correspondingly, the first multiplexer 170 may be configured to transmit the comparison result mrs_comp to the result storage unit 180 or to feed back the output of the result storage unit 180. In particular, the code of the preset mode register set MRS and the currently applied code are transmitted to the first mode register set checking circuit 100_0 through one input terminal mrs_opcode <0: 7>. To this end, the first mode register set check circuit 100_0 transmits a second multiplexer 110 to transfer a predetermined code in response to the mode application signal load_mrs or to feed back the output of the register 120. It includes more.

Each data pad 200_0 further includes a third multiplexer for selectively outputting information including data, etc., and an output mrs_result of the first mode register set check circuit 100_0 corresponding to the mode check signal mon_en. 220. For reference, the mode applying signal load_mrs and the mode check signal mon_en are generated in units of periods of the external clock clk, which applies an external clock clk of various frequencies in the test / monitoring mode. This is because the test results can be obtained.

FIG. 2 is a circuit diagram illustrating the comparison unit 140 shown in FIG. 1.

As shown in the drawing, the comparison unit 140 generates a logical low level result (mrs_comp) when all bits of the two input codes mrs_opcode <0: 7> and mrs_reg <0: 7> are the same. ), And outputs the result of the logical high level (mrs_comp) if it is not the same (if the logic value differs by at least one bit or more).

In detail, a plurality of first logic gates XNOR for performing an exclusive negation operation on bits corresponding to two input 8-bit codes mrs_opcode <0: 7> and mrs_reg <0: 7>, respectively, And performing a negative OR operation on the outputs of the plurality of second logic gates NAND and the outputs of the plurality of second logic gates NAND for performing an AND operation on the outputs of the plurality of first logic gates XNOR. A plurality of third logic gates (NOR) for, and a fourth logic gate (NAND) for performing a negative AND operation on the output of the plurality of third logic gate (NOR).

3 is a circuit diagram illustrating the result storage unit 180 illustrated in FIG. 1.

As illustrated, the result storage unit 180 may store the comparison result input corresponding to the external clocks clk and clkb and output the result of mrs_result. The result storage unit 180 includes a plurality of transmission gates for transmitting signals input corresponding to the external clocks clk and clkb, and a plurality of inverter latches for latching values transmitted from the plurality of transmission gates. .

The result storage unit 180 described above may be configured as a conventional flip-flop, and the result storage unit of the present invention is not limited to the illustrated configuration, but the circuit may be configured by various methods well known to those skilled in the art.

4 is a circuit diagram illustrating the register 120 shown in FIG. 1.

As shown, the register 120 can be designed in a manner very similar to the internal configuration of the result storage 180. However, unlike the result storage unit 180 that temporarily stores a comparison result (mrs_comp) of one bit, the register 120 must store an 8-bit code, and thus, the register 120 must be configured with a plurality of flip-flops corresponding to each bit.

FIG. 5 is a circuit diagram illustrating the delay unit 160 illustrated in FIG. 1.

As shown, the delay unit 160 is composed of a plurality of inverters connected in series. However, the total delay time that the delay unit 160 delays the mode applying signal load_mrs is required by the comparing unit 140 to compare the two codes mrs_opcode <0: 7> and mrs_reg <0: 7>. It must be the same as the time. In the present invention, as long as the comparison unit 140 outputs the comparison result mrs_comp through four logical operations, the delay unit 160 should also be configured with four inverters.

FIG. 6 is a circuit diagram for describing the second multiplexer 110 illustrated in FIG. 1.

As illustrated, the second multiplexer 110 may convert an inverter for inverting the mode applying signal load_mrs and two input codes mrs_opcode <0: 7> and mrs_reg <0: 7> to the mode applying signal load_mrs. And a plurality of transmission gates for transferring corresponding to the logic level. This is because there are eight pairs of transmission gates, and the second multiplexer 110 must be able to transfer bits of each of two codes (mrs_opcode <0: 7> and mrs_reg <0: 7>).

7 and 8 are waveform diagrams for explaining the operation of the mode register set checking circuit shown in FIG. Specifically, FIG. 7 illustrates a case where the same code as the preset code is input to the mode register set (MRS), and FIG. 8 illustrates a case where a code different from the preset code is input to the mode register set (MRS). It is for.

First, referring to FIG. 7, the mode applying signal load_mrs indicating that the code inputted from the preset mode register set MRS is loaded on the input terminal mrs_opcode <0: 7> is activated for one period of the external clock clk. It is. The code at the input terminal mrs_opcode <0: 7> is stored in the register 120 while the mode application signal load_mrs is at a logic high level. Here, the code mrs_reg <0: 7> stored in the register 120 stores a preset value 'A' outputted from the mode register set MRS, and the value mrs_reg <0 stored in the register 120. (7>) is updated to a new value only when the mode applying signal load_mrs is activated to a logic high level and the external clock clk is on the rising edge. Thereafter, the newly input code 'A' is applied through the input terminal mrs_opcode <0: 7>, and the comparison unit 140 compares the two codes. The comparator 140 outputs the comparison result mrs_comp at a logic low level since the two codes have the same value, and the comparison result mrs_comp corresponds to the output load_mrs_d of the delay unit 160. The result is stored in the result storage unit 180 through the multiplexer 170. The value mrs_comp_d stored in the result storage unit 180, that is, the output of the first mode register set check circuit 100_0 (mrs_result) is transmitted to the data pad 200_0 and the mode check signal mon_en is logic high ( It is active at the high level and is output externally through the pin (dq0_out).

On the contrary, as shown in FIG. 8, when the values of the two codes are different ('A' and 'B'), the comparison result is output at a logic high level. The rest of the operations are the same as those in FIG.

Here, the mode check signal mon_en is activated at a logic high level. The mode check signal mon_en may be input to a semiconductor memory device through a pin. You can also create a value and use it.

Through the above-described process, the level of the signal output through the pin can be determined by the test equipment to determine whether the code in the mode register set (MRS) is preferably set. In addition, a setup / hold in which the code preset in the mode register set (MRS) and the extended mode register set (EMRS) is set up in the semiconductor memory device by comparing with an externally applied code every time the operation mode is changed after the application of the power supply voltage. setup / hold) time can be measured. The setup / hold time measured by the present invention can be utilized for debugging a mode register set (MRS).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram illustrating a mode register set checking circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the comparison unit shown in FIG. 1.

FIG. 3 is a circuit diagram illustrating the result storage unit shown in FIG. 1.

FIG. 4 is a circuit diagram for describing the register shown in FIG. 1.

FIG. 5 is a circuit diagram illustrating the delay unit illustrated in FIG. 1.

FIG. 6 is a circuit diagram for describing the second multiplexer illustrated in FIG. 1.

7 and 8 are waveform diagrams for explaining the operation of the mode register set checking circuit shown in FIG.

Claims (14)

A mode register set for storing information in code form for controlling the operation; A register to receive a code set in the mode register set; A comparator for comparing a code temporarily stored in the register with a currently applied code; And And a result storage unit for outputting the comparison result output from the comparison unit to the outside. The method of claim 1, And the register and the result storage unit are flip-flops. The method of claim 2, And the comparator outputs a logic low level when two input codes have the same value, and outputs a logic high level when the two codes are not identical. The method of claim 3, wherein And a multiplexer for selectively outputting a comparison result temporarily stored in the result storage unit through a data pad, and selectively outputting the internally output data and the comparison result in response to a mode check signal. A mode register set for storing basic information for controlling an operation in code form; One or more extended mode register sets for storing, in code form, additional information for controlling the operation in addition to the basic information; A plurality of mode register set checking circuits for storing a predetermined code and outputting a comparison result when a mode applying signal is activated corresponding to each of the mode register set and the extended mode register set, and comparing the currently applied code; And And a plurality of data pads for selectively outputting the output of each of the mode register set check circuits and data transferred therein to the outside in response to a mode check signal. The method of claim 5, And the mode register set stores basic information including cas latency, and the extended mode register set stores additional information including additional latency. The method of claim 5, The mode register set checking circuit A register receiving the predetermined code transmitted in response to the mode applying signal; A comparison unit for comparing the code temporarily stored in the register with the currently applied code; A delay unit for delaying the mode applying signal by the comparison time of the comparison unit; A result storage unit for outputting a comparison result output from the comparison unit corresponding to an external clock; And And a first multiplexing unit configured to transfer the comparison result to the result storage unit or to feed back the output of the result storage unit in response to the output of the delay unit. The method of claim 7, wherein The mode register set checking circuit And a second multiplexer configured to transfer the predetermined code in response to the mode applying signal or to feed back the output of the register. The method of claim 8, And the register and the result storage unit are flip-flops. The method of claim 9, And the comparator outputs a logic low level when two input codes have the same value, and outputs a logic high level when the two codes are not identical. The method of claim 5, And the data pad includes a multiplexer for selectively outputting the data and the output of the mode register set check circuit in response to a mode check signal. A mode register signal corresponding to each of a set of mode registers for storing basic information for controlling an operation in code form and one or more set of extended mode registers for storing additional information for controlling the operation in addition to the basic information in code form When is activated, storing a preset code and comparing the currently applied code to output a comparison result; And And selectively outputting the comparison result to the outside in response to a mode check signal. The method of claim 12, The step for outputting the comparison result is Temporarily storing the predetermined code transmitted in response to the mode applying signal; Comparing the temporarily stored code with the currently applied code; Delaying the mode applying signal by the time required in the comparison process; And And transmitting and temporarily storing the comparison result in response to the delayed signal. The method of claim 13, The result of the comparison is a test method of a semiconductor memory device, characterized in that for outputting a logic low level if the two code values are the same, and outputs a logic high level if they are not the same.

Images